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	// implemented per N2 ras
	// 16b data, 6b checkbits
	// cor_parity_5 use in correction logic;
	// special bit5 generation in correction mode 
module niu_smx_ecc16_genpar (data, chkbit, parity, cor_parity_5);

input  [15:0] data;
input [4:0] chkbit; // use for correct logic; bit5 is different
output [5:0] parity;
output cor_parity_5;

assign parity[0] = data[0] ^ data[1] ^ data[3] ^ data[4] ^ data[6] ^ 
		   data[8] ^ data[10] ^ data[11] ^ data[13] ^ data[15];

assign parity[1] = data[0] ^ data[2] ^ data[3] ^ data[5] ^ data[6] ^ 
		   data[9] ^ data[10] ^ data[12] ^ data[13];

assign parity[2] = data[1] ^ data[2] ^ data[3] ^ data[7] ^ data[8] ^ 
		   data[9] ^ data[10] ^ data[14] ^ data[15];

assign parity[3] = data[4] ^ data[5] ^ data[6] ^ data[7] ^ data[8] ^ 
	           data[9] ^ data[10];

assign parity[4] = data[11] ^ data[12] ^ data[13] ^ data[14] ^ data[15];

assign parity[5]=  data[0] ^ data[1] ^ data[2] ^ data[3] ^ 
		   parity[0] ^ parity[1] ^ parity[2];

assign cor_parity_5 = data[15] ^ data[14] ^ data[13] ^ data[12] ^ 
		      data[11] ^ data[10] ^ data[9] ^ data[8] ^ 
		      data[7] ^ data[6] ^ data[5] ^ data[4] ^ 
		      data[3] ^ data[2] ^ data[1] ^ data[0] ^
		      chkbit[4] ^ chkbit[3] ^ chkbit[2] ^ chkbit[1] ^ chkbit[0];

endmodule