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// OpenSPARC T2 Processor File: pcs_lfsr.v
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// @(#)pcs_lfsr.v	1.1G
/**********************************************************************/
/* Project Name  :  CASSINI                                           */
/* Module Name   :  PCS 10 ms timer				      */
/* Description   :  A LFSR is used to create a 50% duty cycle clock   */
/*		    which has a 4.2 ms cycle time.		      */
/*    								      */
/* Assumptions   : none.					      */
/*    								      */
/* Parent module : pcs_link_config.v				      */
/* Child modules : none.					      */
/* Author Name   : Linda Chen                                         */
/* Date Created  : 11/6/97                                            */
/*                                                                    */
/*              Copyright (c) 1994, Sun Microsystems, Inc.            */
/*                   Sun Proprietary and Confidential                 */
/*                                                                    */ 
/* Modifications : none yet                                           */
/* Synthesis Notes : delay cells are added to meet hold time given    */
/*		400 ps clock skew.				      */
/**********************************************************************/
 
module pcs_lfsr (txclk,timer_override,reset_tx,timer_tick);

input		txclk;
input 		timer_override;
input		reset_tx;

output		timer_tick;
wire		slow_clk;	// ticks every 2.1 ms

reg [17:0]	pat;		// pseudo random pattern generated by LFSR

wire		feedback;	// feedback loop to input of LFSR
wire		at_end;		// to toggle slow clk high for 50% duty cycle
				// ticks every 2.1 ms
wire		nxt_slow_clk; 	// input to slow clk register
wire [17:0]	del_pat;	// delay for hold time for lfsr

assign		at_end = (pat == 18'h1),
		feedback = pat[0],
		nxt_slow_clk = (reset_tx)? 1'h0 : (at_end)? 
			~slow_clk: slow_clk,
		/*
		** If timer override is asserted the slow clk ticks
		** about every 8 txclk ticks.
		*/
		timer_tick = (timer_override)? (pat[0] & pat[1]): slow_clk;


/*
** Primitive polynomial
** 1 + x^1 + x^2 + x^5 + x^19
** 1 + x^7 + x^18
*/
always @(posedge txclk)
  begin
    if (reset_tx) pat <= 18'h1;
    else begin
      pat[0] <= del_pat[0];
      pat[1] <= del_pat[1];
      pat[2] <= del_pat[2];
      pat[3] <= del_pat[3];
      pat[4] <= del_pat[4];
      pat[5] <= del_pat[5];
      pat[6] <= del_pat[6];
      pat[7] <= del_pat[7];
      pat[8] <= del_pat[8];
      pat[9] <= del_pat[9];
      pat[10] <= del_pat[10];
      pat[11] <= del_pat[11];
      pat[12] <= del_pat[12];
      pat[13] <= del_pat[13];
      pat[14] <= del_pat[14];
      pat[15] <= del_pat[15];
      pat[16] <= del_pat[16];
      pat[17] <= del_pat[17];
    end
  end

// for hold time requirement
DEL2ns_PAT delay_pattern(
	del_pat,
	{feedback,	// x^18
	pat[17],
	pat[16],
	pat[15],
	pat[14],
	pat[13],
	pat[12],
	pat[11],
	pat[10],
	pat[9],
	pat[8],
	pat[7] ^ feedback,
	pat[6],
	pat[5], // ^ feedback,	// x^5
	pat[4],
	pat[3],
	pat[2], // ^ feedback,	// x^2
	pat[1]});// ^ feedback});// x

		
REG  #(1) r_slow_clk(slow_clk,txclk,nxt_slow_clk);

endmodule