/* * ========== Copyright Header Begin ========================================== * * OpenSPARC T2 Processor File: n2_8t_bstbld_7.s * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved * 4150 Network Circle, Santa Clara, California 95054, U.S.A. * * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * * For the avoidance of doubt, and except that if any non-GPL license * choice is available it will apply instead, Sun elects to use only * the General Public License version 2 (GPLv2) at this time for any * software where a choice of GPL license versions is made * available with the language indicating that GPLv2 or any later version * may be used, or where a choice of which version of the GPL is applied is * otherwise unspecified. * * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, * CA 95054 USA or visit www.sun.com if you need additional information or * have any questions. * * * ========== Copyright Header End ============================================ */ #define N_CPUS 8 #define REGION_MAPPED_SIZE_RTL 8192 #define REGION_SIZE_RTL (8 * 1024) #define RESULTS_BUF_SIZE_PER_CPU_RTL 1024 #define PRIVATE_DATA_AREA_PER_CPU_RTL 64 #define ALIGN_PAGE_8K .align 8192 #define ALIGN_PAGE_64K .align 65536 #define ALIGN_PAGE_512K .align 524288 #define ALIGN_PAGE_4M .align 4194304 #define USER_PAGE_CUSTOM_MAP SECTION .MY_HYP_SEC TEXT_VA = 0x1100150000 attr_text { Name=.MY_HYP_SEC, hypervisor } .text .global intr0x60_custom_trap intr0x60_custom_trap: ldxa [%g0] 0x72, %g2; ldxa [%g0] 0x74, %g1; retry; .global intr0x190_custom_trap intr0x190_custom_trap: .global intr0x190_custom_trap intr0x190_custom_trap: #ifdef SJM ! programming the JBI - not quite rrugho !===================== !setx 0x0000000006040012, %g1, %g2 !setx 0x8503000010, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000003, %g1, %g2 !setx 0x8500000100, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000000, %g1, %g2 !setx 0x9800000000, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000000, %g1, %g2 !setx 0x9800000400, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000003, %g1, %g2 !setx 0x8500000108, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000101, %g1, %g2 !setx 0x9800000008, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000000, %g1, %g2 !setx 0x9800000408, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000003, %g1, %g2 !setx 0x8500000110, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000202, %g1, %g2 !setx 0x9800000010, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000000, %g1, %g2 !setx 0x9800000410, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000003, %g1, %g2 !setx 0x8500000118, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000303, %g1, %g2 !setx 0x9800000018, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000000, %g1, %g2 !setx 0x9800000418, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000003, %g1, %g2 !setx 0x8500000120, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000404, %g1, %g2 !setx 0x9800000020, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000000, %g1, %g2 !setx 0x9800000420, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000003, %g1, %g2 !setx 0x8500000128, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000505, %g1, %g2 !setx 0x9800000028, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000000, %g1, %g2 !setx 0x9800000428, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000003, %g1, %g2 !setx 0x8500000130, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000606, %g1, %g2 !setx 0x9800000030, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000000, %g1, %g2 !setx 0x9800000430, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000003, %g1, %g2 !setx 0x8500000138, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000707, %g1, %g2 !setx 0x9800000038, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000000, %g1, %g2 !setx 0x9800000438, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000003, %g1, %g2 !setx 0x8500000140, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000808, %g1, %g2 !setx 0x9800000040, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000000, %g1, %g2 !setx 0x9800000440, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000003, %g1, %g2 !setx 0x8500000148, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000909, %g1, %g2 !setx 0x9800000048, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000000, %g1, %g2 !setx 0x9800000448, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000003, %g1, %g2 !setx 0x8500000150, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000a0a, %g1, %g2 !setx 0x9800000050, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000000, %g1, %g2 !setx 0x9800000450, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000003, %g1, %g2 !setx 0x8500000158, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000b0b, %g1, %g2 !setx 0x9800000058, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000000, %g1, %g2 !setx 0x9800000458, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000003, %g1, %g2 !setx 0x8500000160, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000c0c, %g1, %g2 !setx 0x9800000060, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000000, %g1, %g2 !setx 0x9800000460, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000003, %g1, %g2 !setx 0x8500000168, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000d0d, %g1, %g2 !setx 0x9800000068, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000000, %g1, %g2 !setx 0x9800000468, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000003, %g1, %g2 !setx 0x8500000170, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000e0e, %g1, %g2 !setx 0x9800000070, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000000, %g1, %g2 !setx 0x9800000470, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000003, %g1, %g2 !setx 0x8500000178, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000f0f, %g1, %g2 !setx 0x9800000078, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000000, %g1, %g2 !setx 0x9800000478, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x000000000000007f, %g1, %g2 !setx 0x8503000008, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000001010, %g1, %g2 !setx 0x9800000080, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000000, %g1, %g2 !setx 0x9800000480, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000001111, %g1, %g2 !setx 0x9800000088, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000000, %g1, %g2 !setx 0x9800000488, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000000, %g1, %g2 !setx 0x9300000c00, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000000, %g1, %g2 !setx 0x9300000e20, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000000, %g1, %g2 !setx 0x9300000e28, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000000, %g1, %g2 !setx 0x9300000e38, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000008, %g1, %g2 !setx 0x8503000018, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000000, %g1, %g2 !setx 0x9800000828, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000000, %g1, %g2 !setx 0x8503000028, %g1, %g3 !stx %g2, [%g3] !!===================== !setx 0x0000000000000001, %g1, %g2 !setx 0x8503000020, %g1, %g3 !stx %g2, [%g3] !!===================== /*********************************************************************** Disable L2 Cache Visibility Port ***********************************************************************/ setx 0x0000000000000000, %g1, %g2 setx 0x9800001800, %g1, %g3 stx %g2, [%g3] !===================== setx 0x0000000000000000, %g1, %g2 setx 0x9800001820, %g1, %g3 stx %g2, [%g3] !===================== setx 0x0000000000000000, %g1, %g2 setx 0x9800001828, %g1, %g3 stx %g2, [%g3] !===================== setx 0x0000000000000000, %g1, %g2 setx 0x9800001830, %g1, %g3 stx %g2, [%g3] !===================== setx 0x0000000000000000, %g1, %g2 setx 0x9800001838, %g1, %g3 stx %g2, [%g3] !===================== setx 0x0000000000000000, %g1, %g2 setx 0x9800001840, %g1, %g3 stx %g2, [%g3] !===================== /*********************************************************************** Disable IOBridge Visibility Ports ***********************************************************************/ setx 0x0000000000000000, %g1, %g2 setx 0x9800001000, %g1, %g3 stx %g2, [%g3] !===================== setx 0x0000000000000000, %g1, %g2 setx 0x9800002000, %g1, %g3 stx %g2, [%g3] !===================== setx 0x0000000000000000, %g1, %g2 setx 0x9800002008, %g1, %g3 stx %g2, [%g3] !===================== setx 0x0000000000000000, %g1, %g2 setx 0x9800002100, %g1, %g3 stx %g2, [%g3] !===================== setx 0x0000000000000000, %g1, %g2 setx 0x9800002140, %g1, %g3 stx %g2, [%g3] !===================== setx 0x0000000000000000, %g1, %g2 setx 0x9800002160, %g1, %g3 stx %g2, [%g3] !===================== setx 0x0000000000000000, %g1, %g2 setx 0x9800002180, %g1, %g3 stx %g2, [%g3] !===================== setx 0x0000000000000000, %g1, %g2 setx 0x98000021a0, %g1, %g3 stx %g2, [%g3] !===================== setx 0x0000000000000000, %g1, %g2 setx 0x9800002148, %g1, %g3 stx %g2, [%g3] !===================== setx 0x0000000000000000, %g1, %g2 setx 0x9800002168, %g1, %g3 stx %g2, [%g3] !===================== setx 0x0000000000000000, %g1, %g2 setx 0x9800002188, %g1, %g3 stx %g2, [%g3] !===================== setx 0x0000000000000000, %g1, %g2 setx 0x98000021a8, %g1, %g3 stx %g2, [%g3] !===================== setx 0x0000000000000000, %g1, %g2 setx 0x9800002150, %g1, %g3 stx %g2, [%g3] !===================== setx 0x0000000000000000, %g1, %g2 setx 0x9800002170, %g1, %g3 stx %g2, [%g3] !===================== setx 0x0000000000000000, %g1, %g2 setx 0x9800002190, %g1, %g3 stx %g2, [%g3] !===================== setx 0x0000000000000000, %g1, %g2 setx 0x98000021b0, %g1, %g3 stx %g2, [%g3] !===================== /*********************************************************************** Configure jbi controller ***********************************************************************/ setx 0x03fb303e00000001, %g1, %g2 setx 0x8000000000, %g1, %g3 stx %g2, [%g3] !===================== setx 0x000000007033fe0f, %g1, %g2 setx 0x8000000008, %g1, %g3 stx %g2, [%g3] !===================== setx 0x0000003fc0000000, %g1, %g2 setx 0x80000100a0, %g1, %g3 stx %g2, [%g3] !===================== setx 0x00000000fe0003ff, %g1, %g2 setx 0x8000004100, %g1, %g3 stx %g2, [%g3] !===================== /*********************************************************************** IOSYNC cycles to start sjm ***********************************************************************/ setx 0xdeadbeefdeadbeef, %g1, %g2 setx 0xcf00beef00, %g1, %g3 stx %g2, [%g3] !===================== setx 0xdeadbeefdeadbeef, %g1, %g2 setx 0xef00beef00, %g1, %g3 stx %g2, [%g3] !============================= done; #else #ifdef DC_ON_OFF and %i0, 0x1, %i0 brz %i0, on nop mov 0xd, %i0 ba finish_dc_on_off stxa %l0, [%g0] 0x45 /* turn D-cache off */ on: mov 0xf, %i0 stxa %i0, [%g0] 0x45 /* turn D-cache back on */ finish_dc_on_off: done #else stxa %i0, [%g0] 0x73; done; #endif #endif !============================================================================ #define ENABLE_T0_Fp_exception_ieee_754_0x21 #define ENABLE_T0_Fp_exception_other_0x22 #define ENABLE_T0_Fp_disabled_0x20 #define ENABLE_T0_Illegal_instruction_0x10 #define ENABLE_T1_Illegal_instruction_0x10 #define ENABLE_HT0_Illegal_instruction_0x10 #define ENABLE_HT1_Illegal_instruction_0x10 #define ENABLE_T0_Clean_Window_0x24 #define MAIN_PAGE_NUCLEUS_ALSO #define MAIN_PAGE_HV_ALSO #define MAIN_PAGE_VA_IS_RA_ALSO #define H_T0_Trap_Instruction_0 #define My_T0_Trap_Instruction_0 \ ta 0x90; \ done; #define H_HT0_HTrap_Instruction_0 intr0x190_custom_trap #ifdef SJM #define My_HT0_HTrap_Instruction_0 \ setx intr0x190_custom_trap, %g1, %g2; \ jmp %g2; nop #else #define My_HT0_HTrap_Instruction_0 \ stxa %i0, [%g0] 0x73; \ done; #endif #define H_HT0_Interrupt_0x60 intr0x60_custom_trap #define My_HT0_Interrupt_0x60 \ ldxa [%g0] 0x72, %g2; \ ldxa [%g0] 0x74, %g1; \ retry; #define H_HT0_Trap_Instruction_5 #define My_HT0_Trap_Instruction_5 \ ldxa [%g0 + %g0]0x45, %g1; \ membar #Sync; \ xor %g1, 19, %g1; \ stxa %g1, [%g0 + %g0]0x45; \ wrpr %g0, 0x200, %pstate; done; #ifndef THREAD_COUNT #define THREAD_COUNT 8 #endif #ifndef THREAD_STRIDE #define THREAD_STRIDE 1 #endif #define SKIP_TRAPCHECK #include "hboot.s" !try later: ! stxa %l6, [$8] (0x22 | ($2 & 0x9)) ! ASI is randomly set !=========== define(BST_INIT, ` add $6, ($7 & 0xfff0), $8 ! 4-byte align the offset stxa %l6, [$8] 0x22 ! ASI is randomly set ') !try later: !ldda [$8] (0x22 | ($2 & 0x9)), %l6 ! ASI is randomly set !=========== define(BLD_INIT, ` add $6, ($7 & 0xfff0), $8 ! 4-byte align the offset ldda [$8] 0x22, %l6 ! ASI is randomly set ') define(CHECK_PROC_ID,` check_cpu_id: wr %g0, 0x4, %fprs /* make sure fef is 1 */ mov THREAD_STRIDE, %l2 th_fork(thread,%l0) thread_0: #ifdef SJM ta 0x30 #endif mov 0, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_1: mov 1, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_2: mov 2, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_3: mov 3, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_4: mov 4, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_5: mov 5, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_6: mov 6, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_7: mov 7, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_8: mov 8, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_9: mov 9, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_10: mov 10, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_11: mov 11, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_12: mov 12, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_13: mov 13, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_14: mov 14, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_15: mov 15, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_16: mov 16, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_17: mov 17, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_18: mov 18, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_19: mov 19, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_20: mov 20, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_21: mov 21, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_22: mov 22, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_23: mov 23, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_24: mov 24, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_25: mov 25, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_26: mov 26, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_27: mov 27, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_28: mov 28, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_29: mov 29, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_30: mov 30, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_31: mov 31, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_32: mov 32, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_33: mov 33, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_34: mov 34, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_35: mov 35, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_36: mov 36, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_37: mov 37, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_38: mov 38, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_39: mov 39, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_40: mov 40, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_41: mov 41, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_42: mov 42, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_43: mov 43, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_44: mov 44, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_45: mov 45, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_46: mov 46, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_47: mov 47, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_48: mov 48, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_49: mov 49, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_50: mov 50, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_51: mov 51, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_52: mov 52, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_53: mov 53, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_54: mov 54, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_55: mov 55, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_56: mov 56, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_57: mov 57, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_58: mov 58, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_59: mov 59, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_60: mov 60, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_61: mov 61, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_62: mov 62, %g1 udivx %g1, %l2, %g1 ba entry_point; nop thread_63: mov 63, %g1 udivx %g1, %l2, %g1 ba entry_point; nop entry_point: #ifdef RTGPRIV ta T_CHANGE_PRIV #endif ') ! --- Common Macro Definitions --- ! ! macros will be instantiated with these arguments ! macro_name(P#, rand#, my_cpu#, PA_val, VA_val, VA_reg, VA_offset, \ ! tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) ! ! P# - Pid, just in case one needs unique number ! rand# - random number ! my_cpu# - CPU id ! PA_val - shared memory physisal address value ! VA_val - shared memory virtual address value ! VA_reg - register containing VA region base address ! VA_offset - VA_reg + VA_offset will give correct VA address value ! tmp_reg0-tmp_reg3 - integer registers for arbitrary use within the macro ! tmp_reg0 & tmp_reg1 are even-odd register pair ! ! VA_val may be incorrect since VA will be determined at compile time by assembler ! and may not available at diag generation time, but VA_reg+VA_offset is valid ! ! ex. SAMPLE(1, 1249, 0, 0x43400100, 0x100, %i1, 0x100, %l6, %l7, %o5, %l3) ! ! Sample macro 1: ! load unsigned byte from the given shared addr into tmp_reg1 ! the given shared addr is 4-byte aligned and we will randomly ! pick one byte from the 4 bytes. ! ! define(SAMPLE, ` ! ldub [$6+$7+($2 mod 4)], $8 ! ') ! ! Can also use C-like macro definition format. ! ! Sample macro 2: ! issue an "ldda" instruction to the randomly picked shared location ! (aligned it to 16-byte boundary first) with a random ASI value among ! 0x22, 0x23, 0x2a, and 0x2b (utilizing the provided "rand" value). ! ! #define BLD_INIT(Pid, rand, my_cpu, PA_val, \ ! VA_val, VA_reg, VA_offset, \ ! tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \ ! add VA_reg, (VA_offset & 0xfff0), tmp_reg3; \ ! ldda [tmp_reg2] (0x22 | (rand & 0x9)), tmp_reg0; ! ! --- ! Macro NOPTRAIN ! Train of NOPs #define NOPTRAIN(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \ nop;\ nop;\ nop;\ nop; ! Macro STTRAIN4 ! Train of total 4 of UW stores. ! Note: doesn't use shared addresses #define STTRAIN4(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \ set 5120, tmp_reg1; \ add %i0, tmp_reg1, tmp_reg1; \ set rand, tmp_reg2; \ stw tmp_reg2, [tmp_reg1]; \ stw tmp_reg2, [tmp_reg1+4]; \ stw tmp_reg2, [tmp_reg1+8]; \ stw tmp_reg2, [tmp_reg1+16]; ! Macro STTRAIN8 ! Train of total 8 of UW stores #define STTRAIN8(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \ set 5120, tmp_reg1; \ add %i0, tmp_reg1, tmp_reg1; \ set rand, tmp_reg2; \ add tmp_reg2, rand % 4096, tmp_reg3; \ stw tmp_reg2, [tmp_reg1]; \ stw tmp_reg2, [tmp_reg1+4]; \ stw tmp_reg2, [tmp_reg1+8]; \ stw tmp_reg2, [tmp_reg1+12]; \ stw tmp_reg3, [tmp_reg1+4]; \ stw tmp_reg3, [tmp_reg1+12]; \ stw tmp_reg3, [tmp_reg1]; \ stw tmp_reg3, [tmp_reg1+8]; ! Macro LDTRAIN4 ! Train of total 4 of UW Loads ! Note the values of those loads inside the macro will not be analized, ! even though the accesses are [possibly] made to the shared locations #define LDTRAIN4(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \ ld [%i0], tmp_reg1; \ ld [%i1+4], tmp_reg1; \ ld [%i2+8], tmp_reg1; \ ld [%i3+12], tmp_reg1; ! Macro LDTRAIN8 #define LDTRAIN8(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \ ld [%i3], tmp_reg1; \ ld [%i2+4], tmp_reg1; \ ld [%i1+8], tmp_reg2; \ ld [%i0+12], tmp_reg2; \ ld [%i3+4], tmp_reg3; \ ld [%i2], tmp_reg3; \ ld [%i1+12], tmp_reg4; \ ld [%i0+8], tmp_reg4; ! Macro PREFETCHTRAIN4 #define PREFETCHTRAIN4(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \ prefetch [%i0+4], 0; \ prefetch [%i1+12], 0; \ prefetch [%i2+8], 0; \ prefetch [%i3], 0; ! Macro PREFETCHTRAIN8 #define PREFETCHTRAIN8(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \ prefetch [%i3], 0; \ prefetch [%i2+4], 0; \ prefetch [%i1+8], 0; \ prefetch [%i0+12], 0; \ prefetch [%i3+4], 1; \ prefetch [%i2], 1; \ prefetch [%i1+12], 1; \ prefetch [%i0+8], 1; ! Macro CASTRAIN4 ! This is an interesting macro that will probably create the write congessions ! access to the shared locations (offsets from bases have to be adjusted) ! the values of the locations are not changed, so it should not affect analysis #define CASTRAIN4(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \ set 128, tmp_reg1;\ add %i0, tmp_reg1, tmp_reg1;\ set 256, tmp_reg2;\ add %i1, tmp_reg2, tmp_reg2;\ ld [tmp_reg1], tmp_reg3;\ ld [tmp_reg2], tmp_reg4;\ cas [tmp_reg1], tmp_reg3, tmp_reg3;\ cas [tmp_reg1], tmp_reg3, tmp_reg3;\ cas [tmp_reg2], tmp_reg4, tmp_reg4;\ cas [tmp_reg2], tmp_reg4, tmp_reg4; ! CASTRAIN8 ! yet another flavor of cas train theme that actually always use shared locations ! given by the specified instance arguments for the first 4 cases ! and then follows then with another 4 to a randomized offset #define CASTRAIN8(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \ add VA_reg, VA_offset, tmp_reg1;\ add VA_reg, (rand&0x0ffc), tmp_reg2;\ ld [tmp_reg1], tmp_reg3;\ cas [tmp_reg1], tmp_reg3, tmp_reg3;\ cas [tmp_reg1], tmp_reg3, tmp_reg3;\ cas [tmp_reg1], tmp_reg3, tmp_reg3;\ cas [tmp_reg1], tmp_reg3, tmp_reg3;\ ld [tmp_reg2], tmp_reg4;\ cas [tmp_reg2], tmp_reg4, tmp_reg4;\ cas [tmp_reg2], tmp_reg4, tmp_reg4;\ cas [tmp_reg2], tmp_reg4, tmp_reg4;\ cas [tmp_reg2], tmp_reg4, tmp_reg4; ! Macro ST_BR_ANLD_CAS ! this is meant to reproduce NG6025 ! the scenario is the anulled load in the delay slot of the branch is ! not wiped completely, which creates false RAW hazard, and the following cas ! is getting screwed ! WARNING: there is a store to the %i0+128, which can potentially be a shared ! location. When using this macro, make sure that the vicinity of offset 128 in ! region 0 is not used #define ST_BR_ANLD_CAS(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \ set 128, tmp_reg1;\ add %i0, tmp_reg1, tmp_reg1;\ set rand, tmp_reg3;\ stw tmp_reg3, [tmp_reg1];\ ba,a 1;\ cas [tmp_reg1], tmp_reg3, tmp_reg4; #define ASI_BLOCK(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \ setx 0x060, tmp_reg1, tmp_reg2; \ stxa %g0, [tmp_reg2] 0x38; ! Macro SELF_MODIFY ! do a read-unmodify-write at address pc + random[0..0x80] ! this is targetted to catch bugs due to sharing/modification ! of data between D$ and I$. (e.g. Niagara1, Bug #6372) ! 1. 0x80 chosen arbitrarily, is another number better ! 2. should we include an iflush ? ! 3. WT.MACRO.SELF_MODIFY should be given a small non-0 weight by default ! 4. Possible variation: a macro which only does a load ! from the instruction stream instead of a load-store. ! (Niagara1 bug #6372 did not involve stores to instruction ! stream, just sharing of unmodified data between I$ and D$.) ! 5. this macro needs text segment to be writable. On system runs, ! this is achieved by using a special map file for the linker. ! - sgh, 25 may 04 #define SELF_MODIFY(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \ rd %pc, tmp_reg0; \ ld [ tmp_reg0 + (rand & 0x7c)], tmp_reg1; \ st tmp_reg1, [ tmp_reg0 + (rand & 0x7c)] #define ASI_BLOCK(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \ setx 0x060, tmp_reg1, tmp_reg2; \ stxa %g0, [tmp_reg2] 0x38; #define ASI_BLOCK_VA_HOLE(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \ setx 0x8559e06ff33bad10, tmp_reg1, tmp_reg2; \ stxa %g0, [tmp_reg2] 0x80; #define PREFETCH_VA_HOLE(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \ setx 0x8559e06ff33bad10, tmp_reg1, tmp_reg2; \ prefetch [tmp_reg2], 0; \ prefetch [tmp_reg2+4], 1; \ prefetch [tmp_reg2+8], 2; \ prefetch [tmp_reg2+12], 3; \ prefetch [tmp_reg2+4], 4; \ prefetch [tmp_reg2], 5; \ prefetch [tmp_reg2+12], 6; \ prefetch [tmp_reg2+8], 7; #define LOAD_VA_HOLE(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \ setx 0x8559e06ff33bad10, tmp_reg1, tmp_reg2; \ ld [tmp_reg2], tmp_reg1; \ ld [tmp_reg2+4], tmp_reg1; \ ld [tmp_reg2+8], tmp_reg1; \ ld [tmp_reg2+12], tmp_reg1; #define STORE_VA_HOLE(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \ setx 0x8559e06ff33bad10, tmp_reg2, tmp_reg1; \ set rand, tmp_reg2; \ add tmp_reg2, rand % 4096, tmp_reg3; \ stw tmp_reg2, [tmp_reg1]; \ stw tmp_reg2, [tmp_reg1+4]; \ stw tmp_reg2, [tmp_reg1+8]; \ stw tmp_reg2, [tmp_reg1+12]; \ stw tmp_reg3, [tmp_reg1+4]; \ stw tmp_reg3, [tmp_reg1+12]; \ stw tmp_reg3, [tmp_reg1]; \ stw tmp_reg3, [tmp_reg1+8]; #define CAS_VA_HOLE(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \ setx 0x8559e06ff33bad10, tmp_reg3, tmp_reg1; \ setx 0x8559e06ff33bad10, tmp_reg3, tmp_reg2; \ add tmp_reg2, rand % 4096, tmp_reg3; \ cas [tmp_reg1], tmp_reg3, tmp_reg3;\ cas [tmp_reg2], tmp_reg4, tmp_reg4; #define IDC_FLIP(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \ ta 0xb5; \ ta T_CHANGE_NONHPRIV; ! this macro produce ldda/stda to ! ASI_BLOCK_AS_IF_USER_PRIMARY 0x16 ! ASI_BLOCK_AS_IF_USER_SECONDARY 0x17 ! ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 0x1e ! ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x1f !! hardcode for now since illegal asi not working in RS #define BLD_16(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \ add VA_reg, (VA_offset & 0xfff0), tmp_reg3; \ ta T_CHANGE_PRIV;\ ta T_CHANGE_HPRIV;\ ldda [tmp_reg3]0x16, tmp_reg0; #define BLD_17(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \ add VA_reg, (VA_offset & 0xfff0), tmp_reg3; \ ta T_CHANGE_PRIV;\ ta T_CHANGE_HPRIV;\ ldda [tmp_reg3]0x17, tmp_reg0; #define BLD_1e(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \ add VA_reg, (VA_offset & 0xfff0), tmp_reg3; \ ta T_CHANGE_PRIV;\ ta T_CHANGE_HPRIV;\ ldda [tmp_reg3]0x1e, tmp_reg0; #define BLD_1f(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \ add VA_reg, (VA_offset & 0xfff0), tmp_reg3; \ ta T_CHANGE_PRIV;\ ta T_CHANGE_HPRIV;\ ldda [tmp_reg3]0x1f, tmp_reg0; #define BST_16(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \ add VA_reg, (VA_offset & 0xfff0), tmp_reg3; \ ta T_CHANGE_PRIV;\ ta T_CHANGE_HPRIV;\ stda tmp_reg0, [tmp_reg3]0x16; #define BST_17(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \ add VA_reg, (VA_offset & 0xfff0), tmp_reg3; \ ta T_CHANGE_PRIV;\ ta T_CHANGE_HPRIV;\ stda tmp_reg0, [tmp_reg3]0x17; #define BST_1e(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \ add VA_reg, (VA_offset & 0xfff0), tmp_reg3; \ ta T_CHANGE_PRIV;\ ta T_CHANGE_HPRIV;\ stda tmp_reg0, [tmp_reg3]0x1e; #define BST_1f(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \ add VA_reg, (VA_offset & 0xfff0), tmp_reg3; \ ta T_CHANGE_PRIV;\ ta T_CHANGE_HPRIV;\ stda tmp_reg0, [tmp_reg3]0x1f; #define BLD_INIT_2(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \ add VA_reg, (VA_offset & 0xfff0), tmp_reg3; \ ldda [tmp_reg3] (0x27 | (rand & 0xf)), tmp_reg0; #define BST_INIT_2(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \ add VA_reg, (VA_offset & 0xfff0), tmp_reg3; \ stda tmp_reg0, [tmp_reg3] (0x27 | (rand & 0xf)); #define BLD_INIT_E(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \ add VA_reg, (VA_offset & 0xfff0), tmp_reg3; \ ldda [tmp_reg3] (0xe2 | (rand & 0xb)), tmp_reg0; #define BST_INIT_E(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \ add VA_reg, (VA_offset & 0xfff0), tmp_reg3; \ stda tmp_reg0, [tmp_reg3] (0xe2 | (rand & 0xb)); #define PREFETCHA(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \ add VA_reg, (VA_offset & 0x00ff), tmp_reg3; \ prefetch [%i1], (rand & 0x1f); \ prefetch [%i1 + ((rand >> 5) & 0x1f)], ((rand >> 5) & 0x1f); \ prefetcha [%i1]((rand >> 5) & 0x1f), (0x0 | ((rand >> 5) & 0x1f)); #define STBYTE(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \ add VA_reg, (VA_offset & 0xff00), tmp_reg1; \ set rand, tmp_reg2; \ stb tmp_reg2, [tmp_reg1+(rand & 0x5f)]; #define LDBYTE(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \ add VA_reg, (VA_offset & 0xff00), tmp_reg1; \ ldub [tmp_reg1+(rand & 0x5f)], tmp_reg2; #define STBYTE1(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \ add VA_reg, (VA_offset & 0xff00), tmp_reg1;\ set 5200, tmp_reg2; \ add tmp_reg2, tmp_reg1, tmp_reg1; \ set rand, tmp_reg2; \ stb tmp_reg2, [tmp_reg1+(rand & 0x5f)]; #define STINT(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \ set rand, tmp_reg1; \ stha tmp_reg1,[%g0+%g0](0x73); \ stda tmp_reg1, [%g0+%g0](0x73); define(EN_INTERRUPTS,` nop ') define(DIS_INTERRUPTS,` nop ') define(CHECK_DISPATCH_STATUS,` nop ') define(CHECK_RECEIVE_STATUS,` nop ') define(WRITE_INTR_DATA_REGS,` nop ') define(INTR_SET_DISPATCH_VECTOR,` add %g0, $3, $4 sllx $4, 8, $5 ! DEST ID add %g0, $2, $4 ! VECTOR NUMBER or $5, $4, $5 mov %i0, $4 mov $5, %i0 ta 0x30 mov $4, %i0 ') define(DSPCH_INTERRUPT,` nop ') #define REGION0_ALIAS0_O 0x0 #define REGION1_ALIAS0_O 0x2000 #define REGION2_ALIAS0_O 0x4000 #define REGION3_ALIAS0_O 0x6000 #define REGION4_ALIAS0_O 0x8000 #define REGION5_ALIAS0_O 0xa000 #define REGION6_ALIAS0_O 0xc000 #define REGION7_ALIAS0_O 0xe000 #define REPLACEMENT0_ALIAS0_O 0x10000 #define USER_PAGE_CUSTOM_MAP SECTION .MAIN TEXT_VA=0x1000000 attr_text { Name = .MAIN, VA=0x1000000, RA=0x130000000, PA=ra2pa(0x130000000,0), part_0_ctx_nonzero_tsb_config_1, TTE_EP=1, TTE_G=1, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=0 } attr_text { Name = .MAIN, VA=0x1000000, RA=0x130000000, PA=ra2pa(0x130000000,0), part_0_ctx_nonzero_tsb_config_0, TTE_EP=1, TTE_G=1, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } SECTION tsotool_unshared_data DATA_VA=0x21400000 attr_data { Name = tsotool_unshared_data, VA=0x21400000, RA=0x21400000, PA=ra2pa(0x21400000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=1, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1 } SECTION region0_alias0 DATA_VA=0x6000000 attr_data { Name = region0_alias0, VA=0x6000000, RA=0x43000000, PA=ra2pa(0x43000000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1 } SECTION region1_alias0 DATA_VA=0x6002000 attr_data { Name = region1_alias0, VA=0x6002000, RA=0x43800000, PA=ra2pa(0x43800000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1 } SECTION region2_alias0 DATA_VA=0x6004000 attr_data { Name = region2_alias0, VA=0x6004000, RA=0x44000000, PA=ra2pa(0x44000000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1 } SECTION region3_alias0 DATA_VA=0x6006000 attr_data { Name = region3_alias0, VA=0x6006000, RA=0x44800000, PA=ra2pa(0x44800000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1 } SECTION region4_alias0 DATA_VA=0x6008000 attr_data { Name = region4_alias0, VA=0x6008000, RA=0x45000000, PA=ra2pa(0x45000000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1 } SECTION region5_alias0 DATA_VA=0x600a000 attr_data { Name = region5_alias0, VA=0x600a000, RA=0x45800000, PA=ra2pa(0x45800000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1 } SECTION region6_alias0 DATA_VA=0x600c000 attr_data { Name = region6_alias0, VA=0x600c000, RA=0x46000000, PA=ra2pa(0x46000000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1 } SECTION region7_alias0 DATA_VA=0x600e000 attr_data { Name = region7_alias0, VA=0x600e000, RA=0x46800000, PA=ra2pa(0x46800000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1 } SECTION replacement0_alias0 DATA_VA=0x6010000 attr_data { Name = replacement0_alias0, VA=0x6010000, RA=0x47000000, PA=ra2pa(0x47000000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1 } SECTION replacement1_alias0 DATA_VA=0x6012000 attr_data { Name = replacement1_alias0, VA=0x6012000, RA=0x47800000, PA=ra2pa(0x47800000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1 } SECTION replacement2_alias0 DATA_VA=0x6014000 attr_data { Name = replacement2_alias0, VA=0x6014000, RA=0x48000000, PA=ra2pa(0x48000000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1 } SECTION replacement3_alias0 DATA_VA=0x6016000 attr_data { Name = replacement3_alias0, VA=0x6016000, RA=0x48800000, PA=ra2pa(0x48800000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1 } SECTION replacement4_alias0 DATA_VA=0x6018000 attr_data { Name = replacement4_alias0, VA=0x6018000, RA=0x49000000, PA=ra2pa(0x49000000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1 } SECTION replacement5_alias0 DATA_VA=0x601a000 attr_data { Name = replacement5_alias0, VA=0x601a000, RA=0x49800000, PA=ra2pa(0x49800000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1 } SECTION replacement6_alias0 DATA_VA=0x601c000 attr_data { Name = replacement6_alias0, VA=0x601c000, RA=0x4a000000, PA=ra2pa(0x4a000000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1 } SECTION replacement7_alias0 DATA_VA=0x601e000 attr_data { Name = replacement7_alias0, VA=0x601e000, RA=0x4a800000, PA=ra2pa(0x4a800000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1 } SECTION non_fault_area_4 DATA_VA=0x0 attr_data { Name = non_fault_area_4, VA=0x0, RA=0x47002000, PA=ra2pa(0x47002000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=1, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=1, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION region0_alias0_8 DATA_VA=0x6000000 attr_data { Name = region0_alias0_8, VA=0x6000000, RA=0x43000000, PA=ra2pa(0x43000000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=SCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION region1_alias0_8 DATA_VA=0x6002000 attr_data { Name = region1_alias0_8, VA=0x6002000, RA=0x43800000, PA=ra2pa(0x43800000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=SCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION region2_alias0_8 DATA_VA=0x6004000 attr_data { Name = region2_alias0_8, VA=0x6004000, RA=0x44000000, PA=ra2pa(0x44000000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=SCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION region3_alias0_8 DATA_VA=0x6006000 attr_data { Name = region3_alias0_8, VA=0x6006000, RA=0x44800000, PA=ra2pa(0x44800000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=SCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION region4_alias0_8 DATA_VA=0x6008000 attr_data { Name = region4_alias0_8, VA=0x6008000, RA=0x45000000, PA=ra2pa(0x45000000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=SCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION region5_alias0_8 DATA_VA=0x600a000 attr_data { Name = region5_alias0_8, VA=0x600a000, RA=0x45800000, PA=ra2pa(0x45800000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=SCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION region6_alias0_8 DATA_VA=0x600c000 attr_data { Name = region6_alias0_8, VA=0x600c000, RA=0x46000000, PA=ra2pa(0x46000000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=SCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION region7_alias0_8 DATA_VA=0x600e000 attr_data { Name = region7_alias0_8, VA=0x600e000, RA=0x46800000, PA=ra2pa(0x46800000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=SCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION replacement0_alias0_8 DATA_VA=0x6010000 attr_data { Name = replacement0_alias0_8, VA=0x6010000, RA=0x47000000, PA=ra2pa(0x47000000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=SCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION replacement1_alias0_8 DATA_VA=0x6012000 attr_data { Name = replacement1_alias0_8, VA=0x6012000, RA=0x47800000, PA=ra2pa(0x47800000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=SCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION replacement2_alias0_8 DATA_VA=0x6014000 attr_data { Name = replacement2_alias0_8, VA=0x6014000, RA=0x48000000, PA=ra2pa(0x48000000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=SCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION replacement3_alias0_8 DATA_VA=0x6016000 attr_data { Name = replacement3_alias0_8, VA=0x6016000, RA=0x48800000, PA=ra2pa(0x48800000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=SCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION replacement4_alias0_8 DATA_VA=0x6018000 attr_data { Name = replacement4_alias0_8, VA=0x6018000, RA=0x49000000, PA=ra2pa(0x49000000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=SCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION replacement5_alias0_8 DATA_VA=0x601a000 attr_data { Name = replacement5_alias0_8, VA=0x601a000, RA=0x49800000, PA=ra2pa(0x49800000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=SCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION replacement6_alias0_8 DATA_VA=0x601c000 attr_data { Name = replacement6_alias0_8, VA=0x601c000, RA=0x4a000000, PA=ra2pa(0x4a000000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=SCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION replacement7_alias0_8 DATA_VA=0x601e000 attr_data { Name = replacement7_alias0_8, VA=0x601e000, RA=0x4a800000, PA=ra2pa(0x4a800000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=SCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION non_fault_area_8 DATA_VA=0x0 attr_data { Name = non_fault_area_8, VA=0x0, RA=0x47002000, PA=ra2pa(0x47002000,0), part_0_ctx_nonzero_tsb_config_0, TTE_G=0, TTE_Context=SCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=1, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=1, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION region0_alias0_0 DATA_VA=0x6000000 attr_data { Name = region0_alias0_0, VA=0x6000000, RA=0x43000000, PA=ra2pa(0x43000000,0), part_0_ctx_zero_tsb_config_2, TTE_G=0, TTE_Context=0, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION region1_alias0_0 DATA_VA=0x6002000 attr_data { Name = region1_alias0_0, VA=0x6002000, RA=0x43800000, PA=ra2pa(0x43800000,0), part_0_ctx_zero_tsb_config_2, TTE_G=0, TTE_Context=0, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION region2_alias0_0 DATA_VA=0x6004000 attr_data { Name = region2_alias0_0, VA=0x6004000, RA=0x44000000, PA=ra2pa(0x44000000,0), part_0_ctx_zero_tsb_config_2, TTE_G=0, TTE_Context=0, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION region3_alias0_0 DATA_VA=0x6006000 attr_data { Name = region3_alias0_0, VA=0x6006000, RA=0x44800000, PA=ra2pa(0x44800000,0), part_0_ctx_zero_tsb_config_2, TTE_G=0, TTE_Context=0, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION region4_alias0_0 DATA_VA=0x6008000 attr_data { Name = region4_alias0_0, VA=0x6008000, RA=0x45000000, PA=ra2pa(0x45000000,0), part_0_ctx_zero_tsb_config_2, TTE_G=0, TTE_Context=0, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION region5_alias0_0 DATA_VA=0x600a000 attr_data { Name = region5_alias0_0, VA=0x600a000, RA=0x45800000, PA=ra2pa(0x45800000,0), part_0_ctx_zero_tsb_config_2, TTE_G=0, TTE_Context=0, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION region6_alias0_0 DATA_VA=0x600c000 attr_data { Name = region6_alias0_0, VA=0x600c000, RA=0x46000000, PA=ra2pa(0x46000000,0), part_0_ctx_zero_tsb_config_2, TTE_G=0, TTE_Context=0, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION region7_alias0_0 DATA_VA=0x600e000 attr_data { Name = region7_alias0_0, VA=0x600e000, RA=0x46800000, PA=ra2pa(0x46800000,0), part_0_ctx_zero_tsb_config_2, TTE_G=0, TTE_Context=0, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION replacement0_alias0_0 DATA_VA=0x6010000 attr_data { Name = replacement0_alias0_0, VA=0x6010000, RA=0x47000000, PA=ra2pa(0x47000000,0), part_0_ctx_zero_tsb_config_2, TTE_G=0, TTE_Context=0, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION replacement1_alias0_0 DATA_VA=0x6012000 attr_data { Name = replacement1_alias0_0, VA=0x6012000, RA=0x47800000, PA=ra2pa(0x47800000,0), part_0_ctx_zero_tsb_config_2, TTE_G=0, TTE_Context=0, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION replacement2_alias0_0 DATA_VA=0x6014000 attr_data { Name = replacement2_alias0_0, VA=0x6014000, RA=0x48000000, PA=ra2pa(0x48000000,0), part_0_ctx_zero_tsb_config_2, TTE_G=0, TTE_Context=0, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION replacement3_alias0_0 DATA_VA=0x6016000 attr_data { Name = replacement3_alias0_0, VA=0x6016000, RA=0x48800000, PA=ra2pa(0x48800000,0), part_0_ctx_zero_tsb_config_2, TTE_G=0, TTE_Context=0, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION replacement4_alias0_0 DATA_VA=0x6018000 attr_data { Name = replacement4_alias0_0, VA=0x6018000, RA=0x49000000, PA=ra2pa(0x49000000,0), part_0_ctx_zero_tsb_config_2, TTE_G=0, TTE_Context=0, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION replacement5_alias0_0 DATA_VA=0x601a000 attr_data { Name = replacement5_alias0_0, VA=0x601a000, RA=0x49800000, PA=ra2pa(0x49800000,0), part_0_ctx_zero_tsb_config_2, TTE_G=0, TTE_Context=0, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION replacement6_alias0_0 DATA_VA=0x601c000 attr_data { Name = replacement6_alias0_0, VA=0x601c000, RA=0x4a000000, PA=ra2pa(0x4a000000,0), part_0_ctx_zero_tsb_config_2, TTE_G=0, TTE_Context=0, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 SECTION replacement7_alias0_0 DATA_VA=0x601e000 attr_data { Name = replacement7_alias0_0, VA=0x601e000, RA=0x4a800000, PA=ra2pa(0x4a800000,0), part_0_ctx_zero_tsb_config_2, TTE_G=0, TTE_Context=0, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1, tsbonly } .data .skip 1024 !------------------------------------------------------------------------ SECTION tsotool_unshared_data .global tsotool_unshared_data_start .global res_buf_fp_p_0 .global res_buf_int_p_0 .global private_data_p0 .global stack_top_p0: .global res_buf_fp_p_1 .global res_buf_int_p_1 .global private_data_p1 .global stack_top_p1: .global res_buf_fp_p_2 .global res_buf_int_p_2 .global private_data_p2 .global stack_top_p2: .global res_buf_fp_p_3 .global res_buf_int_p_3 .global private_data_p3 .global stack_top_p3: .global res_buf_fp_p_4 .global res_buf_int_p_4 .global private_data_p4 .global stack_top_p4: .global res_buf_fp_p_5 .global res_buf_int_p_5 .global private_data_p5 .global stack_top_p5: .global res_buf_fp_p_6 .global res_buf_int_p_6 .global private_data_p6 .global stack_top_p6: .global res_buf_fp_p_7 .global res_buf_int_p_7 .global private_data_p7 .global stack_top_p7: .data ALIGN_PAGE_512K tsotool_unshared_data_start: !-- label names of res_buf must match with extract_loads_m64.pl -- .align 64 ! for self bcopy() res_buf_fp_p_0: .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2 .align 64 ! for self bcopy() res_buf_int_p_0: .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2 .align 64 ! for self bcopy() res_buf_fp_p_1: .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2 .align 64 ! for self bcopy() res_buf_int_p_1: .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2 .align 64 ! for self bcopy() res_buf_fp_p_2: .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2 .align 64 ! for self bcopy() res_buf_int_p_2: .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2 .align 64 ! for self bcopy() res_buf_fp_p_3: .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2 .align 64 ! for self bcopy() res_buf_int_p_3: .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2 .align 64 ! for self bcopy() res_buf_fp_p_4: .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2 .align 64 ! for self bcopy() res_buf_int_p_4: .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2 .align 64 ! for self bcopy() res_buf_fp_p_5: .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2 .align 64 ! for self bcopy() res_buf_int_p_5: .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2 .align 64 ! for self bcopy() res_buf_fp_p_6: .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2 .align 64 ! for self bcopy() res_buf_int_p_6: .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2 .align 64 ! for self bcopy() res_buf_fp_p_7: .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2 .align 64 ! for self bcopy() res_buf_int_p_7: .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2 private_data_p0: .skip PRIVATE_DATA_AREA_PER_CPU_RTL private_data_p1: .skip PRIVATE_DATA_AREA_PER_CPU_RTL private_data_p2: .skip PRIVATE_DATA_AREA_PER_CPU_RTL private_data_p3: .skip PRIVATE_DATA_AREA_PER_CPU_RTL private_data_p4: .skip PRIVATE_DATA_AREA_PER_CPU_RTL private_data_p5: .skip PRIVATE_DATA_AREA_PER_CPU_RTL private_data_p6: .skip PRIVATE_DATA_AREA_PER_CPU_RTL private_data_p7: .skip PRIVATE_DATA_AREA_PER_CPU_RTL stack_top_p0: .skip 2048 stack_top_p1: .skip 2048 stack_top_p2: .skip 2048 stack_top_p3: .skip 2048 stack_top_p4: .skip 2048 stack_top_p5: .skip 2048 stack_top_p6: .skip 2048 stack_top_p7: .skip 2048 tsotool_unshared_data_end: ALIGN_PAGE_512K ! to prevent VAs from running over from this section into shared regions !------------------------------------------------------------------------ .seg "data" ! 8 shared memory regions, 0 alias(es) each (Alias 0 is normal VA) SECTION region0_alias0 .global REGION0_ALIAS0_START .data ALIGN_PAGE_8K REGION0_ALIAS0_START: .skip REGION_MAPPED_SIZE_RTL REGION0_ALIAS0_END: .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL SECTION region1_alias0 .global REGION1_ALIAS0_START .data ALIGN_PAGE_8K REGION1_ALIAS0_START: .skip REGION_MAPPED_SIZE_RTL REGION1_ALIAS0_END: .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL SECTION region2_alias0 .global REGION2_ALIAS0_START .data ALIGN_PAGE_8K REGION2_ALIAS0_START: .skip REGION_MAPPED_SIZE_RTL REGION2_ALIAS0_END: .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL SECTION region3_alias0 .global REGION3_ALIAS0_START .data ALIGN_PAGE_8K REGION3_ALIAS0_START: .skip REGION_MAPPED_SIZE_RTL REGION3_ALIAS0_END: .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL SECTION region4_alias0 .global REGION4_ALIAS0_START .data ALIGN_PAGE_8K REGION4_ALIAS0_START: .skip REGION_MAPPED_SIZE_RTL REGION4_ALIAS0_END: .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL SECTION region5_alias0 .global REGION5_ALIAS0_START .data ALIGN_PAGE_8K REGION5_ALIAS0_START: .skip REGION_MAPPED_SIZE_RTL REGION5_ALIAS0_END: .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL SECTION region6_alias0 .global REGION6_ALIAS0_START .data ALIGN_PAGE_8K REGION6_ALIAS0_START: .skip REGION_MAPPED_SIZE_RTL REGION6_ALIAS0_END: .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL SECTION region7_alias0 .global REGION7_ALIAS0_START .data ALIGN_PAGE_8K REGION7_ALIAS0_START: .skip REGION_MAPPED_SIZE_RTL REGION7_ALIAS0_END: .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL SECTION replacement0_alias0 .global REPLACEMENT0_ALIAS0_START .data ALIGN_PAGE_8K REPLACEMENT0_ALIAS0_START: .skip REGION_MAPPED_SIZE_RTL REPLACEMENT0_ALIAS0_END: .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL SECTION replacement1_alias0 .global REPLACEMENT1_ALIAS0_START .data ALIGN_PAGE_8K REPLACEMENT1_ALIAS0_START: .skip REGION_MAPPED_SIZE_RTL REPLACEMENT1_ALIAS0_END: .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL SECTION replacement2_alias0 .global REPLACEMENT2_ALIAS0_START .data ALIGN_PAGE_8K REPLACEMENT2_ALIAS0_START: .skip REGION_MAPPED_SIZE_RTL REPLACEMENT2_ALIAS0_END: .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL SECTION replacement3_alias0 .global REPLACEMENT3_ALIAS0_START .data ALIGN_PAGE_8K REPLACEMENT3_ALIAS0_START: .skip REGION_MAPPED_SIZE_RTL REPLACEMENT3_ALIAS0_END: .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL SECTION replacement4_alias0 .global REPLACEMENT4_ALIAS0_START .data ALIGN_PAGE_8K REPLACEMENT4_ALIAS0_START: .skip REGION_MAPPED_SIZE_RTL REPLACEMENT4_ALIAS0_END: .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL SECTION replacement5_alias0 .global REPLACEMENT5_ALIAS0_START .data ALIGN_PAGE_8K REPLACEMENT5_ALIAS0_START: .skip REGION_MAPPED_SIZE_RTL REPLACEMENT5_ALIAS0_END: .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL SECTION replacement6_alias0 .global REPLACEMENT6_ALIAS0_START .data ALIGN_PAGE_8K REPLACEMENT6_ALIAS0_START: .skip REGION_MAPPED_SIZE_RTL REPLACEMENT6_ALIAS0_END: .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL SECTION replacement7_alias0 .global REPLACEMENT7_ALIAS0_START .data ALIGN_PAGE_8K REPLACEMENT7_ALIAS0_START: .skip REGION_MAPPED_SIZE_RTL REPLACEMENT7_ALIAS0_END: .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL SECTION .MAIN .global local_trap_handlers_start .global local_trap_handlers_end.global extern_interrupt_handler .text ALIGN_PAGE_8K local_trap_handlers_start: .align 64 extern_interrupt_handler: stxa %g0, [%g0]ASI_INTR_RECEIVE retry local_trap_handlers_end: SECTION .MAIN .global main .global tsotool_text_start .global irepl_text_start .text ba user_text_start nop ALIGN_PAGE_64K irepl_text_start: jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 jmpl %g1+8, %g1 nop .skip 24 ALIGN_PAGE_64K user_text_start: ba main nop user_text_end: ALIGN_PAGE_64K tsotool_text_start: main: mov 0, %o0 mov 0, %o1 CHECK_PROC_ID ! at this point, g1 should have CPU id (0, 1, 2, ...) set REGION0_ALIAS0_START, %o0 ! shared address 0 set REGION1_ALIAS0_START, %o1 ! shared address 1 cmp %g1, 0x7 be setup_p7 nop cmp %g1, 0x6 be setup_p6 nop cmp %g1, 0x5 be setup_p5 nop cmp %g1, 0x4 be setup_p4 nop cmp %g1, 0x3 be setup_p3 nop cmp %g1, 0x2 be setup_p2 nop cmp %g1, 0x1 be setup_p1 nop cmp %g1, 0x0 be setup_p0 nop EXIT_BAD ! Should never reach here nop setup_p0: setx stack_top_p0, %g1, %l1 add %l1, 1024, %sp setx res_buf_fp_p_0, %g1, %o4 setx private_data_p0, %g1, %o5 setx func0, %g1, %l4 call %l4 nop EXIT_GOOD nop setup_p1: setx stack_top_p1, %g1, %l1 add %l1, 1024, %sp setx res_buf_fp_p_1, %g1, %o4 setx private_data_p1, %g1, %o5 setx func1, %g1, %l4 call %l4 nop EXIT_GOOD nop setup_p2: setx stack_top_p2, %g1, %l1 add %l1, 1024, %sp setx res_buf_fp_p_2, %g1, %o4 setx private_data_p2, %g1, %o5 setx func2, %g1, %l4 call %l4 nop EXIT_GOOD nop setup_p3: setx stack_top_p3, %g1, %l1 add %l1, 1024, %sp setx res_buf_fp_p_3, %g1, %o4 setx private_data_p3, %g1, %o5 setx func3, %g1, %l4 call %l4 nop EXIT_GOOD nop setup_p4: setx stack_top_p4, %g1, %l1 add %l1, 1024, %sp setx res_buf_fp_p_4, %g1, %o4 setx private_data_p4, %g1, %o5 setx func4, %g1, %l4 call %l4 nop EXIT_GOOD nop setup_p5: setx stack_top_p5, %g1, %l1 add %l1, 1024, %sp setx res_buf_fp_p_5, %g1, %o4 setx private_data_p5, %g1, %o5 setx func5, %g1, %l4 call %l4 nop EXIT_GOOD nop setup_p6: setx stack_top_p6, %g1, %l1 add %l1, 1024, %sp setx res_buf_fp_p_6, %g1, %o4 setx private_data_p6, %g1, %o5 setx func6, %g1, %l4 call %l4 nop EXIT_GOOD nop setup_p7: setx stack_top_p7, %g1, %l1 add %l1, 1024, %sp setx res_buf_fp_p_7, %g1, %o4 setx private_data_p7, %g1, %o5 setx func7, %g1, %l4 call %l4 nop EXIT_GOOD nop #define NO_REAL_CPUS_MINUS_1 7 !----------------- ! register usage: ! %i0 %i1 : base registers for first 2 regions ! %i2 %i3 : cache registers for 8 regions ! %i4 fixed pointer to per-cpu results area ! %l1 moving pointer to per-cpu FP results area ! %o7 moving pointer to per-cpu integer results area ! %i5 pointer to per-cpu private area ! %l0 holds lfsr, used as source of random bits ! %l2 loop count register ! %f16 running counter for unique fp store values ! %f17 holds increment value for fp counter ! %l4 running counter for unique integer store values (increment value is always 1) ! %l5 move-to register for load values (simulation only) ! %f30 move-to register for FP values (simulation only) ! %i4 holds the instructions count which is used for interrupt ordering ! %i4 holds the thread_id (OBP only) ! %l5 holds the moving pointer for interrupt bonus data (OBP only). Conflicts with RTL/simulation usage ! %l3 %l6 %l7 %o5 : 4 temporary registers ! %o0 %o1 %o2 %o3 %o4 : 5 integer results buffer registers ! %f0-f15 FP results buffer registers ! %f32-f47 FP block load/store registers func0: ! instruction sequence begins save %sp, -192, %sp ! Force %i0-%i3 to be 64-byte aligned add %i0, 63, %i0 andn %i0, 63, %i0 add %i1, 63, %i1 andn %i1, 63, %i1 add %i2, 63, %i2 andn %i2, 63, %i2 add %i3, 63, %i3 andn %i3, 63, %i3 add %i4, 63, %i4 andn %i4, 63, %i4 add %i5, 63, %i5 andn %i5, 63, %i5 ! Initialize pointer to FP load results area mov %i4, %l1 ! Initialize pointer to integer load results area sethi %hi(0x80000), %o7 or %o7, %lo(0x80000), %o7 add %o7, %l1, %o7 ! Reinitialize i4 to 0. i4 will be used to keep the count of analyzable node info mov 0x0, %i4 ! Initialize %f0-%f62 to 0xdeadbee0deadbee1 sethi %hi(0xdeadbee0), %l6 or %l6, %lo(0xdeadbee0), %l6 stw %l6, [%i5] sethi %hi(0xdeadbee1), %l6 or %l6, %lo(0xdeadbee1), %l6 stw %l6, [%i5+4] ldd [%i5], %f0 fmovd %f0, %f2 fmovd %f0, %f4 fmovd %f0, %f6 fmovd %f0, %f8 fmovd %f0, %f10 fmovd %f0, %f12 fmovd %f0, %f14 fmovd %f0, %f16 fmovd %f0, %f18 fmovd %f0, %f20 fmovd %f0, %f22 fmovd %f0, %f24 fmovd %f0, %f26 fmovd %f0, %f28 fmovd %f0, %f30 fmovd %f0, %f32 fmovd %f0, %f34 fmovd %f0, %f36 fmovd %f0, %f38 fmovd %f0, %f40 fmovd %f0, %f42 fmovd %f0, %f44 fmovd %f0, %f46 fmovd %f0, %f48 fmovd %f0, %f50 fmovd %f0, %f52 fmovd %f0, %f54 fmovd %f0, %f56 fmovd %f0, %f58 fmovd %f0, %f60 fmovd %f0, %f62 ! Signature for extract_loads script to start extracting load values for this stream sethi %hi(0x00deade1), %l6 or %l6, %lo(0x00deade1), %l6 stw %l6, [%i5] ld [%i5], %f16 ! Initialize running integer counter in register %l4 sethi %hi(0x1), %l4 or %l4, %lo(0x1), %l4 ! Initialize running FP counter in register %f16 sethi %hi(0x3f800001), %l6 or %l6, %lo(0x3f800001), %l6 stw %l6, [%i5] ld [%i5], %f16 ! Initialize FP counter increment value in register %f17 (constant) sethi %hi(0x34000000), %l6 or %l6, %lo(0x34000000), %l6 stw %l6, [%i5] ld [%i5], %f17 ! Initialize LFSR to 0x7bfe^4 sethi %hi(0x7bfe), %l0 or %l0, %lo(0x7bfe), %l0 mulx %l0, %l0, %l0 mulx %l0, %l0, %l0 BEGIN_NODES0: ! Test instruction sequence for ISTREAM 0 begins P1: !_REPLACEMENT [8] (Int) (Loop entry) sethi %hi(0x5), %l2 or %l2, %lo(0x5), %l2 loop_entry_0_0: sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+0], %l3 st %l3, [%i3+0] add %i3, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] P2: !_LD [33] (Int) (Branch target of P181) sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduw [%i2 + 0], %o0 ! move %o0(lower) -> %o0(upper) sllx %o0, 32, %o0 ba P3 nop TARGET181: ba RET181 nop P3: !_ST [17] (maybe <- 0x1) (Int) (Branch target of P7) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stw %l4, [%i3 + 96 ] add %l4, 1, %l4 ba P4 nop TARGET7: ba RET7 nop P4: !_MEMBAR (FP) membar #StoreLoad P5: !_BLD [21] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f0 membar #Sync ! 3 addresses covered fmovd %f8, %f2 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET5 nop RET5: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P6: !_MEMBAR (FP) P7: !_LD [2] (Int) (CBR) lduw [%i0 + 8], %l3 ! move %l3(lower) -> %o0(lower) or %l3, %o0, %o0 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET7 nop RET7: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P8: !_MEMBAR (FP) membar #StoreLoad P9: !_BLD [23] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 fmovs %f19, %f4 fmovd %f40, %f18 fmovs %f18, %f5 P10: !_MEMBAR (FP) P11: !_BST [22] (maybe <- 0x3f800001) (FP) (CBR) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET11 nop RET11: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P12: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET12 nop RET12: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P13: !_BST [1] (maybe <- 0x3f800004) (FP) (Secondary ctx) wr %g0, 0xf1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P14: !_MEMBAR (FP) (Secondary ctx) P15: !_BSTC [31] (maybe <- 0x3f800009) (FP) (Branch target of P216) wr %g0, 0xe0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 192 ] %asi ba P16 nop TARGET216: ba RET216 nop P16: !_MEMBAR (FP) P17: !_BSTC [6] (maybe <- 0x3f80000a) (FP) (Branch target of P53) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 64 ] %asi ba P18 nop TARGET53: ba RET53 nop P18: !_MEMBAR (FP) membar #StoreLoad P19: !_REPLACEMENT [29] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+64], %l7 st %l7, [%i2+64] add %i2, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] P20: !_REPLACEMENT [16] (Int) sethi %hi(0x2000), %o5 ld [%i2+16], %l6 st %l6, [%i2+16] add %i2, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] P21: !_MEMBAR (FP) P22: !_BST [30] (maybe <- 0x3f80000c) (FP) (CBR) (Branch target of P57) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 128 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET22 nop RET22: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P23 nop TARGET57: ba RET57 nop P23: !_MEMBAR (FP) membar #StoreLoad P24: !_REPLACEMENT [25] (Int) sethi %hi(0x2000), %l7 ld [%i2+96], %l3 st %l3, [%i2+96] add %i2, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] P25: !_IDC_FLIP [33] (Int) (Branch target of P86) sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 IDC_FLIP(25, 17498, 0, 0x46800000, 0x0, %i3, 0x0, %l6, %l7, %o5, %l3) ba P26 nop TARGET86: ba RET86 nop P26: !_LD [22] (FP) (CBR) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ld [%i2 + 4], %f6 ! 1 addresses covered ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET26 nop RET26: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P27: !_ST [17] (maybe <- 0x3f80000d) (FP) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 96 ] P28: !_MEMBAR (FP) membar #StoreLoad P29: !_BLD [3] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 fmovs %f19, %f8 fmovd %f34, %f18 fmovs %f18, %f9 fmovd %f36, %f10 fmovd %f40, %f18 fmovs %f18, %f11 P30: !_MEMBAR (FP) (Branch target of P87) ba P31 nop TARGET87: ba RET87 nop P31: !_REPLACEMENT [2] (Int) (CBR) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l6 ld [%i2+8], %o5 st %o5, [%i2+8] add %i2, %l6, %l7 ld [%l7+8], %o5 st %o5, [%l7+8] add %l7, %l6, %l7 ld [%l7+8], %o5 st %o5, [%l7+8] add %l7, %l6, %l7 ld [%l7+8], %o5 st %o5, [%l7+8] add %l7, %l6, %l7 ld [%l7+8], %o5 st %o5, [%l7+8] add %l7, %l6, %l7 ld [%l7+8], %o5 st %o5, [%l7+8] add %l7, %l6, %l7 ld [%l7+8], %o5 st %o5, [%l7+8] add %l7, %l6, %l7 ld [%l7+8], %o5 st %o5, [%l7+8] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET31 nop RET31: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P32: !_MEMBAR (FP) (Branch target of P64) ba P33 nop TARGET64: ba RET64 nop P33: !_BST [18] (maybe <- 0x3f80000e) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 128 ] %asi P34: !_MEMBAR (FP) P35: !_BST [7] (maybe <- 0x3f80000f) (FP) (CBR) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i0 + 128 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET35 nop RET35: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P36: !_MEMBAR (FP) membar #StoreLoad P37: !_BLD [20] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f12 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET37 nop RET37: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P38: !_MEMBAR (FP) P39: !_ST [23] (maybe <- 0x2) (Int) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 stw %l4, [%i2 + 32 ] add %l4, 1, %l4 P40: !_IDC_FLIP [8] (Int) IDC_FLIP(40, 16893, 0, 0x43800000, 0x0, %i1, 0x0, %l6, %l7, %o5, %l3) P41: !_MEMBAR (FP) P42: !_BSTC [3] (maybe <- 0x3f800010) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P43: !_MEMBAR (FP) membar #StoreLoad P44: !_BLD [29] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 P45: !_MEMBAR (FP) P46: !_BLD [27] (FP) (CBR) (Branch target of P5) wr %g0, 0xf0, %asi ldda [%i2 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f14 fmovd %f40, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET46 nop RET46: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P47 nop TARGET5: ba RET5 nop P47: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET47 nop RET47: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P48: !_REPLACEMENT [30] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l7 ld [%i2+128], %l3 st %l3, [%i2+128] add %i2, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] P49: !_MEMBAR (FP) P50: !_BST [24] (maybe <- 0x3f800015) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 64 ] %asi P51: !_MEMBAR (FP) P52: !_BSTC [0] (maybe <- 0x3f800017) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P53: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET53 nop RET53: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P54: !_LD [24] (FP) ld [%i3 + 64], %f0 ! 1 addresses covered P55: !_MEMBAR (FP) membar #StoreLoad P56: !_BLD [27] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 fmovd %f40, %f2 P57: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET57 nop RET57: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P58: !_REPLACEMENT [28] (Int) (CBR) (Branch target of P235) sethi %hi(0x2000), %l6 ld [%i2+0], %o5 st %o5, [%i2+0] add %i2, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET58 nop RET58: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P59 nop TARGET235: ba RET235 nop P59: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P60: !_BLD [23] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 fmovs %f19, %f4 fmovd %f40, %f18 fmovs %f18, %f5 P61: !_MEMBAR (FP) (Secondary ctx) (Branch target of P206) ba P62 nop TARGET206: ba RET206 nop P62: !_BST [0] (maybe <- 0x3f80001c) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P63: !_MEMBAR (FP) membar #StoreLoad P64: !_LD [31] (Int) (CBR) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduw [%i2 + 192], %o1 ! move %o1(lower) -> %o1(upper) sllx %o1, 32, %o1 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET64 nop RET64: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P65: !_MEMBAR (FP) membar #StoreLoad P66: !_BLD [0] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f6 fmovd %f34, %f8 fmovd %f36, %f18 fmovs %f18, %f9 fmovd %f40, %f10 P67: !_MEMBAR (FP) (Branch target of P136) ba P68 nop TARGET136: ba RET136 nop P68: !_LD [27] (Int) (CBR) (Branch target of P84) lduw [%i3 + 160], %l3 ! move %l3(lower) -> %o1(lower) or %l3, %o1, %o1 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET68 nop RET68: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P69 nop TARGET84: ba RET84 nop P69: !_MEMBAR (FP) P70: !_BST [11] (maybe <- 0x3f800021) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P71: !_MEMBAR (FP) P72: !_BST [8] (maybe <- 0x3f800024) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i1 + 0 ] %asi P73: !_MEMBAR (FP) membar #StoreLoad P74: !_BLD [10] (FP) wr %g0, 0xf0, %asi ldda [%i1 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 P75: !_MEMBAR (FP) P76: !_REPLACEMENT [15] (Int) (CBR) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+128], %l7 st %l7, [%i2+128] add %i2, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET76 nop RET76: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P77: !_MEMBAR (FP) membar #StoreLoad P78: !_BLD [30] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f12 P79: !_MEMBAR (FP) P80: !_LD [32] (Int) (Branch target of P88) lduw [%i3 + 256], %o2 ! move %o2(lower) -> %o2(upper) sllx %o2, 32, %o2 ba P81 nop TARGET88: ba RET88 nop P81: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET81 nop RET81: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P82: !_BLD [2] (FP) (Branch target of P93) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 fmovs %f19, %f14 fmovd %f34, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f36, %f0 fmovd %f40, %f18 fmovs %f18, %f1 ba P83 nop TARGET93: ba RET93 nop P83: !_MEMBAR (FP) P84: !_BLD [7] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i0 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f2 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET84 nop RET84: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P85: !_MEMBAR (FP) P86: !_REPLACEMENT [18] (Int) (CBR) sethi %hi(0x2000), %l3 ld [%i2+128], %l7 st %l7, [%i2+128] add %i2, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET86 nop RET86: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P87: !_LD [6] (FP) (CBR) ld [%i0 + 96], %f3 ! 1 addresses covered ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET87 nop RET87: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P88: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET88 nop RET88: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P89: !_BLD [22] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f4 fmovd %f40, %f6 P90: !_MEMBAR (FP) P91: !_BSTC [2] (maybe <- 0x3f800026) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P92: !_MEMBAR (FP) P93: !_BSTC [1] (maybe <- 0x3f80002b) (FP) (CBR) (Secondary ctx) wr %g0, 0xe1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET93 nop RET93: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P94: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P95: !_PREFETCH [14] (Int) (LE) (Branch target of P22) wr %g0, 0x88, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetcha [%i3 + 64] %asi, 1 ba P96 nop TARGET22: ba RET22 nop P96: !_LD [18] (FP) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ld [%i2 + 128], %f7 ! 1 addresses covered P97: !_LD [27] (FP) (CBR) (Branch target of P35) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ld [%i3 + 160], %f8 ! 1 addresses covered ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET97 nop RET97: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P98 nop TARGET35: ba RET35 nop P98: !_ST [32] (maybe <- 0x3) (Int) (CBR) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 stw %l4, [%i2 + 256 ] add %l4, 1, %l4 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET98 nop RET98: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P99: !_IDC_FLIP [31] (Int) IDC_FLIP(99, 12346, 0, 0x460000c0, 0xc0, %i2, 0xc0, %l6, %l7, %o5, %l3) P100: !_MEMBAR (FP) membar #StoreLoad P101: !_BLD [26] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f9 fmovd %f40, %f10 P102: !_MEMBAR (FP) P103: !_IDC_FLIP [7] (Int) IDC_FLIP(103, 25991, 0, 0x43000080, 0x80, %i0, 0x80, %l6, %l7, %o5, %l3) P104: !_IDC_FLIP [17] (Int) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 IDC_FLIP(104, 14968, 0, 0x44800060, 0x60, %i3, 0x60, %l6, %l7, %o5, %l3) P105: !_MEMBAR (FP) (Secondary ctx) P106: !_BSTC [29] (maybe <- 0x3f800030) (FP) (Secondary ctx) wr %g0, 0xe1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 64 ] %asi P107: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P108: !_REPLACEMENT [29] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+64], %l7 st %l7, [%i2+64] add %i2, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] P109: !_PREFETCH [33] (Int) sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 0], 1 P110: !_REPLACEMENT [29] (Int) sethi %hi(0x2000), %o5 ld [%i2+64], %l6 st %l6, [%i2+64] add %i2, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] P111: !_MEMBAR (FP) P112: !_BST [22] (maybe <- 0x3f800031) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P113: !_MEMBAR (FP) membar #StoreLoad P114: !_REPLACEMENT [12] (Int) (Branch target of P123) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l6 ld [%i3+4], %o5 st %o5, [%i3+4] add %i3, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] ba P115 nop TARGET123: ba RET123 nop P115: !_MEMBAR (FP) P116: !_BST [3] (maybe <- 0x3f800034) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P117: !_MEMBAR (FP) membar #StoreLoad P118: !_REPLACEMENT [9] (Int) sethi %hi(0x2000), %o5 ld [%i3+32], %l6 st %l6, [%i3+32] add %i3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] P119: !_ST [8] (maybe <- 0x3f800039) (FP) (Secondary ctx) wr %g0, 0x81, %asi ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i1 + 0 ] %asi P120: !_PREFETCH [12] (Int) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 4], 1 P121: !_MEMBAR (FP) membar #StoreLoad P122: !_BLD [32] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 P123: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET123 nop RET123: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P124: !_IDC_FLIP [11] (Int) (Branch target of P97) IDC_FLIP(124, 11466, 0, 0x44000000, 0x0, %i2, 0x0, %l6, %l7, %o5, %l3) ba P125 nop TARGET97: ba RET97 nop P125: !_LD [2] (FP) ld [%i0 + 8], %f12 ! 1 addresses covered P126: !_ST [24] (maybe <- 0x4) (Int) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 stw %l4, [%i2 + 64 ] add %l4, 1, %l4 P127: !_LD [27] (Int) lduw [%i2 + 160], %l6 ! move %l6(lower) -> %o2(lower) or %l6, %o2, %o2 P128: !_MEMBAR (FP) membar #StoreLoad P129: !_BLD [24] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i2 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 fmovd %f40, %f14 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET129 nop RET129: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P130: !_MEMBAR (FP) P131: !_BST [11] (maybe <- 0x3f80003a) (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET131 nop RET131: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P132: !_MEMBAR (FP) membar #StoreLoad P133: !_REPLACEMENT [11] (Int) (Branch target of P160) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %o5 ld [%i2+0], %l6 st %l6, [%i2+0] add %i2, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] ba P134 nop TARGET160: ba RET160 nop P134: !_ST [12] (maybe <- 0x5) (Int) (CBR) stw %l4, [%i3 + 4 ] add %l4, 1, %l4 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET134 nop RET134: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P135: !_PREFETCH [4] (Int) (LE) wr %g0, 0x88, %asi prefetcha [%i0 + 32] %asi, 1 P136: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET136 nop RET136: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P137: !_BSTC [20] (maybe <- 0x3f80003d) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 256 ] %asi P138: !_MEMBAR (FP) (Branch target of P76) membar #StoreLoad ba P139 nop TARGET76: ba RET76 nop P139: !_LD [20] (Int) (Nucleus ctx) wr %g0, 0x4, %asi lduwa [%i3 + 256] %asi, %o3 ! move %o3(lower) -> %o3(upper) sllx %o3, 32, %o3 P140: !_MEMBAR (FP) P141: !_BSTC [7] (maybe <- 0x3f80003e) (FP) (Branch target of P68) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i0 + 128 ] %asi ba P142 nop TARGET68: ba RET68 nop P142: !_MEMBAR (FP) (Branch target of P134) ba P143 nop TARGET134: ba RET134 nop P143: !_BSTC [19] (maybe <- 0x3f80003f) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 0 ] %asi P144: !_MEMBAR (FP) membar #StoreLoad P145: !_BLD [8] (FP) (Branch target of P168) wr %g0, 0xf0, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f40, %f0 ba P146 nop TARGET168: ba RET168 nop P146: !_MEMBAR (FP) P147: !_BSTC [11] (maybe <- 0x3f800040) (FP) (Branch target of P230) wr %g0, 0xe0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi ba P148 nop TARGET230: ba RET230 nop P148: !_MEMBAR (FP) (Branch target of P58) membar #StoreLoad ba P149 nop TARGET58: ba RET58 nop P149: !_PREFETCH [26] (Int) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 128], 1 P150: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET150 nop RET150: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P151: !_BLD [16] (FP) (CBR) (Branch target of P37) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f36, %f18 fmovs %f18, %f1 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET151 nop RET151: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P152 nop TARGET37: ba RET37 nop P152: !_MEMBAR (FP) P153: !_REPLACEMENT [17] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %o5 ld [%i3+96], %l6 st %l6, [%i3+96] add %i3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] P154: !_LD [12] (FP) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lda [%i2 + 4] %asi, %f2 ! 1 addresses covered P155: !_MEMBAR (FP) (Secondary ctx) (Branch target of P188) ba P156 nop TARGET188: ba RET188 nop P156: !_BST [9] (maybe <- 0x3f800043) (FP) (Secondary ctx) wr %g0, 0xf1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i1 + 0 ] %asi P157: !_MEMBAR (FP) (Secondary ctx) P158: !_BST [29] (maybe <- 0x3f800045) (FP) (CBR) (Branch target of P158) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET158 nop RET158: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P159 nop TARGET158: ba RET158 nop P159: !_MEMBAR (FP) (Branch target of P190) ba P160 nop TARGET190: ba RET190 nop P160: !_BSTC [0] (maybe <- 0x3f800046) (FP) (CBR) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET160 nop RET160: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P161: !_MEMBAR (FP) membar #StoreLoad P162: !_PREFETCH [7] (Int) prefetch [%i0 + 128], 1 P163: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P164: !_BLD [15] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i2 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 P165: !_MEMBAR (FP) (Secondary ctx) (Branch target of P213) ba P166 nop TARGET213: ba RET213 nop P166: !_BLD [33] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f4 P167: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET167 nop RET167: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P168: !_ST [27] (maybe <- 0x6) (Int) (CBR) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stw %l4, [%i3 + 160 ] add %l4, 1, %l4 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET168 nop RET168: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P169: !_PREFETCH [21] (Int) (CBR) prefetch [%i3 + 0], 1 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET169 nop RET169: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P170: !_LD [14] (Int) (Branch target of P169) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduw [%i2 + 64], %l3 ! move %l3(lower) -> %o3(lower) or %l3, %o3, %o3 ba P171 nop TARGET169: ba RET169 nop P171: !_MEMBAR (FP) (Branch target of P223) ba P172 nop TARGET223: ba RET223 nop P172: !_BST [6] (maybe <- 0x3f80004b) (FP) (CBR) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET172 nop RET172: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P173: !_MEMBAR (FP) membar #StoreLoad P174: !_ST [33] (maybe <- 0x7) (Int) (LE) (Nucleus ctx) wr %g0, 0xc, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! Change single-word-level endianess (big endian <-> little endian) sethi %hi(0xff00ff00), %l7 or %l7, %lo(0xff00ff00), %l7 and %l4, %l7, %o5 srl %o5, 8, %o5 sll %l4, 8, %l6 and %l6, %l7, %l6 or %l6, %o5, %l6 srl %l6, 16, %o5 sll %l6, 16, %l6 srl %l6, 0, %l6 or %l6, %o5, %l6 stwa %l6, [%i3 + 0] %asi add %l4, 1, %l4 P175: !_MEMBAR (FP) (CBR) (Branch target of P11) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET175 nop RET175: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P176 nop TARGET11: ba RET11 nop P176: !_BLD [23] (FP) (Branch target of P81) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 fmovs %f19, %f6 fmovd %f40, %f18 fmovs %f18, %f7 ba P177 nop TARGET81: ba RET81 nop P177: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET177 nop RET177: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P178: !_BLD [1] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f8 fmovd %f34, %f10 fmovd %f36, %f18 fmovs %f18, %f11 fmovd %f40, %f12 P179: !_MEMBAR (FP) (Branch target of P167) ba P180 nop TARGET167: ba RET167 nop P180: !_BLD [22] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 fmovs %f19, %f14 fmovd %f40, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- P181: !_MEMBAR (FP) (CBR) (Secondary ctx) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET181 nop RET181: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P182: !_LD [17] (FP) (Branch target of P177) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ld [%i3 + 96], %f0 ! 1 addresses covered ba P183 nop TARGET177: ba RET177 nop P183: !_LD [18] (FP) (Nucleus ctx) wr %g0, 0x4, %asi lda [%i3 + 128] %asi, %f1 ! 1 addresses covered P184: !_MEMBAR (FP) membar #StoreLoad P185: !_BLD [20] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f2 P186: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET186 nop RET186: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P187: !_REPLACEMENT [5] (Int) (Branch target of P172) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+64], %l7 st %l7, [%i3+64] add %i3, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] ba P188 nop TARGET172: ba RET172 nop P188: !_MEMBAR (FP) (CBR) (Branch target of P150) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET188 nop RET188: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 ba P189 nop TARGET150: ba RET150 nop P189: !_BLD [11] (FP) (Branch target of P129) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 fmovs %f19, %f4 fmovd %f40, %f18 fmovs %f18, %f5 ba P190 nop TARGET129: ba RET129 nop P190: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET190 nop RET190: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P191: !_REPLACEMENT [28] (Int) (Secondary ctx) (Branch target of P12) wr %g0, 0x81, %asi sethi %hi(0x2000), %l6 ld [%i3+0], %o5 st %o5, [%i3+0] add %i3, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] ba P192 nop TARGET12: ba RET12 nop P192: !_PREFETCH [4] (Int) (Nucleus ctx) wr %g0, 0x4, %asi prefetcha [%i0 + 32] %asi, 1 P193: !_PREFETCH [21] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetcha [%i3 + 0] %asi, 1 P194: !_ST [24] (maybe <- 0x3f80004d) (FP) (CBR) (Branch target of P131) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 64 ] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET194 nop RET194: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 ba P195 nop TARGET131: ba RET131 nop P195: !_ST [5] (maybe <- 0x8) (Int) (LE) wr %g0, 0x88, %asi ! Change single-word-level endianess (big endian <-> little endian) sethi %hi(0xff00ff00), %l6 or %l6, %lo(0xff00ff00), %l6 and %l4, %l6, %l7 srl %l7, 8, %l7 sll %l4, 8, %l3 and %l3, %l6, %l3 or %l3, %l7, %l3 srl %l3, 16, %l7 sll %l3, 16, %l3 srl %l3, 0, %l3 or %l3, %l7, %l3 stwa %l3, [%i0 + 64] %asi add %l4, 1, %l4 P196: !_FLUSHI [0] (Int) flush %g0 P197: !_ST [4] (maybe <- 0x9) (Int) (Branch target of P151) stw %l4, [%i0 + 32 ] add %l4, 1, %l4 ba P198 nop TARGET151: ba RET151 nop P198: !_REPLACEMENT [32] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l7 ld [%i2+256], %l3 st %l3, [%i2+256] add %i2, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] P199: !_MEMBAR (FP) P200: !_BSTC [23] (maybe <- 0x3f80004e) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P201: !_MEMBAR (FP) (Branch target of P212) ba P202 nop TARGET212: ba RET212 nop P202: !_BST [10] (maybe <- 0x3f800051) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i1 + 64 ] %asi P203: !_MEMBAR (FP) (Branch target of P186) membar #StoreLoad ba P204 nop TARGET186: ba RET186 nop P204: !_ST [28] (maybe <- 0x3f800052) (FP) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 0 ] P205: !_MEMBAR (FP) membar #StoreLoad P206: !_BLD [3] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f6 fmovd %f34, %f8 fmovd %f36, %f18 fmovs %f18, %f9 fmovd %f40, %f10 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET206 nop RET206: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P207: !_MEMBAR (FP) P208: !_ST [7] (maybe <- 0xa) (Int) stw %l4, [%i0 + 128 ] add %l4, 1, %l4 P209: !_MEMBAR (FP) (Branch target of P47) ba P210 nop TARGET47: ba RET47 nop P210: !_BST [15] (maybe <- 0x3f800053) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 128 ] %asi P211: !_MEMBAR (FP) (Branch target of P98) membar #StoreLoad ba P212 nop TARGET98: ba RET98 nop P212: !_REPLACEMENT [1] (Int) (CBR) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l6 ld [%i3+4], %o5 st %o5, [%i3+4] add %i3, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET212 nop RET212: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P213: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET213 nop RET213: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P214: !_BLD [14] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 P215: !_MEMBAR (FP) P216: !_BSTC [33] (maybe <- 0x3f800054) (FP) (CBR) wr %g0, 0xe0, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET216 nop RET216: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P217: !_MEMBAR (FP) P218: !_BSTC [2] (maybe <- 0x3f800055) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P219: !_MEMBAR (FP) (Branch target of P194) membar #StoreLoad ba P220 nop TARGET194: ba RET194 nop P220: !_ST [19] (maybe <- 0x3f80005a) (FP) (Branch target of P31) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 0 ] ba P221 nop TARGET31: ba RET31 nop P221: !_MEMBAR (FP) P222: !_BST [10] (maybe <- 0x3f80005b) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i1 + 64 ] %asi P223: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET223 nop RET223: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P224: !_REPLACEMENT [21] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+0], %l7 st %l7, [%i2+0] add %i2, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] P225: !_MEMBAR (FP) (Branch target of P175) membar #StoreLoad ba P226 nop TARGET175: ba RET175 nop P226: !_BLD [6] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f12 fmovd %f40, %f18 fmovs %f18, %f13 P227: !_MEMBAR (FP) P228: !_BLD [26] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f14 fmovd %f40, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- P229: !_MEMBAR (FP) P230: !_LD [22] (Int) (CBR) (Secondary ctx) (Branch target of P46) wr %g0, 0x81, %asi lduwa [%i3 + 4] %asi, %o4 ! move %o4(lower) -> %o4(upper) sllx %o4, 32, %o4 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET230 nop RET230: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P231 nop TARGET46: ba RET46 nop P231: !_MEMBAR (FP) membar #StoreLoad P232: !_BLD [33] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f0 membar #Sync ! 1 addresses covered P233: !_MEMBAR (FP) P234: !_BST [7] (maybe <- 0x3f80005c) (FP) (Branch target of P26) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i0 + 128 ] %asi ba P235 nop TARGET26: ba RET26 nop P235: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET235 nop RET235: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P236: !_LD [28] (Int) (Loop exit) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lduw [%i3 + 0], %o5 ! move %o5(lower) -> %o4(lower) or %o5, %o4, %o4 !---- flushing int results buffer---- mov %o0, %l5 mov %o1, %l5 mov %o2, %l5 mov %o3, %l5 mov %o4, %l5 !---- flushing fp results buffer to %f30 ---- fmovs %f0, %f30 !-- loop_exit_0_0: sub %l2, 1, %l2 cmp %l2, 0 bg loop_entry_0_0 nop P237: !_MEMBAR (Int) membar #StoreLoad END_NODES0: ! Test instruction sequence for CPU 0 ends sethi %hi(0xdead0e0f), %l6 or %l6, %lo(0xdead0e0f), %l6 ! move %l6(lower) -> %o0(upper) sllx %l6, 32, %o0 sethi %hi(0xdead0e0f), %l6 or %l6, %lo(0xdead0e0f), %l6 stw %l6, [%i5] ld [%i5], %f0 !---- flushing int results buffer---- mov %o0, %l5 !---- flushing fp results buffer to %f30 ---- fmovs %f0, %f30 !-- restore retl nop !----------------- ! register usage: ! %i0 %i1 : base registers for first 2 regions ! %i2 %i3 : cache registers for 8 regions ! %i4 fixed pointer to per-cpu results area ! %l1 moving pointer to per-cpu FP results area ! %o7 moving pointer to per-cpu integer results area ! %i5 pointer to per-cpu private area ! %l0 holds lfsr, used as source of random bits ! %l2 loop count register ! %f16 running counter for unique fp store values ! %f17 holds increment value for fp counter ! %l4 running counter for unique integer store values (increment value is always 1) ! %l5 move-to register for load values (simulation only) ! %f30 move-to register for FP values (simulation only) ! %i4 holds the instructions count which is used for interrupt ordering ! %i4 holds the thread_id (OBP only) ! %l5 holds the moving pointer for interrupt bonus data (OBP only). Conflicts with RTL/simulation usage ! %l3 %l6 %l7 %o5 : 4 temporary registers ! %o0 %o1 %o2 %o3 %o4 : 5 integer results buffer registers ! %f0-f15 FP results buffer registers ! %f32-f47 FP block load/store registers func1: ! instruction sequence begins save %sp, -192, %sp ! Force %i0-%i3 to be 64-byte aligned add %i0, 63, %i0 andn %i0, 63, %i0 add %i1, 63, %i1 andn %i1, 63, %i1 add %i2, 63, %i2 andn %i2, 63, %i2 add %i3, 63, %i3 andn %i3, 63, %i3 add %i4, 63, %i4 andn %i4, 63, %i4 add %i5, 63, %i5 andn %i5, 63, %i5 ! Initialize pointer to FP load results area mov %i4, %l1 ! Initialize pointer to integer load results area sethi %hi(0x80000), %o7 or %o7, %lo(0x80000), %o7 add %o7, %l1, %o7 ! Reinitialize i4 to 0. i4 will be used to keep the count of analyzable node info mov 0x0, %i4 ! Initialize %f0-%f62 to 0xdeadbee0deadbee1 sethi %hi(0xdeadbee0), %l3 or %l3, %lo(0xdeadbee0), %l3 stw %l3, [%i5] sethi %hi(0xdeadbee1), %l3 or %l3, %lo(0xdeadbee1), %l3 stw %l3, [%i5+4] ldd [%i5], %f0 fmovd %f0, %f2 fmovd %f0, %f4 fmovd %f0, %f6 fmovd %f0, %f8 fmovd %f0, %f10 fmovd %f0, %f12 fmovd %f0, %f14 fmovd %f0, %f16 fmovd %f0, %f18 fmovd %f0, %f20 fmovd %f0, %f22 fmovd %f0, %f24 fmovd %f0, %f26 fmovd %f0, %f28 fmovd %f0, %f30 fmovd %f0, %f32 fmovd %f0, %f34 fmovd %f0, %f36 fmovd %f0, %f38 fmovd %f0, %f40 fmovd %f0, %f42 fmovd %f0, %f44 fmovd %f0, %f46 fmovd %f0, %f48 fmovd %f0, %f50 fmovd %f0, %f52 fmovd %f0, %f54 fmovd %f0, %f56 fmovd %f0, %f58 fmovd %f0, %f60 fmovd %f0, %f62 ! Signature for extract_loads script to start extracting load values for this stream sethi %hi(0x01deade1), %l3 or %l3, %lo(0x01deade1), %l3 stw %l3, [%i5] ld [%i5], %f16 ! Initialize running integer counter in register %l4 sethi %hi(0x800001), %l4 or %l4, %lo(0x800001), %l4 ! Initialize running FP counter in register %f16 sethi %hi(0x40000001), %l3 or %l3, %lo(0x40000001), %l3 stw %l3, [%i5] ld [%i5], %f16 ! Initialize FP counter increment value in register %f17 (constant) sethi %hi(0x34800000), %l3 or %l3, %lo(0x34800000), %l3 stw %l3, [%i5] ld [%i5], %f17 ! Initialize LFSR to 0x1a12^4 sethi %hi(0x1a12), %l0 or %l0, %lo(0x1a12), %l0 mulx %l0, %l0, %l0 mulx %l0, %l0, %l0 BEGIN_NODES1: ! Test instruction sequence for ISTREAM 1 begins P238: !_MEMBAR (FP) (Loop entry) (CBR) sethi %hi(0x3), %l2 or %l2, %lo(0x3), %l2 loop_entry_1_0: membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET238 nop RET238: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P239: !_BLD [4] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f0 membar #Sync ! 5 addresses covered fmovs %f4, %f3 fmovd %f8, %f4 P240: !_MEMBAR (FP) P241: !_IDC_FLIP [19] (Int) (Branch target of P469) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 IDC_FLIP(241, 5930, 1, 0x45000000, 0x0, %i2, 0x0, %l6, %l7, %o5, %l3) ba P242 nop TARGET469: ba RET469 nop P242: !_MEMBAR (FP) (Branch target of P410) membar #StoreLoad ba P243 nop TARGET410: ba RET410 nop P243: !_BLD [8] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 fmovd %f40, %f6 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET243 nop RET243: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P244: !_MEMBAR (FP) P245: !_PREFETCH [13] (Int) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 32], 1 P246: !_REPLACEMENT [18] (Int) (CBR) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l7 ld [%i2+128], %l3 st %l3, [%i2+128] add %i2, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET246 nop RET246: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P247: !_LD [14] (FP) (CBR) ld [%i3 + 64], %f7 ! 1 addresses covered ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET247 nop RET247: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P248: !_MEMBAR (FP) (Secondary ctx) P249: !_BST [16] (maybe <- 0x40000001) (FP) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f36 membar #Sync stda %f32, [%i3 + 0 ] %asi P250: !_MEMBAR (FP) (Secondary ctx) (Branch target of P480) membar #StoreLoad ba P251 nop TARGET480: ba RET480 nop P251: !_BLD [5] (FP) (Branch target of P645) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f8 fmovd %f40, %f18 fmovs %f18, %f9 ba P252 nop TARGET645: ba RET645 nop P252: !_MEMBAR (FP) P253: !_BSTC [14] (maybe <- 0x40000002) (FP) (CBR) (Branch target of P284) wr %g0, 0xe0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET253 nop RET253: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P254 nop TARGET284: ba RET284 nop P254: !_MEMBAR (FP) membar #StoreLoad P255: !_REPLACEMENT [13] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+32], %l3 st %l3, [%i3+32] add %i3, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] P256: !_PREFETCH [17] (Int) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 96], 1 P257: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET257 nop RET257: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P258: !_BST [18] (maybe <- 0x40000003) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 128 ] %asi P259: !_MEMBAR (FP) (Branch target of P560) membar #StoreLoad ba P260 nop TARGET560: ba RET560 nop P260: !_LD [24] (FP) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ld [%i3 + 64], %f10 ! 1 addresses covered P261: !_REPLACEMENT [24] (Int) (CBR) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l6 ld [%i2+64], %o5 st %o5, [%i2+64] add %i2, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET261 nop RET261: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P262: !_MEMBAR (FP) (CBR) (Secondary ctx) (Branch target of P262) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET262 nop RET262: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P263 nop TARGET262: ba RET262 nop P263: !_BST [24] (maybe <- 0x40000004) (FP) (Secondary ctx) wr %g0, 0xf1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 64 ] %asi P264: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P265: !_LD [22] (Int) (Branch target of P577) lduw [%i3 + 4], %o0 ! move %o0(lower) -> %o0(upper) sllx %o0, 32, %o0 ba P266 nop TARGET577: ba RET577 nop P266: !_MEMBAR (FP) P267: !_BST [1] (maybe <- 0x40000006) (FP) (CBR) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET267 nop RET267: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P268: !_MEMBAR (FP) P269: !_BSTC [13] (maybe <- 0x4000000b) (FP) (Branch target of P627) wr %g0, 0xe0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi ba P270 nop TARGET627: ba RET627 nop P270: !_MEMBAR (FP) membar #StoreLoad P271: !_PREFETCH [31] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetcha [%i2 + 192] %asi, 1 P272: !_LD [11] (Int) lduw [%i3 + 0], %o5 ! move %o5(lower) -> %o0(lower) or %o5, %o0, %o0 P273: !_LD [9] (Int) lduw [%i1 + 32], %o1 ! move %o1(lower) -> %o1(upper) sllx %o1, 32, %o1 P274: !_REPLACEMENT [20] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+256], %l3 st %l3, [%i3+256] add %i3, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] P275: !_REPLACEMENT [20] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(0x2000), %l6 ld [%i3+256], %o5 st %o5, [%i3+256] add %i3, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] P276: !_MEMBAR (FP) membar #StoreLoad P277: !_BLD [21] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 fmovs %f19, %f12 fmovd %f40, %f18 fmovs %f18, %f13 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET277 nop RET277: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P278: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET278 nop RET278: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P279: !_BSTC [30] (maybe <- 0x4000000e) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 128 ] %asi P280: !_MEMBAR (FP) P281: !_BSTC [15] (maybe <- 0x4000000f) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 128 ] %asi P282: !_MEMBAR (FP) (Branch target of P407) membar #StoreLoad ba P283 nop TARGET407: ba RET407 nop P283: !_PREFETCH [12] (Int) (CBR) prefetch [%i2 + 4], 1 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET283 nop RET283: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P284: !_LD [26] (FP) (CBR) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ld [%i3 + 128], %f14 ! 1 addresses covered ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET284 nop RET284: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P285: !_MEMBAR (FP) (Branch target of P293) membar #StoreLoad ba P286 nop TARGET293: ba RET293 nop P286: !_BLD [20] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- P287: !_MEMBAR (FP) P288: !_BST [0] (maybe <- 0x40000010) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P289: !_MEMBAR (FP) (Branch target of P634) membar #StoreLoad ba P290 nop TARGET634: ba RET634 nop P290: !_REPLACEMENT [21] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l6 ld [%i3+0], %o5 st %o5, [%i3+0] add %i3, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] P291: !_REPLACEMENT [1] (Int) sethi %hi(0x2000), %l3 ld [%i3+4], %l7 st %l7, [%i3+4] add %i3, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] P292: !_REPLACEMENT [29] (Int) (CBR) sethi %hi(0x2000), %o5 ld [%i3+64], %l6 st %l6, [%i3+64] add %i3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET292 nop RET292: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P293: !_PREFETCH [25] (Int) (LE) (CBR) (Secondary ctx) wr %g0, 0x89, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetcha [%i2 + 96] %asi, 1 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET293 nop RET293: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P294: !_MEMBAR (FP) membar #StoreLoad P295: !_BLD [29] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 64] %asi, %f0 membar #Sync ! 1 addresses covered P296: !_MEMBAR (FP) (CBR) (Branch target of P654) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET296 nop RET296: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P297 nop TARGET654: ba RET654 nop P297: !_BST [33] (maybe <- 0x40000015) (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET297 nop RET297: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P298: !_MEMBAR (FP) P299: !_BSTC [30] (maybe <- 0x40000016) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 128 ] %asi P300: !_MEMBAR (FP) P301: !_BSTC [32] (maybe <- 0x40000017) (FP) (Secondary ctx) (Branch target of P401) wr %g0, 0xe1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 256 ] %asi ba P302 nop TARGET401: ba RET401 nop P302: !_MEMBAR (FP) (CBR) (Secondary ctx) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET302 nop RET302: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P303: !_ST [19] (maybe <- 0x40000018) (FP) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i3 + 0 ] %asi P304: !_MEMBAR (FP) membar #StoreLoad P305: !_BLD [9] (FP) wr %g0, 0xf0, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 fmovd %f40, %f2 P306: !_MEMBAR (FP) (Branch target of P552) ba P307 nop TARGET552: ba RET552 nop P307: !_BST [26] (maybe <- 0x40000019) (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 128 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET307 nop RET307: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P308: !_MEMBAR (FP) membar #StoreLoad P309: !_PREFETCH [28] (Int) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 0], 1 P310: !_REPLACEMENT [15] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %o5 ld [%i2+128], %l6 st %l6, [%i2+128] add %i2, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] P311: !_MEMBAR (FP) (Secondary ctx) (Branch target of P624) membar #StoreLoad ba P312 nop TARGET624: ba RET624 nop P312: !_BLD [15] (FP) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 P313: !_MEMBAR (FP) (Secondary ctx) P314: !_BSTC [22] (maybe <- 0x4000001b) (FP) (Secondary ctx) wr %g0, 0xe1, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P315: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P316: !_BLD [30] (FP) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f4 P317: !_MEMBAR (FP) (Secondary ctx) (Branch target of P261) ba P318 nop TARGET261: ba RET261 nop P318: !_BST [17] (maybe <- 0x4000001e) (FP) (Branch target of P529) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f40 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 64 ] %asi ba P319 nop TARGET529: ba RET529 nop P319: !_MEMBAR (FP) membar #StoreLoad P320: !_PREFETCH [21] (Int) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 0], 1 P321: !_MEMBAR (FP) membar #StoreLoad P322: !_BLD [29] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 P323: !_MEMBAR (FP) P324: !_IDC_FLIP [6] (Int) (Branch target of P593) IDC_FLIP(324, 27843, 1, 0x43000060, 0x60, %i0, 0x60, %l6, %l7, %o5, %l3) ba P325 nop TARGET593: ba RET593 nop P325: !_REPLACEMENT [24] (Int) (Nucleus ctx) (Branch target of P488) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l6 ld [%i3+64], %o5 st %o5, [%i3+64] add %i3, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] ba P326 nop TARGET488: ba RET488 nop P326: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P327: !_BLD [4] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f6 fmovd %f34, %f8 fmovd %f36, %f18 fmovs %f18, %f9 fmovd %f40, %f10 P328: !_MEMBAR (FP) (CBR) (Secondary ctx) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET328 nop RET328: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P329: !_REPLACEMENT [26] (Int) sethi %hi(0x2000), %l6 ld [%i3+128], %o5 st %o5, [%i3+128] add %i3, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] P330: !_MEMBAR (FP) P331: !_BSTC [14] (maybe <- 0x4000001f) (FP) (Branch target of P702) wr %g0, 0xe0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 64 ] %asi ba P332 nop TARGET702: ba RET702 nop P332: !_MEMBAR (FP) membar #StoreLoad P333: !_BLD [13] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 fmovs %f19, %f12 fmovd %f40, %f18 fmovs %f18, %f13 P334: !_MEMBAR (FP) P335: !_LD [8] (Int) lduw [%i1 + 0], %l3 ! move %l3(lower) -> %o1(lower) or %l3, %o1, %o1 P336: !_MEMBAR (FP) (Branch target of P579) membar #StoreLoad ba P337 nop TARGET579: ba RET579 nop P337: !_BLD [13] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f14 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f40, %f0 P338: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET338 nop RET338: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P339: !_ST [21] (maybe <- 0x800001) (Int) (Branch target of P424) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stw %l4, [%i3 + 0 ] add %l4, 1, %l4 ba P340 nop TARGET424: ba RET424 nop P340: !_ST [17] (maybe <- 0x40000020) (FP) (Secondary ctx) (Branch target of P528) wr %g0, 0x81, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i2 + 96 ] %asi ba P341 nop TARGET528: ba RET528 nop P341: !_MEMBAR (FP) membar #StoreLoad P342: !_BLD [24] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 fmovd %f40, %f2 P343: !_MEMBAR (FP) P344: !_BST [7] (maybe <- 0x40000021) (FP) (CBR) (Secondary ctx) wr %g0, 0xf1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i0 + 128 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET344 nop RET344: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P345: !_MEMBAR (FP) (CBR) (Secondary ctx) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET345 nop RET345: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P346: !_BLD [28] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 P347: !_MEMBAR (FP) P348: !_ST [6] (maybe <- 0x40000022) (FP) (Secondary ctx) wr %g0, 0x81, %asi ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i0 + 96 ] %asi P349: !_MEMBAR (FP) P350: !_BSTC [9] (maybe <- 0x40000023) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i1 + 0 ] %asi P351: !_MEMBAR (FP) (Branch target of P475) membar #StoreLoad ba P352 nop TARGET475: ba RET475 nop P352: !_BLD [22] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f4 fmovd %f40, %f6 P353: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET353 nop RET353: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P354: !_BLD [17] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f40, %f18 fmovs %f18, %f7 P355: !_MEMBAR (FP) P356: !_BSTC [10] (maybe <- 0x40000025) (FP) (CBR) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i1 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET356 nop RET356: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P357: !_MEMBAR (FP) membar #StoreLoad P358: !_REPLACEMENT [19] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+0], %l7 st %l7, [%i2+0] add %i2, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] P359: !_MEMBAR (FP) (Secondary ctx) (Branch target of P428) ba P360 nop TARGET428: ba RET428 nop P360: !_BST [31] (maybe <- 0x40000026) (FP) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 192 ] %asi P361: !_MEMBAR (FP) (CBR) (Secondary ctx) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET361 nop RET361: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P362: !_BSTC [20] (maybe <- 0x40000027) (FP) (Secondary ctx) wr %g0, 0xe1, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 256 ] %asi P363: !_MEMBAR (FP) (CBR) (Secondary ctx) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET363 nop RET363: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P364: !_BLD [1] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f8 fmovd %f34, %f10 fmovd %f36, %f18 fmovs %f18, %f11 fmovd %f40, %f12 P365: !_MEMBAR (FP) P366: !_BST [5] (maybe <- 0x40000028) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 64 ] %asi P367: !_MEMBAR (FP) membar #StoreLoad P368: !_LD [16] (Int) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lduw [%i3 + 16], %o2 ! move %o2(lower) -> %o2(upper) sllx %o2, 32, %o2 P369: !_REPLACEMENT [11] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+0], %l7 st %l7, [%i2+0] add %i2, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] P370: !_REPLACEMENT [16] (Int) sethi %hi(0x2000), %o5 ld [%i2+16], %l6 st %l6, [%i2+16] add %i2, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] P371: !_LD [3] (Int) lduw [%i0 + 16], %o5 ! move %o5(lower) -> %o2(lower) or %o5, %o2, %o2 P372: !_MEMBAR (FP) (Secondary ctx) P373: !_BSTC [28] (maybe <- 0x4000002a) (FP) (Secondary ctx) wr %g0, 0xe1, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 0 ] %asi P374: !_MEMBAR (FP) (Secondary ctx) P375: !_BSTC [25] (maybe <- 0x4000002b) (FP) (CBR) wr %g0, 0xe0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET375 nop RET375: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P376: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET376 nop RET376: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P377: !_BST [0] (maybe <- 0x4000002d) (FP) (CBR) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET377 nop RET377: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P378: !_MEMBAR (FP) membar #StoreLoad P379: !_BLD [10] (FP) wr %g0, 0xf0, %asi ldda [%i1 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 P380: !_MEMBAR (FP) P381: !_REPLACEMENT [9] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+32], %l7 st %l7, [%i3+32] add %i3, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] P382: !_REPLACEMENT [32] (Int) sethi %hi(0x2000), %o5 ld [%i3+256], %l6 st %l6, [%i3+256] add %i3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] P383: !_MEMBAR (FP) (Branch target of P533) ba P384 nop TARGET533: ba RET533 nop P384: !_BSTC [31] (maybe <- 0x40000032) (FP) (CBR) wr %g0, 0xe0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 192 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET384 nop RET384: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P385: !_MEMBAR (FP) (CBR) (Branch target of P361) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET385 nop RET385: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P386 nop TARGET361: ba RET361 nop P386: !_BSTC [6] (maybe <- 0x40000033) (FP) (Branch target of P678) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 64 ] %asi ba P387 nop TARGET678: ba RET678 nop P387: !_MEMBAR (FP) (Branch target of P414) membar #StoreLoad ba P388 nop TARGET414: ba RET414 nop P388: !_LD [8] (Int) lduw [%i1 + 0], %o3 ! move %o3(lower) -> %o3(upper) sllx %o3, 32, %o3 P389: !_MEMBAR (FP) (Secondary ctx) P390: !_BSTC [6] (maybe <- 0x40000035) (FP) (Secondary ctx) wr %g0, 0xe1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 64 ] %asi P391: !_MEMBAR (FP) (Secondary ctx) (Branch target of P576) membar #StoreLoad ba P392 nop TARGET576: ba RET576 nop P392: !_LD [3] (FP) ld [%i0 + 16], %f14 ! 1 addresses covered P393: !_REPLACEMENT [32] (Int) (Secondary ctx) (Branch target of P638) wr %g0, 0x81, %asi sethi %hi(0x2000), %o5 ld [%i3+256], %l6 st %l6, [%i3+256] add %i3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] ba P394 nop TARGET638: ba RET638 nop P394: !_ST [25] (maybe <- 0x800002) (Int) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stw %l4, [%i3 + 96 ] add %l4, 1, %l4 P395: !_MEMBAR (FP) P396: !_BST [25] (maybe <- 0x40000037) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 64 ] %asi P397: !_MEMBAR (FP) membar #StoreLoad P398: !_BLD [29] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- P399: !_MEMBAR (FP) (Branch target of P307) ba P400 nop TARGET307: ba RET307 nop P400: !_REPLACEMENT [19] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+0], %l7 st %l7, [%i2+0] add %i2, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] P401: !_MEMBAR (FP) (CBR) (Branch target of P419) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET401 nop RET401: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 ba P402 nop TARGET419: ba RET419 nop P402: !_BLD [19] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f0 membar #Sync ! 1 addresses covered ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET402 nop RET402: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P403: !_MEMBAR (FP) P404: !_BSTC [19] (maybe <- 0x40000039) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 0 ] %asi P405: !_MEMBAR (FP) (Branch target of P292) membar #StoreLoad ba P406 nop TARGET292: ba RET292 nop P406: !_LD [8] (Int) lduw [%i1 + 0], %l6 ! move %l6(lower) -> %o3(lower) or %l6, %o3, %o3 P407: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET407 nop RET407: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P408: !_BLD [22] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 fmovs %f19, %f2 fmovd %f40, %f18 fmovs %f18, %f3 P409: !_MEMBAR (FP) P410: !_BSTC [27] (maybe <- 0x4000003a) (FP) (CBR) (Branch target of P257) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 128 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET410 nop RET410: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P411 nop TARGET257: ba RET257 nop P411: !_MEMBAR (FP) membar #StoreLoad P412: !_REPLACEMENT [19] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %o5 ld [%i3+0], %l6 st %l6, [%i3+0] add %i3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] P413: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET413 nop RET413: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P414: !_BLD [28] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f4 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET414 nop RET414: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P415: !_MEMBAR (FP) (Branch target of P644) ba P416 nop TARGET644: ba RET644 nop P416: !_BSTC [11] (maybe <- 0x4000003c) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P417: !_MEMBAR (FP) P418: !_BSTC [32] (maybe <- 0x4000003f) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 256 ] %asi P419: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET419 nop RET419: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P420: !_BSTC [2] (maybe <- 0x40000040) (FP) (CBR) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET420 nop RET420: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P421: !_MEMBAR (FP) membar #StoreLoad P422: !_BLD [31] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 192] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 P423: !_MEMBAR (FP) P424: !_ST [27] (maybe <- 0x40000045) (FP) (CBR) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 160 ] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET424 nop RET424: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P425: !_MEMBAR (FP) P426: !_BSTC [9] (maybe <- 0x40000046) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i1 + 0 ] %asi P427: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET427 nop RET427: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P428: !_PREFETCH [3] (Int) (CBR) (Nucleus ctx) wr %g0, 0x4, %asi prefetcha [%i0 + 16] %asi, 1 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET428 nop RET428: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P429: !_REPLACEMENT [16] (Int) (CBR) (Secondary ctx) (Branch target of P618) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+16], %l7 st %l7, [%i3+16] add %i3, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET429 nop RET429: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 ba P430 nop TARGET618: ba RET618 nop P430: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET430 nop RET430: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P431: !_BST [3] (maybe <- 0x40000048) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P432: !_MEMBAR (FP) (Branch target of P454) membar #StoreLoad ba P433 nop TARGET454: ba RET454 nop P433: !_ST [23] (maybe <- 0x800003) (Int) (Secondary ctx) (Branch target of P283) wr %g0, 0x81, %asi stwa %l4, [%i2 + 32] %asi add %l4, 1, %l4 ba P434 nop TARGET283: ba RET283 nop P434: !_MEMBAR (FP) (Branch target of P590) ba P435 nop TARGET590: ba RET590 nop P435: !_BST [26] (maybe <- 0x4000004d) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 128 ] %asi P436: !_MEMBAR (FP) membar #StoreLoad P437: !_LD [11] (FP) (Secondary ctx) (Branch target of P485) wr %g0, 0x81, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lda [%i2 + 0] %asi, %f6 ! 1 addresses covered ba P438 nop TARGET485: ba RET485 nop P438: !_LD [5] (FP) ld [%i0 + 64], %f7 ! 1 addresses covered P439: !_LD [11] (Int) lduw [%i2 + 0], %o4 ! move %o4(lower) -> %o4(upper) sllx %o4, 32, %o4 P440: !_LD [31] (FP) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ld [%i3 + 192], %f8 ! 1 addresses covered P441: !_LD [12] (FP) (Branch target of P384) ld [%i2 + 4], %f9 ! 1 addresses covered ba P442 nop TARGET384: ba RET384 nop P442: !_REPLACEMENT [23] (Int) (Secondary ctx) (Branch target of P238) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+32], %l7 st %l7, [%i2+32] add %i2, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] ba P443 nop TARGET238: ba RET238 nop P443: !_MEMBAR (FP) P444: !_BSTC [20] (maybe <- 0x4000004f) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 256 ] %asi P445: !_MEMBAR (FP) membar #StoreLoad P446: !_BLD [4] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f10 fmovd %f34, %f12 fmovd %f36, %f18 fmovs %f18, %f13 fmovd %f40, %f14 P447: !_MEMBAR (FP) P448: !_BSTC [6] (maybe <- 0x40000050) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 64 ] %asi P449: !_MEMBAR (FP) membar #StoreLoad P450: !_REPLACEMENT [20] (Int) (Secondary ctx) (Branch target of P328) wr %g0, 0x81, %asi sethi %hi(0x2000), %l6 ld [%i2+256], %o5 st %o5, [%i2+256] add %i2, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] ba P451 nop TARGET328: ba RET328 nop P451: !_MEMBAR (FP) membar #StoreLoad P452: !_BLD [6] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f40, %f0 P453: !_MEMBAR (FP) P454: !_PREFETCH [23] (Int) (CBR) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 32], 1 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET454 nop RET454: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P455: !_PREFETCH [5] (Int) prefetch [%i0 + 64], 1 P456: !_PREFETCH [27] (Int) (Secondary ctx) wr %g0, 0x81, %asi prefetcha [%i2 + 160] %asi, 1 P457: !_MEMBAR (FP) P458: !_BSTC [29] (maybe <- 0x40000052) (FP) (CBR) wr %g0, 0xe0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET458 nop RET458: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P459: !_MEMBAR (FP) P460: !_BST [11] (maybe <- 0x40000053) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P461: !_MEMBAR (FP) P462: !_BSTC [15] (maybe <- 0x40000056) (FP) (Branch target of P563) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 128 ] %asi ba P463 nop TARGET563: ba RET563 nop P463: !_MEMBAR (FP) membar #StoreLoad P464: !_REPLACEMENT [8] (Int) (Branch target of P356) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %o5 ld [%i3+0], %l6 st %l6, [%i3+0] add %i3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] ba P465 nop TARGET356: ba RET356 nop P465: !_PREFETCH [7] (Int) (Secondary ctx) wr %g0, 0x81, %asi prefetcha [%i0 + 128] %asi, 1 P466: !_MEMBAR (FP) membar #StoreLoad P467: !_BLD [14] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 P468: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET468 nop RET468: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P469: !_BST [14] (maybe <- 0x40000057) (FP) (CBR) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET469 nop RET469: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P470: !_MEMBAR (FP) membar #StoreLoad P471: !_REPLACEMENT [8] (Int) sethi %hi(0x2000), %o5 ld [%i3+0], %l6 st %l6, [%i3+0] add %i3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] P472: !_MEMBAR (FP) membar #StoreLoad P473: !_BLD [25] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f2 fmovd %f40, %f18 fmovs %f18, %f3 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET473 nop RET473: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P474: !_MEMBAR (FP) P475: !_BLD [6] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f4 fmovd %f40, %f18 fmovs %f18, %f5 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET475 nop RET475: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P476: !_MEMBAR (FP) P477: !_PREFETCH [12] (Int) (Branch target of P377) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 4], 1 ba P478 nop TARGET377: ba RET377 nop P478: !_REPLACEMENT [20] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+256], %l7 st %l7, [%i2+256] add %i2, %l3, %l6 ld [%l6+256], %l7 st %l7, [%l6+256] add %l6, %l3, %l6 ld [%l6+256], %l7 st %l7, [%l6+256] add %l6, %l3, %l6 ld [%l6+256], %l7 st %l7, [%l6+256] add %l6, %l3, %l6 ld [%l6+256], %l7 st %l7, [%l6+256] add %l6, %l3, %l6 ld [%l6+256], %l7 st %l7, [%l6+256] add %l6, %l3, %l6 ld [%l6+256], %l7 st %l7, [%l6+256] add %l6, %l3, %l6 ld [%l6+256], %l7 st %l7, [%l6+256] P479: !_REPLACEMENT [5] (Int) (Branch target of P246) sethi %hi(0x2000), %o5 ld [%i2+64], %l6 st %l6, [%i2+64] add %i2, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] ba P480 nop TARGET246: ba RET246 nop P480: !_ST [28] (maybe <- 0x800004) (Int) (CBR) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stwa %l4, [%i3 + 0] %asi add %l4, 1, %l4 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET480 nop RET480: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P481: !_MEMBAR (FP) (Branch target of P247) membar #StoreLoad ba P482 nop TARGET247: ba RET247 nop P482: !_BLD [30] (FP) (Branch target of P429) wr %g0, 0xf0, %asi ldda [%i3 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f6 ba P483 nop TARGET429: ba RET429 nop P483: !_MEMBAR (FP) P484: !_REPLACEMENT [13] (Int) (CBR) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(0x2000), %l7 ld [%i2+32], %l3 st %l3, [%i2+32] add %i2, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET484 nop RET484: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P485: !_MEMBAR (FP) (CBR) (Branch target of P277) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET485 nop RET485: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P486 nop TARGET277: ba RET277 nop P486: !_BST [12] (maybe <- 0x40000058) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P487: !_MEMBAR (FP) membar #StoreLoad P488: !_ST [24] (maybe <- 0x4000005b) (FP) (CBR) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 64 ] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET488 nop RET488: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P489: !_MEMBAR (FP) P490: !_BSTC [20] (maybe <- 0x4000005c) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 256 ] %asi P491: !_MEMBAR (FP) membar #StoreLoad P492: !_BLD [16] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f36, %f18 fmovs %f18, %f7 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET492 nop RET492: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P493: !_MEMBAR (FP) (Branch target of P385) ba P494 nop TARGET385: ba RET385 nop P494: !_BLD [4] (FP) (Branch target of P537) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f8 fmovd %f34, %f10 fmovd %f36, %f18 fmovs %f18, %f11 fmovd %f40, %f12 ba P495 nop TARGET537: ba RET537 nop P495: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET495 nop RET495: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P496: !_PREFETCH [5] (Int) (Branch target of P344) prefetch [%i0 + 64], 1 ba P497 nop TARGET344: ba RET344 nop P497: !_MEMBAR (FP) membar #StoreLoad P498: !_BLD [28] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 P499: !_MEMBAR (FP) (CBR) (Branch target of P521) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET499 nop RET499: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 ba P500 nop TARGET521: ba RET521 nop P500: !_BLD [3] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f14 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f34, %f0 fmovd %f36, %f18 fmovs %f18, %f1 fmovd %f40, %f2 P501: !_MEMBAR (FP) (Branch target of P345) ba P502 nop TARGET345: ba RET345 nop P502: !_REPLACEMENT [11] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+0], %l7 st %l7, [%i3+0] add %i3, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] P503: !_LD [13] (Int) (CBR) (Branch target of P509) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduw [%i2 + 32], %l3 ! move %l3(lower) -> %o4(lower) or %l3, %o4, %o4 !---- flushing int results buffer---- mov %o0, %l5 mov %o1, %l5 mov %o2, %l5 mov %o3, %l5 mov %o4, %l5 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET503 nop RET503: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P504 nop TARGET509: ba RET509 nop P504: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET504 nop RET504: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P505: !_BST [31] (maybe <- 0x4000005d) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 192 ] %asi P506: !_MEMBAR (FP) membar #StoreLoad P507: !_BLD [3] (FP) (Secondary ctx) (Branch target of P609) wr %g0, 0xf1, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 fmovs %f19, %f4 fmovd %f34, %f18 fmovs %f18, %f5 fmovd %f36, %f6 fmovd %f40, %f18 fmovs %f18, %f7 ba P508 nop TARGET609: ba RET609 nop P508: !_MEMBAR (FP) (Secondary ctx) P509: !_BLD [19] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f8 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET509 nop RET509: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P510: !_MEMBAR (FP) P511: !_BLD [20] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f9 P512: !_MEMBAR (FP) P513: !_ST [26] (maybe <- 0x800005) (Int) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stw %l4, [%i3 + 128 ] add %l4, 1, %l4 P514: !_MEMBAR (FP) membar #StoreLoad P515: !_BLD [12] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f10 fmovd %f40, %f12 P516: !_MEMBAR (FP) P517: !_ST [3] (maybe <- 0x4000005e) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i0 + 16 ] P518: !_ST [27] (maybe <- 0x800006) (Int) stw %l4, [%i3 + 160 ] add %l4, 1, %l4 P519: !_MEMBAR (FP) membar #StoreLoad P520: !_BLD [9] (FP) wr %g0, 0xf0, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 fmovd %f40, %f14 P521: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET521 nop RET521: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P522: !_BST [29] (maybe <- 0x4000005f) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 64 ] %asi P523: !_MEMBAR (FP) (Branch target of P468) membar #StoreLoad ba P524 nop TARGET468: ba RET468 nop P524: !_LD [33] (Int) (Branch target of P527) sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduw [%i2 + 0], %o0 ! move %o0(lower) -> %o0(upper) sllx %o0, 32, %o0 ba P525 nop TARGET527: ba RET527 nop P525: !_PREFETCH [23] (Int) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 32], 1 P526: !_ST [30] (maybe <- 0x40000060) (FP) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 128 ] P527: !_ST [33] (maybe <- 0x40000061) (FP) (CBR) sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 0 ] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET527 nop RET527: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P528: !_ST [16] (maybe <- 0x800007) (Int) (CBR) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 stwa %l4, [%i2 + 16] %asi add %l4, 1, %l4 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET528 nop RET528: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P529: !_LD [9] (FP) (CBR) ld [%i1 + 32], %f15 ! 1 addresses covered !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET529 nop RET529: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P530: !_MEMBAR (FP) (Branch target of P363) ba P531 nop TARGET363: ba RET363 nop P531: !_BST [7] (maybe <- 0x40000062) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i0 + 128 ] %asi P532: !_MEMBAR (FP) (Branch target of P297) membar #StoreLoad ba P533 nop TARGET297: ba RET297 nop P533: !_BLD [30] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f0 membar #Sync ! 1 addresses covered ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET533 nop RET533: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P534: !_MEMBAR (FP) P535: !_LD [20] (Int) (Nucleus ctx) (Branch target of P296) wr %g0, 0x4, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduwa [%i2 + 256] %asi, %o5 ! move %o5(lower) -> %o0(lower) or %o5, %o0, %o0 ba P536 nop TARGET296: ba RET296 nop P536: !_IDC_FLIP [13] (Int) (Branch target of P561) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 IDC_FLIP(536, 16690, 1, 0x44000020, 0x20, %i3, 0x20, %l6, %l7, %o5, %l3) ba P537 nop TARGET561: ba RET561 nop P537: !_REPLACEMENT [19] (Int) (CBR) (Branch target of P473) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l6 ld [%i2+0], %o5 st %o5, [%i2+0] add %i2, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET537 nop RET537: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P538 nop TARGET473: ba RET473 nop P538: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P539: !_BLD [10] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i1 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 P540: !_MEMBAR (FP) (Secondary ctx) P541: !_IDC_FLIP [21] (Int) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 IDC_FLIP(541, 10991, 1, 0x45800000, 0x0, %i3, 0x0, %l6, %l7, %o5, %l3) P542: !_REPLACEMENT [2] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(0x2000), %l6 ld [%i2+8], %o5 st %o5, [%i2+8] add %i2, %l6, %l7 ld [%l7+8], %o5 st %o5, [%l7+8] add %l7, %l6, %l7 ld [%l7+8], %o5 st %o5, [%l7+8] add %l7, %l6, %l7 ld [%l7+8], %o5 st %o5, [%l7+8] add %l7, %l6, %l7 ld [%l7+8], %o5 st %o5, [%l7+8] add %l7, %l6, %l7 ld [%l7+8], %o5 st %o5, [%l7+8] add %l7, %l6, %l7 ld [%l7+8], %o5 st %o5, [%l7+8] add %l7, %l6, %l7 ld [%l7+8], %o5 st %o5, [%l7+8] P543: !_PREFETCH [6] (Int) (LE) wr %g0, 0x88, %asi prefetcha [%i0 + 96] %asi, 1 P544: !_PREFETCH [4] (Int) prefetch [%i0 + 32], 1 P545: !_MEMBAR (FP) membar #StoreLoad P546: !_BLD [11] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f2 fmovd %f40, %f4 P547: !_MEMBAR (FP) P548: !_LD [21] (Int) (Secondary ctx) wr %g0, 0x81, %asi lduwa [%i3 + 0] %asi, %o1 ! move %o1(lower) -> %o1(upper) sllx %o1, 32, %o1 P549: !_PREFETCH [16] (Int) (CBR) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 16], 1 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET549 nop RET549: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P550: !_LD [5] (FP) (CBR) (Branch target of P302) ld [%i0 + 64], %f5 ! 1 addresses covered ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET550 nop RET550: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 ba P551 nop TARGET302: ba RET302 nop P551: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P552: !_BLD [2] (FP) (CBR) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f6 fmovd %f34, %f8 fmovd %f36, %f18 fmovs %f18, %f9 fmovd %f40, %f10 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET552 nop RET552: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P553: !_MEMBAR (FP) (Secondary ctx) (Branch target of P402) ba P554 nop TARGET402: ba RET402 nop P554: !_BLD [25] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 fmovd %f40, %f12 P555: !_MEMBAR (FP) P556: !_IDC_FLIP [22] (Int) IDC_FLIP(556, 26988, 1, 0x45800004, 0x4, %i2, 0x4, %l6, %l7, %o5, %l3) P557: !_MEMBAR (FP) membar #StoreLoad P558: !_BLD [24] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 fmovd %f40, %f14 P559: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET559 nop RET559: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P560: !_BSTC [18] (maybe <- 0x40000063) (FP) (CBR) (Branch target of P427) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 128 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET560 nop RET560: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P561 nop TARGET427: ba RET427 nop P561: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET561 nop RET561: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P562: !_REPLACEMENT [17] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %o5 ld [%i3+96], %l6 st %l6, [%i3+96] add %i3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] P563: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET563 nop RET563: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P564: !_BLD [29] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- P565: !_MEMBAR (FP) P566: !_BST [17] (maybe <- 0x40000064) (FP) (CBR) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f40 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET566 nop RET566: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P567: !_MEMBAR (FP) (Secondary ctx) (Branch target of P243) membar #StoreLoad ba P568 nop TARGET243: ba RET243 nop P568: !_PREFETCH [19] (Int) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 0], 1 P569: !_REPLACEMENT [22] (Int) (Branch target of P430) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %o5 ld [%i3+4], %l6 st %l6, [%i3+4] add %i3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] ba P570 nop TARGET430: ba RET430 nop P570: !_MEMBAR (FP) membar #StoreLoad P571: !_BLD [31] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 192] %asi, %f0 membar #Sync ! 1 addresses covered P572: !_MEMBAR (FP) P573: !_PREFETCH [31] (Int) (Branch target of P375) prefetch [%i2 + 192], 1 ba P574 nop TARGET375: ba RET375 nop P574: !_LD [23] (Int) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lduw [%i3 + 32], %o5 ! move %o5(lower) -> %o1(lower) or %o5, %o1, %o1 P575: !_MEMBAR (FP) membar #StoreLoad P576: !_BLD [24] (FP) (CBR) (Branch target of P623) wr %g0, 0xf0, %asi ldda [%i3 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 fmovd %f40, %f2 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET576 nop RET576: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P577 nop TARGET623: ba RET623 nop P577: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET577 nop RET577: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P578: !_PREFETCH [26] (Int) prefetch [%i3 + 128], 1 P579: !_LD [2] (FP) (CBR) (Branch target of P549) ld [%i0 + 8], %f3 ! 1 addresses covered ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET579 nop RET579: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P580 nop TARGET549: ba RET549 nop P580: !_MEMBAR (FP) P581: !_BSTC [32] (maybe <- 0x40000065) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 256 ] %asi P582: !_MEMBAR (FP) membar #StoreLoad P583: !_LD [0] (Int) (LE) wr %g0, 0x88, %asi lduwa [%i0 + 0] %asi, %o2 ! move %o2(lower) -> %o2(upper) sllx %o2, 32, %o2 P584: !_MEMBAR (FP) P585: !_BSTC [27] (maybe <- 0x40000066) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 128 ] %asi P586: !_MEMBAR (FP) P587: !_BST [14] (maybe <- 0x40000068) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 64 ] %asi P588: !_MEMBAR (FP) membar #StoreLoad P589: !_BLD [10] (FP) (Secondary ctx) (Branch target of P484) wr %g0, 0xf1, %asi ldda [%i1 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f4 ba P590 nop TARGET484: ba RET484 nop P590: !_MEMBAR (FP) (CBR) (Secondary ctx) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET590 nop RET590: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P591: !_PREFETCH [0] (Int) (Branch target of P278) prefetch [%i0 + 0], 1 ba P592 nop TARGET278: ba RET278 nop P592: !_REPLACEMENT [18] (Int) (Branch target of P611) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %o5 ld [%i3+128], %l6 st %l6, [%i3+128] add %i3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] ba P593 nop TARGET611: ba RET611 nop P593: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET593 nop RET593: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P594: !_BLD [9] (FP) wr %g0, 0xf0, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 fmovd %f40, %f6 P595: !_MEMBAR (FP) P596: !_REPLACEMENT [18] (Int) sethi %hi(0x2000), %o5 ld [%i3+128], %l6 st %l6, [%i3+128] add %i3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] P597: !_MEMBAR (FP) P598: !_BST [1] (maybe <- 0x40000069) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P599: !_MEMBAR (FP) P600: !_BST [5] (maybe <- 0x4000006e) (FP) (Branch target of P616) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 64 ] %asi ba P601 nop TARGET616: ba RET616 nop P601: !_MEMBAR (FP) membar #StoreLoad P602: !_BLD [15] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 P603: !_MEMBAR (FP) P604: !_REPLACEMENT [33] (Int) sethi %hi(0x2000), %l3 ld [%i3+0], %l7 st %l7, [%i3+0] add %i3, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] P605: !_MEMBAR (FP) (Branch target of P420) membar #StoreLoad ba P606 nop TARGET420: ba RET420 nop P606: !_BLD [2] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f8 fmovd %f34, %f10 fmovd %f36, %f18 fmovs %f18, %f11 fmovd %f40, %f12 P607: !_MEMBAR (FP) P608: !_REPLACEMENT [21] (Int) sethi %hi(0x2000), %o5 ld [%i3+0], %l6 st %l6, [%i3+0] add %i3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] P609: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET609 nop RET609: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P610: !_BLD [15] (FP) (Branch target of P550) wr %g0, 0xf0, %asi ldda [%i2 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 ba P611 nop TARGET550: ba RET550 nop P611: !_MEMBAR (FP) (CBR) (Branch target of P566) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET611 nop RET611: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 ba P612 nop TARGET566: ba RET566 nop P612: !_REPLACEMENT [29] (Int) sethi %hi(0x2000), %l3 ld [%i3+64], %l7 st %l7, [%i3+64] add %i3, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] P613: !_LD [28] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduwa [%i2 + 0] %asi, %l3 ! move %l3(lower) -> %o2(lower) or %l3, %o2, %o2 P614: !_MEMBAR (FP) membar #StoreLoad P615: !_BLD [24] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f14 fmovd %f40, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- P616: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET616 nop RET616: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P617: !_ST [23] (maybe <- 0x40000070) (FP) (Branch target of P504) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 32 ] ba P618 nop TARGET504: ba RET504 nop P618: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET618 nop RET618: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P619: !_BST [19] (maybe <- 0x40000071) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 0 ] %asi P620: !_MEMBAR (FP) (Branch target of P495) membar #StoreLoad ba P621 nop TARGET495: ba RET495 nop P621: !_BLD [6] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f0 membar #Sync ! 2 addresses covered fmovs %f8, %f1 P622: !_MEMBAR (FP) (Branch target of P559) ba P623 nop TARGET559: ba RET559 nop P623: !_BST [25] (maybe <- 0x40000072) (FP) (CBR) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET623 nop RET623: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P624: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET624 nop RET624: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P625: !_PREFETCH [23] (Int) (Secondary ctx) wr %g0, 0x81, %asi prefetcha [%i3 + 32] %asi, 1 P626: !_MEMBAR (FP) (Branch target of P458) membar #StoreLoad ba P627 nop TARGET458: ba RET458 nop P627: !_BLD [4] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f2 fmovd %f34, %f4 fmovd %f36, %f18 fmovs %f18, %f5 fmovd %f40, %f6 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET627 nop RET627: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P628: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET628 nop RET628: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P629: !_BST [24] (maybe <- 0x40000074) (FP) (Branch target of P338) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 64 ] %asi ba P630 nop TARGET338: ba RET338 nop P630: !_MEMBAR (FP) membar #StoreLoad P631: !_BLD [23] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 fmovs %f19, %f8 fmovd %f40, %f18 fmovs %f18, %f9 P632: !_MEMBAR (FP) P633: !_BLD [20] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f10 P634: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET634 nop RET634: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P635: !_REPLACEMENT [27] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+160], %l7 st %l7, [%i3+160] add %i3, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] P636: !_REPLACEMENT [33] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(0x2000), %o5 ld [%i3+0], %l6 st %l6, [%i3+0] add %i3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] P637: !_LD [7] (Int) lduw [%i0 + 128], %o3 ! move %o3(lower) -> %o3(upper) sllx %o3, 32, %o3 P638: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET638 nop RET638: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P639: !_BLD [26] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 fmovd %f40, %f12 P640: !_MEMBAR (FP) P641: !_ST [28] (maybe <- 0x800008) (Int) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stw %l4, [%i3 + 0 ] add %l4, 1, %l4 P642: !_MEMBAR (FP) membar #StoreLoad P643: !_BLD [0] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 fmovs %f19, %f14 fmovd %f34, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f36, %f0 fmovd %f40, %f18 fmovs %f18, %f1 P644: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET644 nop RET644: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P645: !_BST [3] (maybe <- 0x40000076) (FP) (CBR) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET645 nop RET645: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P646: !_MEMBAR (FP) membar #StoreLoad P647: !_REPLACEMENT [3] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l6 ld [%i2+16], %o5 st %o5, [%i2+16] add %i2, %l6, %l7 ld [%l7+16], %o5 st %o5, [%l7+16] add %l7, %l6, %l7 ld [%l7+16], %o5 st %o5, [%l7+16] add %l7, %l6, %l7 ld [%l7+16], %o5 st %o5, [%l7+16] add %l7, %l6, %l7 ld [%l7+16], %o5 st %o5, [%l7+16] add %l7, %l6, %l7 ld [%l7+16], %o5 st %o5, [%l7+16] add %l7, %l6, %l7 ld [%l7+16], %o5 st %o5, [%l7+16] add %l7, %l6, %l7 ld [%l7+16], %o5 st %o5, [%l7+16] P648: !_LD [8] (FP) (Secondary ctx) wr %g0, 0x81, %asi lda [%i1 + 0] %asi, %f2 ! 1 addresses covered P649: !_ST [8] (maybe <- 0x800009) (Int) stw %l4, [%i1 + 0 ] add %l4, 1, %l4 P650: !_MEMBAR (FP) membar #StoreLoad P651: !_BLD [18] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 P652: !_MEMBAR (FP) P653: !_ST [13] (maybe <- 0x4000007b) (FP) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 32 ] P654: !_REPLACEMENT [17] (Int) (CBR) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+96], %l3 st %l3, [%i3+96] add %i3, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET654 nop RET654: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P655: !_ST [19] (maybe <- 0x80000a) (Int) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 stw %l4, [%i2 + 0 ] add %l4, 1, %l4 P656: !_MEMBAR (FP) membar #StoreLoad P657: !_BLD [19] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f4 P658: !_MEMBAR (FP) P659: !_BLD [5] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 fmovd %f40, %f6 P660: !_MEMBAR (FP) P661: !_BST [6] (maybe <- 0x4000007c) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 64 ] %asi P662: !_MEMBAR (FP) membar #StoreLoad P663: !_BLD [30] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 P664: !_MEMBAR (FP) (Branch target of P499) ba P665 nop TARGET499: ba RET499 nop P665: !_REPLACEMENT [24] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+64], %l7 st %l7, [%i2+64] add %i2, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] P666: !_MEMBAR (FP) P667: !_BSTC [16] (maybe <- 0x4000007e) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f36 membar #Sync stda %f32, [%i3 + 0 ] %asi P668: !_MEMBAR (FP) membar #StoreLoad P669: !_LD [7] (Int) lduw [%i0 + 128], %o5 ! move %o5(lower) -> %o3(lower) or %o5, %o3, %o3 P670: !_LD [19] (FP) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ld [%i2 + 0], %f8 ! 1 addresses covered P671: !_MEMBAR (FP) (Branch target of P267) membar #StoreLoad ba P672 nop TARGET267: ba RET267 nop P672: !_BLD [25] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f9 fmovd %f40, %f10 P673: !_MEMBAR (FP) P674: !_IDC_FLIP [2] (Int) IDC_FLIP(674, 8916, 1, 0x43000008, 0x8, %i0, 0x8, %l6, %l7, %o5, %l3) P675: !_MEMBAR (FP) membar #StoreLoad P676: !_BLD [13] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 fmovs %f19, %f12 fmovd %f40, %f18 fmovs %f18, %f13 P677: !_MEMBAR (FP) (Branch target of P376) ba P678 nop TARGET376: ba RET376 nop P678: !_BST [15] (maybe <- 0x4000007f) (FP) (CBR) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 128 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET678 nop RET678: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P679: !_MEMBAR (FP) membar #StoreLoad P680: !_BLD [6] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f14 fmovd %f40, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- P681: !_MEMBAR (FP) (Secondary ctx) P682: !_BLD [21] (FP) (Branch target of P353) wr %g0, 0xf0, %asi ldda [%i3 + 0] %asi, %f0 membar #Sync ! 3 addresses covered fmovd %f8, %f2 ba P683 nop TARGET353: ba RET353 nop P683: !_MEMBAR (FP) (Branch target of P628) ba P684 nop TARGET628: ba RET628 nop P684: !_REPLACEMENT [23] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l6 ld [%i3+32], %o5 st %o5, [%i3+32] add %i3, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] P685: !_MEMBAR (FP) (Secondary ctx) P686: !_BST [5] (maybe <- 0x40000080) (FP) (Secondary ctx) (Branch target of P492) wr %g0, 0xf1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 64 ] %asi ba P687 nop TARGET492: ba RET492 nop P687: !_MEMBAR (FP) (Secondary ctx) P688: !_BSTC [11] (maybe <- 0x40000082) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P689: !_MEMBAR (FP) membar #StoreLoad P690: !_REPLACEMENT [12] (Int) (Nucleus ctx) (Branch target of P413) wr %g0, 0x4, %asi sethi %hi(0x2000), %l7 ld [%i3+4], %l3 st %l3, [%i3+4] add %i3, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] ba P691 nop TARGET413: ba RET413 nop P691: !_REPLACEMENT [8] (Int) sethi %hi(0x2000), %l6 ld [%i3+0], %o5 st %o5, [%i3+0] add %i3, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] P692: !_MEMBAR (FP) P693: !_BSTC [21] (maybe <- 0x40000085) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P694: !_MEMBAR (FP) membar #StoreLoad P695: !_LD [25] (FP) ld [%i2 + 96], %f3 ! 1 addresses covered P696: !_MEMBAR (FP) membar #StoreLoad P697: !_BLD [15] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f4 P698: !_MEMBAR (FP) P699: !_ST [30] (maybe <- 0x80000b) (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 stwa %l4, [%i2 + 128] %asi add %l4, 1, %l4 P700: !_REPLACEMENT [11] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+0], %l3 st %l3, [%i3+0] add %i3, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] P701: !_REPLACEMENT [20] (Int) sethi %hi(0x2000), %l6 ld [%i3+256], %o5 st %o5, [%i3+256] add %i3, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] P702: !_REPLACEMENT [9] (Int) (CBR) sethi %hi(0x2000), %l3 ld [%i3+32], %l7 st %l7, [%i3+32] add %i3, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET702 nop RET702: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P703: !_MEMBAR (FP) P704: !_BST [11] (maybe <- 0x40000088) (FP) (Branch target of P253) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi ba P705 nop TARGET253: ba RET253 nop P705: !_MEMBAR (FP) membar #StoreLoad P706: !_LD [10] (Int) lduw [%i1 + 64], %o4 ! move %o4(lower) -> %o4(upper) sllx %o4, 32, %o4 P707: !_REPLACEMENT [5] (Int) sethi %hi(0x2000), %l6 ld [%i3+64], %o5 st %o5, [%i3+64] add %i3, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] P708: !_LD [27] (FP) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lda [%i3 + 160] %asi, %f5 ! 1 addresses covered P709: !_MEMBAR (FP) (Secondary ctx) P710: !_BST [12] (maybe <- 0x4000008b) (FP) (Secondary ctx) wr %g0, 0xf1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P711: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P712: !_LD [17] (Int) (Loop exit) (Branch target of P503) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduw [%i2 + 96], %l3 ! move %l3(lower) -> %o4(lower) or %l3, %o4, %o4 !---- flushing int results buffer---- mov %o0, %l5 mov %o1, %l5 mov %o2, %l5 mov %o3, %l5 mov %o4, %l5 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 !-- loop_exit_1_0: sub %l2, 1, %l2 cmp %l2, 0 bg loop_entry_1_0 nop ba P713 nop TARGET503: ba RET503 nop P713: !_MEMBAR (Int) membar #StoreLoad END_NODES1: ! Test instruction sequence for CPU 1 ends sethi %hi(0xdead0e0f), %l7 or %l7, %lo(0xdead0e0f), %l7 ! move %l7(lower) -> %o0(upper) sllx %l7, 32, %o0 sethi %hi(0xdead0e0f), %l7 or %l7, %lo(0xdead0e0f), %l7 stw %l7, [%i5] ld [%i5], %f0 !---- flushing int results buffer---- mov %o0, %l5 !---- flushing fp results buffer to %f30 ---- fmovs %f0, %f30 !-- restore retl nop !----------------- ! register usage: ! %i0 %i1 : base registers for first 2 regions ! %i2 %i3 : cache registers for 8 regions ! %i4 fixed pointer to per-cpu results area ! %l1 moving pointer to per-cpu FP results area ! %o7 moving pointer to per-cpu integer results area ! %i5 pointer to per-cpu private area ! %l0 holds lfsr, used as source of random bits ! %l2 loop count register ! %f16 running counter for unique fp store values ! %f17 holds increment value for fp counter ! %l4 running counter for unique integer store values (increment value is always 1) ! %l5 move-to register for load values (simulation only) ! %f30 move-to register for FP values (simulation only) ! %i4 holds the instructions count which is used for interrupt ordering ! %i4 holds the thread_id (OBP only) ! %l5 holds the moving pointer for interrupt bonus data (OBP only). Conflicts with RTL/simulation usage ! %l3 %l6 %l7 %o5 : 4 temporary registers ! %o0 %o1 %o2 %o3 %o4 : 5 integer results buffer registers ! %f0-f15 FP results buffer registers ! %f32-f47 FP block load/store registers func2: ! instruction sequence begins save %sp, -192, %sp ! Force %i0-%i3 to be 64-byte aligned add %i0, 63, %i0 andn %i0, 63, %i0 add %i1, 63, %i1 andn %i1, 63, %i1 add %i2, 63, %i2 andn %i2, 63, %i2 add %i3, 63, %i3 andn %i3, 63, %i3 add %i4, 63, %i4 andn %i4, 63, %i4 add %i5, 63, %i5 andn %i5, 63, %i5 ! Initialize pointer to FP load results area mov %i4, %l1 ! Initialize pointer to integer load results area sethi %hi(0x80000), %o7 or %o7, %lo(0x80000), %o7 add %o7, %l1, %o7 ! Reinitialize i4 to 0. i4 will be used to keep the count of analyzable node info mov 0x0, %i4 ! Initialize %f0-%f62 to 0xdeadbee0deadbee1 sethi %hi(0xdeadbee0), %l6 or %l6, %lo(0xdeadbee0), %l6 stw %l6, [%i5] sethi %hi(0xdeadbee1), %l6 or %l6, %lo(0xdeadbee1), %l6 stw %l6, [%i5+4] ldd [%i5], %f0 fmovd %f0, %f2 fmovd %f0, %f4 fmovd %f0, %f6 fmovd %f0, %f8 fmovd %f0, %f10 fmovd %f0, %f12 fmovd %f0, %f14 fmovd %f0, %f16 fmovd %f0, %f18 fmovd %f0, %f20 fmovd %f0, %f22 fmovd %f0, %f24 fmovd %f0, %f26 fmovd %f0, %f28 fmovd %f0, %f30 fmovd %f0, %f32 fmovd %f0, %f34 fmovd %f0, %f36 fmovd %f0, %f38 fmovd %f0, %f40 fmovd %f0, %f42 fmovd %f0, %f44 fmovd %f0, %f46 fmovd %f0, %f48 fmovd %f0, %f50 fmovd %f0, %f52 fmovd %f0, %f54 fmovd %f0, %f56 fmovd %f0, %f58 fmovd %f0, %f60 fmovd %f0, %f62 ! Signature for extract_loads script to start extracting load values for this stream sethi %hi(0x02deade1), %l6 or %l6, %lo(0x02deade1), %l6 stw %l6, [%i5] ld [%i5], %f16 ! Initialize running integer counter in register %l4 sethi %hi(0x1000001), %l4 or %l4, %lo(0x1000001), %l4 ! Initialize running FP counter in register %f16 sethi %hi(0x40800001), %l6 or %l6, %lo(0x40800001), %l6 stw %l6, [%i5] ld [%i5], %f16 ! Initialize FP counter increment value in register %f17 (constant) sethi %hi(0x35000000), %l6 or %l6, %lo(0x35000000), %l6 stw %l6, [%i5] ld [%i5], %f17 ! Initialize LFSR to 0x7e38^4 sethi %hi(0x7e38), %l0 or %l0, %lo(0x7e38), %l0 mulx %l0, %l0, %l0 mulx %l0, %l0, %l0 BEGIN_NODES2: ! Test instruction sequence for ISTREAM 2 begins P714: !_MEMBAR (FP) (Loop entry) (Branch target of P1037) sethi %hi(0x2), %l2 or %l2, %lo(0x2), %l2 loop_entry_2_0: ba P715 nop TARGET1037: ba RET1037 nop P715: !_BST [33] (maybe <- 0x40800001) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 0 ] %asi P716: !_MEMBAR (FP) membar #StoreLoad P717: !_REPLACEMENT [12] (Int) (CBR) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l6 ld [%i2+4], %o5 st %o5, [%i2+4] add %i2, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET717 nop RET717: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P718: !_REPLACEMENT [13] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(0x2000), %l6 ld [%i2+32], %o5 st %o5, [%i2+32] add %i2, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] P719: !_ST [6] (maybe <- 0x40800002) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i0 + 96 ] P720: !_REPLACEMENT [5] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(0x2000), %o5 ld [%i2+64], %l6 st %l6, [%i2+64] add %i2, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] P721: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET721 nop RET721: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P722: !_BSTC [5] (maybe <- 0x40800003) (FP) (CBR) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET722 nop RET722: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P723: !_MEMBAR (FP) membar #StoreLoad P724: !_BLD [0] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f0 membar #Sync ! 5 addresses covered fmovs %f4, %f3 fmovd %f8, %f4 P725: !_MEMBAR (FP) P726: !_BLD [25] (FP) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 fmovd %f40, %f6 P727: !_MEMBAR (FP) (Secondary ctx) P728: !_REPLACEMENT [9] (Int) sethi %hi(0x2000), %o5 ld [%i2+32], %l6 st %l6, [%i2+32] add %i2, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] P729: !_MEMBAR (FP) P730: !_BST [2] (maybe <- 0x40800005) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P731: !_MEMBAR (FP) membar #StoreLoad P732: !_ST [9] (maybe <- 0x4080000a) (FP) (Secondary ctx) (Branch target of P1009) wr %g0, 0x81, %asi ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i1 + 32 ] %asi ba P733 nop TARGET1009: ba RET1009 nop P733: !_LD [26] (Int) lduw [%i3 + 128], %o0 ! move %o0(lower) -> %o0(upper) sllx %o0, 32, %o0 P734: !_LD [21] (FP) (Secondary ctx) wr %g0, 0x81, %asi lda [%i3 + 0] %asi, %f7 ! 1 addresses covered P735: !_LD [11] (FP) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lda [%i2 + 0] %asi, %f8 ! 1 addresses covered P736: !_MEMBAR (FP) P737: !_BST [10] (maybe <- 0x4080000b) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i1 + 64 ] %asi P738: !_MEMBAR (FP) membar #StoreLoad P739: !_REPLACEMENT [7] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l6 ld [%i3+128], %o5 st %o5, [%i3+128] add %i3, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] P740: !_ST [29] (maybe <- 0x4080000c) (FP) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 64 ] P741: !_LD [22] (Int) (CBR) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lduw [%i3 + 4], %l3 ! move %l3(lower) -> %o0(lower) or %l3, %o0, %o0 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET741 nop RET741: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P742: !_REPLACEMENT [21] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l7 ld [%i2+0], %l3 st %l3, [%i2+0] add %i2, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] P743: !_MEMBAR (FP) P744: !_BSTC [30] (maybe <- 0x4080000d) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 128 ] %asi P745: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET745 nop RET745: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P746: !_PREFETCH [24] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetcha [%i2 + 64] %asi, 1 P747: !_REPLACEMENT [14] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l6 ld [%i3+64], %o5 st %o5, [%i3+64] add %i3, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] P748: !_PREFETCH [8] (Int) (CBR) (Nucleus ctx) (Branch target of P887) wr %g0, 0x4, %asi prefetcha [%i1 + 0] %asi, 1 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET748 nop RET748: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P749 nop TARGET887: ba RET887 nop P749: !_MEMBAR (FP) membar #StoreLoad P750: !_BLD [0] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f9 fmovs %f19, %f10 fmovd %f34, %f18 fmovs %f18, %f11 fmovd %f36, %f12 fmovd %f40, %f18 fmovs %f18, %f13 P751: !_MEMBAR (FP) P752: !_PREFETCH [1] (Int) prefetch [%i0 + 4], 1 P753: !_ST [30] (maybe <- 0x1000001) (Int) (CBR) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 stwa %l4, [%i2 + 128] %asi add %l4, 1, %l4 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET753 nop RET753: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P754: !_PREFETCH [20] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetcha [%i3 + 256] %asi, 1 P755: !_MEMBAR (FP) (Branch target of P924) membar #StoreLoad ba P756 nop TARGET924: ba RET924 nop P756: !_BLD [0] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f14 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f34, %f0 fmovd %f36, %f18 fmovs %f18, %f1 fmovd %f40, %f2 P757: !_MEMBAR (FP) P758: !_BLD [13] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 fmovs %f19, %f4 fmovd %f40, %f18 fmovs %f18, %f5 P759: !_MEMBAR (FP) (CBR) (Branch target of P748) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET759 nop RET759: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P760 nop TARGET748: ba RET748 nop P760: !_LD [24] (FP) (CBR) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ld [%i3 + 64], %f6 ! 1 addresses covered ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET760 nop RET760: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P761: !_LD [23] (Int) (Branch target of P918) lduw [%i3 + 32], %o1 ! move %o1(lower) -> %o1(upper) sllx %o1, 32, %o1 ba P762 nop TARGET918: ba RET918 nop P762: !_LD [16] (FP) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ld [%i2 + 16], %f7 ! 1 addresses covered P763: !_MEMBAR (FP) membar #StoreLoad P764: !_BLD [1] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f8 fmovd %f34, %f10 fmovd %f36, %f18 fmovs %f18, %f11 fmovd %f40, %f12 P765: !_MEMBAR (FP) P766: !_BST [17] (maybe <- 0x4080000e) (FP) (Secondary ctx) wr %g0, 0xf1, %asi ! preparing store val #0, next val will be in f40 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 64 ] %asi P767: !_MEMBAR (FP) (Secondary ctx) (Branch target of P916) membar #StoreLoad ba P768 nop TARGET916: ba RET916 nop P768: !_BLD [6] (FP) (Branch target of P1233) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 fmovd %f40, %f14 ba P769 nop TARGET1233: ba RET1233 nop P769: !_MEMBAR (FP) P770: !_PREFETCH [19] (Int) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 0], 1 P771: !_LD [7] (FP) ld [%i0 + 128], %f15 ! 1 addresses covered !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- P772: !_IDC_FLIP [12] (Int) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 IDC_FLIP(772, 25411, 2, 0x44000004, 0x4, %i2, 0x4, %l6, %l7, %o5, %l3) P773: !_MEMBAR (FP) P774: !_BSTC [1] (maybe <- 0x4080000f) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P775: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET775 nop RET775: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P776: !_BSTC [8] (maybe <- 0x40800014) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i1 + 0 ] %asi P777: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET777 nop RET777: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P778: !_IDC_FLIP [24] (Int) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 IDC_FLIP(778, 14957, 2, 0x45800040, 0x40, %i3, 0x40, %l6, %l7, %o5, %l3) P779: !_MEMBAR (FP) P780: !_BSTC [14] (maybe <- 0x40800016) (FP) (Branch target of P940) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 64 ] %asi ba P781 nop TARGET940: ba RET940 nop P781: !_MEMBAR (FP) (Branch target of P952) membar #StoreLoad ba P782 nop TARGET952: ba RET952 nop P782: !_LD [11] (Int) lduw [%i2 + 0], %l6 ! move %l6(lower) -> %o1(lower) or %l6, %o1, %o1 P783: !_ST [0] (maybe <- 0x40800017) (FP) (CBR) (Nucleus ctx) wr %g0, 0x4, %asi ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i0 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET783 nop RET783: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P784: !_ST [31] (maybe <- 0x40800018) (FP) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 192 ] P785: !_REPLACEMENT [24] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l6 ld [%i3+64], %o5 st %o5, [%i3+64] add %i3, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] P786: !_REPLACEMENT [27] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(0x2000), %l3 ld [%i3+160], %l7 st %l7, [%i3+160] add %i3, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] P787: !_MEMBAR (FP) P788: !_BST [22] (maybe <- 0x40800019) (FP) (Branch target of P1085) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi ba P789 nop TARGET1085: ba RET1085 nop P789: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET789 nop RET789: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P790: !_BLD [2] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f0 membar #Sync ! 5 addresses covered fmovs %f4, %f3 fmovd %f8, %f4 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET790 nop RET790: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P791: !_MEMBAR (FP) (Branch target of P760) ba P792 nop TARGET760: ba RET760 nop P792: !_LD [28] (FP) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ld [%i3 + 0], %f5 ! 1 addresses covered P793: !_LD [29] (FP) (Nucleus ctx) wr %g0, 0x4, %asi lda [%i3 + 64] %asi, %f6 ! 1 addresses covered P794: !_PREFETCH [0] (Int) prefetch [%i0 + 0], 1 P795: !_MEMBAR (FP) P796: !_BST [32] (maybe <- 0x4080001c) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 256 ] %asi P797: !_MEMBAR (FP) (Branch target of P1156) membar #StoreLoad ba P798 nop TARGET1156: ba RET1156 nop P798: !_BLD [6] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 fmovd %f40, %f8 P799: !_MEMBAR (FP) (Branch target of P1033) ba P800 nop TARGET1033: ba RET1033 nop P800: !_BSTC [33] (maybe <- 0x4080001d) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 0 ] %asi P801: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET801 nop RET801: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P802: !_BLD [16] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f36, %f18 fmovs %f18, %f9 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET802 nop RET802: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P803: !_MEMBAR (FP) (Branch target of P1169) ba P804 nop TARGET1169: ba RET1169 nop P804: !_ST [25] (maybe <- 0x4080001e) (FP) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i2 + 96 ] %asi P805: !_LD [16] (FP) (Branch target of P840) ld [%i3 + 16], %f10 ! 1 addresses covered ba P806 nop TARGET840: ba RET840 nop P806: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P807: !_BLD [17] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i3 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f40, %f18 fmovs %f18, %f11 P808: !_MEMBAR (FP) (Secondary ctx) P809: !_BLD [22] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f12 fmovd %f40, %f14 P810: !_MEMBAR (FP) (Branch target of P1197) ba P811 nop TARGET1197: ba RET1197 nop P811: !_BST [4] (maybe <- 0x4080001f) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P812: !_MEMBAR (FP) (Branch target of P986) membar #StoreLoad ba P813 nop TARGET986: ba RET986 nop P813: !_BLD [3] (FP) (Branch target of P1147) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovs %f19, %f0 fmovd %f34, %f18 fmovs %f18, %f1 fmovd %f36, %f2 fmovd %f40, %f18 fmovs %f18, %f3 ba P814 nop TARGET1147: ba RET1147 nop P814: !_MEMBAR (FP) P815: !_BLD [33] (FP) (Secondary ctx) (Branch target of P1193) wr %g0, 0xf1, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f4 ba P816 nop TARGET1193: ba RET1193 nop P816: !_MEMBAR (FP) (CBR) (Secondary ctx) (Branch target of P1145) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET816 nop RET816: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P817 nop TARGET1145: ba RET1145 nop P817: !_BSTC [11] (maybe <- 0x40800024) (FP) (CBR) (Secondary ctx) (Branch target of P1000) wr %g0, 0xe1, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET817 nop RET817: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P818 nop TARGET1000: ba RET1000 nop P818: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P819: !_LD [10] (Int) lduw [%i1 + 64], %o2 ! move %o2(lower) -> %o2(upper) sllx %o2, 32, %o2 P820: !_REPLACEMENT [27] (Int) (CBR) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l6 ld [%i3+160], %o5 st %o5, [%i3+160] add %i3, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET820 nop RET820: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P821: !_PREFETCH [8] (Int) prefetch [%i1 + 0], 1 P822: !_MEMBAR (FP) membar #StoreLoad P823: !_BLD [14] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 P824: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET824 nop RET824: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P825: !_BST [12] (maybe <- 0x40800027) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P826: !_MEMBAR (FP) membar #StoreLoad P827: !_BLD [21] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f6 fmovd %f40, %f8 P828: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET828 nop RET828: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P829: !_IDC_FLIP [23] (Int) IDC_FLIP(829, 26945, 2, 0x45800020, 0x20, %i2, 0x20, %l6, %l7, %o5, %l3) P830: !_MEMBAR (FP) membar #StoreLoad P831: !_BLD [23] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f9 fmovs %f19, %f10 fmovd %f40, %f18 fmovs %f18, %f11 P832: !_MEMBAR (FP) P833: !_BSTC [19] (maybe <- 0x4080002a) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 0 ] %asi P834: !_MEMBAR (FP) membar #StoreLoad P835: !_BLD [16] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f36, %f12 P836: !_MEMBAR (FP) P837: !_REPLACEMENT [33] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+0], %l7 st %l7, [%i3+0] add %i3, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] P838: !_REPLACEMENT [26] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(0x2000), %o5 ld [%i3+128], %l6 st %l6, [%i3+128] add %i3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] P839: !_IDC_FLIP [5] (Int) IDC_FLIP(839, 6666, 2, 0x43000040, 0x40, %i0, 0x40, %l6, %l7, %o5, %l3) P840: !_MEMBAR (FP) (CBR) (Branch target of P1119) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET840 nop RET840: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P841 nop TARGET1119: ba RET1119 nop P841: !_BSTC [10] (maybe <- 0x4080002b) (FP) (Branch target of P849) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i1 + 64 ] %asi ba P842 nop TARGET849: ba RET849 nop P842: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET842 nop RET842: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P843: !_BSTC [13] (maybe <- 0x4080002c) (FP) (CBR) wr %g0, 0xe0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET843 nop RET843: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P844: !_MEMBAR (FP) membar #StoreLoad P845: !_BLD [6] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 fmovd %f40, %f14 P846: !_MEMBAR (FP) P847: !_BLD [25] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f40, %f0 P848: !_MEMBAR (FP) (Branch target of P1112) ba P849 nop TARGET1112: ba RET1112 nop P849: !_LD [7] (FP) (CBR) ld [%i0 + 128], %f1 ! 1 addresses covered ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET849 nop RET849: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P850: !_MEMBAR (FP) (Secondary ctx) (Branch target of P1001) membar #StoreLoad ba P851 nop TARGET1001: ba RET1001 nop P851: !_BLD [17] (FP) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f40, %f2 P852: !_MEMBAR (FP) (Secondary ctx) (Branch target of P777) ba P853 nop TARGET777: ba RET777 nop P853: !_BLD [19] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET853 nop RET853: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P854: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET854 nop RET854: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P855: !_REPLACEMENT [31] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l6 ld [%i2+192], %o5 st %o5, [%i2+192] add %i2, %l6, %l7 ld [%l7+192], %o5 st %o5, [%l7+192] add %l7, %l6, %l7 ld [%l7+192], %o5 st %o5, [%l7+192] add %l7, %l6, %l7 ld [%l7+192], %o5 st %o5, [%l7+192] add %l7, %l6, %l7 ld [%l7+192], %o5 st %o5, [%l7+192] add %l7, %l6, %l7 ld [%l7+192], %o5 st %o5, [%l7+192] add %l7, %l6, %l7 ld [%l7+192], %o5 st %o5, [%l7+192] add %l7, %l6, %l7 ld [%l7+192], %o5 st %o5, [%l7+192] P856: !_ST [26] (maybe <- 0x4080002f) (FP) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i3 + 128 ] %asi P857: !_PREFETCH [9] (Int) (Nucleus ctx) wr %g0, 0x4, %asi prefetcha [%i1 + 32] %asi, 1 P858: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET858 nop RET858: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P859: !_BST [33] (maybe <- 0x40800030) (FP) (Branch target of P1040) wr %g0, 0xf0, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 0 ] %asi ba P860 nop TARGET1040: ba RET1040 nop P860: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET860 nop RET860: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P861: !_REPLACEMENT [10] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+64], %l7 st %l7, [%i3+64] add %i3, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] P862: !_MEMBAR (FP) membar #StoreLoad P863: !_BLD [15] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f4 P864: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET864 nop RET864: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P865: !_LD [31] (FP) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ld [%i3 + 192], %f5 ! 1 addresses covered P866: !_REPLACEMENT [25] (Int) (CBR) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+96], %l7 st %l7, [%i2+96] add %i2, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET866 nop RET866: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P867: !_ST [27] (maybe <- 0x1000002) (Int) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stw %l4, [%i3 + 160 ] add %l4, 1, %l4 P868: !_PREFETCH [27] (Int) (LE) wr %g0, 0x88, %asi prefetcha [%i3 + 160] %asi, 1 P869: !_MEMBAR (FP) membar #StoreLoad P870: !_BLD [8] (FP) wr %g0, 0xf0, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f6 fmovd %f40, %f18 fmovs %f18, %f7 P871: !_MEMBAR (FP) P872: !_BST [8] (maybe <- 0x40800031) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i1 + 0 ] %asi P873: !_MEMBAR (FP) membar #StoreLoad P874: !_BLD [14] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f8 P875: !_MEMBAR (FP) P876: !_REPLACEMENT [14] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+64], %l3 st %l3, [%i3+64] add %i3, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] P877: !_LD [8] (Int) (LE) wr %g0, 0x88, %asi lduwa [%i1 + 0] %asi, %l7 ! move %l7(lower) -> %o2(lower) or %l7, %o2, %o2 P878: !_REPLACEMENT [17] (Int) sethi %hi(0x2000), %o5 ld [%i3+96], %l6 st %l6, [%i3+96] add %i3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] P879: !_MEMBAR (FP) membar #StoreLoad P880: !_BLD [5] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f9 fmovd %f40, %f10 P881: !_MEMBAR (FP) P882: !_ST [28] (maybe <- 0x1000003) (Int) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 stw %l4, [%i2 + 0 ] add %l4, 1, %l4 P883: !_MEMBAR (FP) P884: !_BSTC [2] (maybe <- 0x40800033) (FP) (Branch target of P1087) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi ba P885 nop TARGET1087: ba RET1087 nop P885: !_MEMBAR (FP) membar #StoreLoad P886: !_BLD [7] (FP) (Branch target of P1128) wr %g0, 0xf0, %asi ldda [%i0 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 ba P887 nop TARGET1128: ba RET1128 nop P887: !_MEMBAR (FP) (CBR) (Branch target of P722) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET887 nop RET887: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P888 nop TARGET722: ba RET722 nop P888: !_LD [18] (Int) (CBR) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lduwa [%i3 + 128] %asi, %o3 ! move %o3(lower) -> %o3(upper) sllx %o3, 32, %o3 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET888 nop RET888: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P889: !_REPLACEMENT [13] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+32], %l7 st %l7, [%i2+32] add %i2, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] P890: !_ST [19] (maybe <- 0x1000004) (Int) (CBR) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stw %l4, [%i3 + 0 ] add %l4, 1, %l4 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET890 nop RET890: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P891: !_MEMBAR (FP) P892: !_BST [25] (maybe <- 0x40800038) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 64 ] %asi P893: !_MEMBAR (FP) membar #StoreLoad P894: !_BLD [3] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f12 fmovd %f34, %f14 fmovd %f36, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f40, %f0 P895: !_MEMBAR (FP) (Branch target of P1178) ba P896 nop TARGET1178: ba RET1178 nop P896: !_ST [33] (maybe <- 0x1000005) (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stwa %l4, [%i3 + 0] %asi add %l4, 1, %l4 P897: !_MEMBAR (FP) (Secondary ctx) P898: !_BST [19] (maybe <- 0x4080003a) (FP) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 0 ] %asi P899: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P900: !_BLD [25] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 fmovd %f40, %f2 P901: !_MEMBAR (FP) P902: !_BSTC [27] (maybe <- 0x4080003b) (FP) (Branch target of P1158) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 128 ] %asi ba P903 nop TARGET1158: ba RET1158 nop P903: !_MEMBAR (FP) (CBR) (Branch target of P1069) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET903 nop RET903: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 ba P904 nop TARGET1069: ba RET1069 nop P904: !_BLD [1] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 fmovs %f19, %f4 fmovd %f34, %f18 fmovs %f18, %f5 fmovd %f36, %f6 fmovd %f40, %f18 fmovs %f18, %f7 P905: !_MEMBAR (FP) P906: !_REPLACEMENT [16] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+16], %l7 st %l7, [%i2+16] add %i2, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] P907: !_LD [33] (Int) sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lduw [%i3 + 0], %l3 ! move %l3(lower) -> %o3(lower) or %l3, %o3, %o3 P908: !_MEMBAR (FP) membar #StoreLoad P909: !_BLD [19] (FP) (Branch target of P888) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f8 ba P910 nop TARGET888: ba RET888 nop P910: !_MEMBAR (FP) P911: !_BST [33] (maybe <- 0x4080003d) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 0 ] %asi P912: !_MEMBAR (FP) membar #StoreLoad P913: !_REPLACEMENT [25] (Int) (CBR) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+96], %l7 st %l7, [%i3+96] add %i3, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET913 nop RET913: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P914: !_PREFETCH [11] (Int) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 0], 1 P915: !_ST [16] (maybe <- 0x4080003e) (FP) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i3 + 16 ] %asi P916: !_ST [32] (maybe <- 0x1000006) (Int) (CBR) (Branch target of P1127) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 stw %l4, [%i2 + 256 ] add %l4, 1, %l4 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET916 nop RET916: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P917 nop TARGET1127: ba RET1127 nop P917: !_MEMBAR (FP) P918: !_BST [2] (maybe <- 0x4080003f) (FP) (CBR) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET918 nop RET918: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P919: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET919 nop RET919: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P920: !_REPLACEMENT [29] (Int) (CBR) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+64], %l7 st %l7, [%i3+64] add %i3, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET920 nop RET920: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P921: !_ST [15] (maybe <- 0x1000007) (Int) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 stw %l4, [%i2 + 128 ] add %l4, 1, %l4 P922: !_MEMBAR (FP) (Branch target of P1165) ba P923 nop TARGET1165: ba RET1165 nop P923: !_BSTC [10] (maybe <- 0x40800044) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i1 + 64 ] %asi P924: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET924 nop RET924: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P925: !_BLD [18] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f9 P926: !_MEMBAR (FP) P927: !_BSTC [15] (maybe <- 0x40800045) (FP) (Secondary ctx) wr %g0, 0xe1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 128 ] %asi P928: !_MEMBAR (FP) (Secondary ctx) P929: !_BSTC [16] (maybe <- 0x40800046) (FP) (Branch target of P783) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f36 membar #Sync stda %f32, [%i3 + 0 ] %asi ba P930 nop TARGET783: ba RET783 nop P930: !_MEMBAR (FP) (Branch target of P843) membar #StoreLoad ba P931 nop TARGET843: ba RET843 nop P931: !_REPLACEMENT [2] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l6 ld [%i2+8], %o5 st %o5, [%i2+8] add %i2, %l6, %l7 ld [%l7+8], %o5 st %o5, [%l7+8] add %l7, %l6, %l7 ld [%l7+8], %o5 st %o5, [%l7+8] add %l7, %l6, %l7 ld [%l7+8], %o5 st %o5, [%l7+8] add %l7, %l6, %l7 ld [%l7+8], %o5 st %o5, [%l7+8] add %l7, %l6, %l7 ld [%l7+8], %o5 st %o5, [%l7+8] add %l7, %l6, %l7 ld [%l7+8], %o5 st %o5, [%l7+8] add %l7, %l6, %l7 ld [%l7+8], %o5 st %o5, [%l7+8] P932: !_PREFETCH [25] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetcha [%i3 + 96] %asi, 1 P933: !_MEMBAR (FP) (CBR) (Secondary ctx) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET933 nop RET933: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P934: !_BST [25] (maybe <- 0x40800047) (FP) (Secondary ctx) wr %g0, 0xf1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 64 ] %asi P935: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P936: !_ST [14] (maybe <- 0x1000008) (Int) (Branch target of P860) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 stw %l4, [%i2 + 64 ] add %l4, 1, %l4 ba P937 nop TARGET860: ba RET860 nop P937: !_REPLACEMENT [8] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %o5 ld [%i3+0], %l6 st %l6, [%i3+0] add %i3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] P938: !_MEMBAR (FP) (Branch target of P919) membar #StoreLoad ba P939 nop TARGET919: ba RET919 nop P939: !_BLD [28] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f10 P940: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET940 nop RET940: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P941: !_REPLACEMENT [26] (Int) (Branch target of P842) sethi %hi(0x2000), %o5 ld [%i3+128], %l6 st %l6, [%i3+128] add %i3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] ba P942 nop TARGET842: ba RET842 nop P942: !_MEMBAR (FP) P943: !_BST [23] (maybe <- 0x40800049) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P944: !_MEMBAR (FP) membar #StoreLoad P945: !_ST [18] (maybe <- 0x1000009) (Int) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 stw %l4, [%i2 + 128 ] add %l4, 1, %l4 P946: !_LD [1] (Int) (CBR) lduw [%i0 + 4], %o4 ! move %o4(lower) -> %o4(upper) sllx %o4, 32, %o4 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET946 nop RET946: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P947: !_ST [14] (maybe <- 0x4080004c) (FP) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 64 ] P948: !_MEMBAR (FP) (Branch target of P1188) membar #StoreLoad ba P949 nop TARGET1188: ba RET1188 nop P949: !_BLD [27] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 fmovd %f40, %f12 P950: !_MEMBAR (FP) P951: !_BST [15] (maybe <- 0x4080004d) (FP) (Branch target of P973) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 128 ] %asi ba P952 nop TARGET973: ba RET973 nop P952: !_MEMBAR (FP) (CBR) (Branch target of P1157) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET952 nop RET952: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P953 nop TARGET1157: ba RET1157 nop P953: !_LD [33] (FP) (CBR) sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ld [%i3 + 0], %f13 ! 1 addresses covered ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET953 nop RET953: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P954: !_MEMBAR (FP) membar #StoreLoad P955: !_BLD [3] (FP) (Branch target of P978) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f14 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f34, %f0 fmovd %f36, %f18 fmovs %f18, %f1 fmovd %f40, %f2 ba P956 nop TARGET978: ba RET978 nop P956: !_MEMBAR (FP) (Branch target of P801) ba P957 nop TARGET801: ba RET801 nop P957: !_LD [5] (Int) lduw [%i0 + 64], %l3 ! move %l3(lower) -> %o4(lower) or %l3, %o4, %o4 !---- flushing int results buffer---- mov %o0, %l5 mov %o1, %l5 mov %o2, %l5 mov %o3, %l5 mov %o4, %l5 P958: !_LD [10] (FP) (Branch target of P913) ld [%i1 + 64], %f3 ! 1 addresses covered ba P959 nop TARGET913: ba RET913 nop P959: !_IDC_FLIP [8] (Int) (Branch target of P1050) IDC_FLIP(959, 20428, 2, 0x43800000, 0x0, %i1, 0x0, %l6, %l7, %o5, %l3) ba P960 nop TARGET1050: ba RET1050 nop P960: !_LD [12] (FP) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lda [%i2 + 4] %asi, %f4 ! 1 addresses covered P961: !_ST [5] (maybe <- 0x4080004e) (FP) (Secondary ctx) wr %g0, 0x81, %asi ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i0 + 64 ] %asi P962: !_LD [14] (FP) ld [%i2 + 64], %f5 ! 1 addresses covered P963: !_MEMBAR (FP) P964: !_BSTC [14] (maybe <- 0x4080004f) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 64 ] %asi P965: !_MEMBAR (FP) membar #StoreLoad P966: !_LD [0] (FP) (Branch target of P1131) ld [%i0 + 0], %f6 ! 1 addresses covered ba P967 nop TARGET1131: ba RET1131 nop P967: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P968: !_BLD [1] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 fmovs %f19, %f8 fmovd %f34, %f18 fmovs %f18, %f9 fmovd %f36, %f10 fmovd %f40, %f18 fmovs %f18, %f11 P969: !_MEMBAR (FP) (Secondary ctx) (Branch target of P1286) ba P970 nop TARGET1286: ba RET1286 nop P970: !_REPLACEMENT [16] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %o5 ld [%i3+16], %l6 st %l6, [%i3+16] add %i3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] P971: !_MEMBAR (FP) (Branch target of P1236) ba P972 nop TARGET1236: ba RET1236 nop P972: !_BST [19] (maybe <- 0x40800050) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 0 ] %asi P973: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET973 nop RET973: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P974: !_BST [19] (maybe <- 0x40800051) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 0 ] %asi P975: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET975 nop RET975: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P976: !_ST [23] (maybe <- 0x40800052) (FP) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 32 ] P977: !_ST [1] (maybe <- 0x40800053) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i0 + 4 ] P978: !_PREFETCH [11] (Int) (CBR) (Branch target of P820) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 0], 1 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET978 nop RET978: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P979 nop TARGET820: ba RET820 nop P979: !_MEMBAR (FP) P980: !_BST [11] (maybe <- 0x40800054) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P981: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET981 nop RET981: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P982: !_REPLACEMENT [9] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l6 ld [%i3+32], %o5 st %o5, [%i3+32] add %i3, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] P983: !_ST [13] (maybe <- 0x40800057) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 32 ] P984: !_REPLACEMENT [20] (Int) sethi %hi(0x2000), %o5 ld [%i3+256], %l6 st %l6, [%i3+256] add %i3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] P985: !_ST [12] (maybe <- 0x100000a) (Int) stw %l4, [%i2 + 4 ] add %l4, 1, %l4 P986: !_LD [3] (Int) (CBR) (Secondary ctx) wr %g0, 0x81, %asi lduwa [%i0 + 16] %asi, %o0 ! move %o0(lower) -> %o0(upper) sllx %o0, 32, %o0 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET986 nop RET986: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P987: !_ST [12] (maybe <- 0x100000b) (Int) (Nucleus ctx) wr %g0, 0x4, %asi stwa %l4, [%i2 + 4] %asi add %l4, 1, %l4 P988: !_MEMBAR (FP) (Secondary ctx) P989: !_BST [28] (maybe <- 0x40800058) (FP) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 0 ] %asi P990: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P991: !_LD [25] (Int) (CBR) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lduw [%i3 + 96], %o5 ! move %o5(lower) -> %o0(lower) or %o5, %o0, %o0 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET991 nop RET991: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P992: !_LD [33] (FP) sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ld [%i2 + 0], %f12 ! 1 addresses covered P993: !_MEMBAR (FP) membar #StoreLoad P994: !_BLD [9] (FP) (Branch target of P1101) wr %g0, 0xf0, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 fmovd %f40, %f14 ba P995 nop TARGET1101: ba RET1101 nop P995: !_MEMBAR (FP) P996: !_BLD [6] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f40, %f0 P997: !_MEMBAR (FP) P998: !_REPLACEMENT [18] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l6 ld [%i3+128], %o5 st %o5, [%i3+128] add %i3, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] P999: !_MEMBAR (FP) membar #StoreLoad P1000: !_BLD [16] (FP) (CBR) (Branch target of P828) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f36, %f18 fmovs %f18, %f1 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1000 nop RET1000: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P1001 nop TARGET828: ba RET828 nop P1001: !_MEMBAR (FP) (CBR) (Branch target of P981) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1001 nop RET1001: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P1002 nop TARGET981: ba RET981 nop P1002: !_BLD [28] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f2 P1003: !_MEMBAR (FP) P1004: !_REPLACEMENT [16] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l7 ld [%i2+16], %l3 st %l3, [%i2+16] add %i2, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] P1005: !_LD [4] (FP) ld [%i0 + 32], %f3 ! 1 addresses covered P1006: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1006 nop RET1006: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1007: !_BLD [28] (FP) (Branch target of P741) wr %g0, 0xf0, %asi ldda [%i3 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f4 ba P1008 nop TARGET741: ba RET741 nop P1008: !_MEMBAR (FP) P1009: !_LD [33] (Int) (CBR) sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lduw [%i3 + 0], %o1 ! move %o1(lower) -> %o1(upper) sllx %o1, 32, %o1 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1009 nop RET1009: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1010: !_ST [1] (maybe <- 0x100000c) (Int) stw %l4, [%i0 + 4 ] add %l4, 1, %l4 P1011: !_MEMBAR (FP) P1012: !_BST [3] (maybe <- 0x40800059) (FP) (Branch target of P1064) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi ba P1013 nop TARGET1064: ba RET1064 nop P1013: !_MEMBAR (FP) P1014: !_BST [20] (maybe <- 0x4080005e) (FP) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 256 ] %asi P1015: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P1016: !_ST [8] (maybe <- 0x100000d) (Int) stw %l4, [%i1 + 0 ] add %l4, 1, %l4 P1017: !_PREFETCH [2] (Int) prefetch [%i0 + 8], 1 P1018: !_ST [23] (maybe <- 0x100000e) (Int) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stw %l4, [%i3 + 32 ] add %l4, 1, %l4 P1019: !_MEMBAR (FP) P1020: !_BSTC [22] (maybe <- 0x4080005f) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P1021: !_MEMBAR (FP) (Branch target of P946) membar #StoreLoad ba P1022 nop TARGET946: ba RET946 nop P1022: !_ST [29] (maybe <- 0x40800062) (FP) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 64 ] P1023: !_MEMBAR (FP) P1024: !_BSTC [23] (maybe <- 0x40800063) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P1025: !_MEMBAR (FP) membar #StoreLoad P1026: !_REPLACEMENT [1] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l6 ld [%i3+4], %o5 st %o5, [%i3+4] add %i3, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] P1027: !_REPLACEMENT [30] (Int) (Nucleus ctx) (Branch target of P1243) wr %g0, 0x4, %asi sethi %hi(0x2000), %l3 ld [%i3+128], %l7 st %l7, [%i3+128] add %i3, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] ba P1028 nop TARGET1243: ba RET1243 nop P1028: !_REPLACEMENT [28] (Int) sethi %hi(0x2000), %o5 ld [%i3+0], %l6 st %l6, [%i3+0] add %i3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] P1029: !_REPLACEMENT [8] (Int) (Branch target of P775) sethi %hi(0x2000), %l7 ld [%i3+0], %l3 st %l3, [%i3+0] add %i3, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] ba P1030 nop TARGET775: ba RET775 nop P1030: !_LD [32] (FP) ld [%i2 + 256], %f5 ! 1 addresses covered P1031: !_REPLACEMENT [2] (Int) (Branch target of P802) sethi %hi(0x2000), %l6 ld [%i3+8], %o5 st %o5, [%i3+8] add %i3, %l6, %l7 ld [%l7+8], %o5 st %o5, [%l7+8] add %l7, %l6, %l7 ld [%l7+8], %o5 st %o5, [%l7+8] add %l7, %l6, %l7 ld [%l7+8], %o5 st %o5, [%l7+8] add %l7, %l6, %l7 ld [%l7+8], %o5 st %o5, [%l7+8] add %l7, %l6, %l7 ld [%l7+8], %o5 st %o5, [%l7+8] add %l7, %l6, %l7 ld [%l7+8], %o5 st %o5, [%l7+8] add %l7, %l6, %l7 ld [%l7+8], %o5 st %o5, [%l7+8] ba P1032 nop TARGET802: ba RET802 nop P1032: !_ST [21] (maybe <- 0x40800066) (FP) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 0 ] P1033: !_REPLACEMENT [25] (Int) (CBR) sethi %hi(0x2000), %o5 ld [%i3+96], %l6 st %l6, [%i3+96] add %i3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1033 nop RET1033: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1034: !_MEMBAR (FP) (Branch target of P933) membar #StoreLoad ba P1035 nop TARGET933: ba RET933 nop P1035: !_BLD [15] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f6 P1036: !_MEMBAR (FP) (Branch target of P864) ba P1037 nop TARGET864: ba RET864 nop P1037: !_BSTC [5] (maybe <- 0x40800067) (FP) (CBR) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1037 nop RET1037: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1038: !_MEMBAR (FP) (Branch target of P1284) ba P1039 nop TARGET1284: ba RET1284 nop P1039: !_BSTC [22] (maybe <- 0x40800069) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P1040: !_MEMBAR (FP) (CBR) (Branch target of P789) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1040 nop RET1040: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P1041 nop TARGET789: ba RET789 nop P1041: !_ST [0] (maybe <- 0x4080006c) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i0 + 0 ] P1042: !_ST [11] (maybe <- 0x4080006d) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 0 ] P1043: !_MEMBAR (FP) P1044: !_BSTC [7] (maybe <- 0x4080006e) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i0 + 128 ] %asi P1045: !_MEMBAR (FP) membar #StoreLoad P1046: !_REPLACEMENT [28] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+0], %l7 st %l7, [%i2+0] add %i2, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] P1047: !_LD [3] (FP) ld [%i0 + 16], %f7 ! 1 addresses covered P1048: !_LD [19] (Int) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lduw [%i3 + 0], %l3 ! move %l3(lower) -> %o1(lower) or %l3, %o1, %o1 P1049: !_PREFETCH [19] (Int) (Nucleus ctx) wr %g0, 0x4, %asi prefetcha [%i3 + 0] %asi, 1 P1050: !_PREFETCH [6] (Int) (CBR) (Secondary ctx) wr %g0, 0x81, %asi prefetcha [%i0 + 96] %asi, 1 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1050 nop RET1050: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1051: !_IDC_FLIP [9] (Int) IDC_FLIP(1051, 20083, 2, 0x43800020, 0x20, %i1, 0x20, %l6, %l7, %o5, %l3) P1052: !_MEMBAR (FP) (Branch target of P1089) ba P1053 nop TARGET1089: ba RET1089 nop P1053: !_BST [14] (maybe <- 0x4080006f) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 64 ] %asi P1054: !_MEMBAR (FP) membar #StoreLoad P1055: !_ST [3] (maybe <- 0x40800070) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i0 + 16 ] P1056: !_MEMBAR (FP) (Secondary ctx) (Branch target of P1006) membar #StoreLoad ba P1057 nop TARGET1006: ba RET1006 nop P1057: !_BLD [32] (FP) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f8 P1058: !_MEMBAR (FP) (CBR) (Secondary ctx) (Branch target of P1261) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1058 nop RET1058: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 ba P1059 nop TARGET1261: ba RET1261 nop P1059: !_BSTC [2] (maybe <- 0x40800071) (FP) (CBR) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1059 nop RET1059: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1060: !_MEMBAR (FP) (Branch target of P903) ba P1061 nop TARGET903: ba RET903 nop P1061: !_BSTC [26] (maybe <- 0x40800076) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 128 ] %asi P1062: !_MEMBAR (FP) P1063: !_BSTC [29] (maybe <- 0x40800078) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 64 ] %asi P1064: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1064 nop RET1064: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1065: !_BST [29] (maybe <- 0x40800079) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 64 ] %asi P1066: !_MEMBAR (FP) membar #StoreLoad P1067: !_IDC_FLIP [0] (Int) IDC_FLIP(1067, 9313, 2, 0x43000000, 0x0, %i0, 0x0, %l6, %l7, %o5, %l3) P1068: !_MEMBAR (FP) membar #StoreLoad P1069: !_BLD [9] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f9 fmovd %f40, %f10 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1069 nop RET1069: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1070: !_MEMBAR (FP) P1071: !_BLD [26] (FP) (CBR) (Branch target of P824) wr %g0, 0xf0, %asi ldda [%i2 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 fmovd %f40, %f12 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1071 nop RET1071: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P1072 nop TARGET824: ba RET824 nop P1072: !_MEMBAR (FP) (Branch target of P953) ba P1073 nop TARGET953: ba RET953 nop P1073: !_PREFETCH [18] (Int) (LE) (Branch target of P1090) wr %g0, 0x88, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetcha [%i3 + 128] %asi, 1 ba P1074 nop TARGET1090: ba RET1090 nop P1074: !_PREFETCH [3] (Int) prefetch [%i0 + 16], 1 P1075: !_MEMBAR (FP) P1076: !_BSTC [0] (maybe <- 0x4080007a) (FP) (Branch target of P866) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi ba P1077 nop TARGET866: ba RET866 nop P1077: !_MEMBAR (FP) membar #StoreLoad P1078: !_ST [30] (maybe <- 0x4080007f) (FP) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 128 ] P1079: !_MEMBAR (FP) (CBR) (Secondary ctx) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1079 nop RET1079: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1080: !_BLD [29] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i2 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 P1081: !_MEMBAR (FP) (Secondary ctx) P1082: !_BLD [1] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f14 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f34, %f0 fmovd %f36, %f18 fmovs %f18, %f1 fmovd %f40, %f2 P1083: !_MEMBAR (FP) P1084: !_BST [21] (maybe <- 0x40800080) (FP) (Secondary ctx) (Branch target of P1263) wr %g0, 0xf1, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi ba P1085 nop TARGET1263: ba RET1263 nop P1085: !_MEMBAR (FP) (CBR) (Secondary ctx) (Branch target of P1164) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1085 nop RET1085: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P1086 nop TARGET1164: ba RET1164 nop P1086: !_BST [26] (maybe <- 0x40800083) (FP) (Branch target of P1228) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 128 ] %asi ba P1087 nop TARGET1228: ba RET1228 nop P1087: !_MEMBAR (FP) (CBR) (Branch target of P753) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1087 nop RET1087: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P1088 nop TARGET753: ba RET753 nop P1088: !_BSTC [32] (maybe <- 0x40800085) (FP) (CBR) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 256 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1088 nop RET1088: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1089: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1089 nop RET1089: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1090: !_BSTC [10] (maybe <- 0x40800086) (FP) (CBR) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i1 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1090 nop RET1090: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1091: !_MEMBAR (FP) (Branch target of P1059) membar #StoreLoad ba P1092 nop TARGET1059: ba RET1059 nop P1092: !_PREFETCH [27] (Int) prefetch [%i3 + 160], 1 P1093: !_REPLACEMENT [18] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %o5 ld [%i2+128], %l6 st %l6, [%i2+128] add %i2, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] P1094: !_PREFETCH [25] (Int) prefetch [%i3 + 96], 1 P1095: !_REPLACEMENT [24] (Int) sethi %hi(0x2000), %l7 ld [%i2+64], %l3 st %l3, [%i2+64] add %i2, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] P1096: !_MEMBAR (FP) P1097: !_BSTC [31] (maybe <- 0x40800087) (FP) (Branch target of P1288) wr %g0, 0xe0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 192 ] %asi ba P1098 nop TARGET1288: ba RET1288 nop P1098: !_MEMBAR (FP) membar #StoreLoad P1099: !_REPLACEMENT [27] (Int) sethi %hi(0x2000), %l3 ld [%i2+160], %l7 st %l7, [%i2+160] add %i2, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] P1100: !_MEMBAR (FP) (Branch target of P790) membar #StoreLoad ba P1101 nop TARGET790: ba RET790 nop P1101: !_BLD [7] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i0 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1101 nop RET1101: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1102: !_MEMBAR (FP) P1103: !_REPLACEMENT [21] (Int) (Branch target of P1124) sethi %hi(0x2000), %l3 ld [%i2+0], %l7 st %l7, [%i2+0] add %i2, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] ba P1104 nop TARGET1124: ba RET1124 nop P1104: !_REPLACEMENT [33] (Int) sethi %hi(0x2000), %o5 ld [%i2+0], %l6 st %l6, [%i2+0] add %i2, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] P1105: !_MEMBAR (FP) membar #StoreLoad P1106: !_BLD [19] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f4 P1107: !_MEMBAR (FP) (Branch target of P717) ba P1108 nop TARGET717: ba RET717 nop P1108: !_BST [28] (maybe <- 0x40800088) (FP) (Secondary ctx) wr %g0, 0xf1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 0 ] %asi P1109: !_MEMBAR (FP) (Secondary ctx) P1110: !_BSTC [18] (maybe <- 0x40800089) (FP) (Secondary ctx) wr %g0, 0xe1, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 128 ] %asi P1111: !_MEMBAR (FP) (Secondary ctx) P1112: !_BST [9] (maybe <- 0x4080008a) (FP) (CBR) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i1 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1112 nop RET1112: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1113: !_MEMBAR (FP) membar #StoreLoad P1114: !_BLD [29] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 P1115: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1115 nop RET1115: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1116: !_ST [13] (maybe <- 0x4080008c) (FP) (Nucleus ctx) (Branch target of P1207) wr %g0, 0x4, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i3 + 32 ] %asi ba P1117 nop TARGET1207: ba RET1207 nop P1117: !_REPLACEMENT [10] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+64], %l7 st %l7, [%i2+64] add %i2, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] P1118: !_MEMBAR (FP) membar #StoreLoad P1119: !_BLD [7] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i0 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f6 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1119 nop RET1119: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1120: !_MEMBAR (FP) P1121: !_BLD [22] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 fmovs %f19, %f8 fmovd %f40, %f18 fmovs %f18, %f9 P1122: !_MEMBAR (FP) (Branch target of P1079) ba P1123 nop TARGET1079: ba RET1079 nop P1123: !_BLD [22] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f10 fmovd %f40, %f12 P1124: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1124 nop RET1124: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1125: !_REPLACEMENT [23] (Int) sethi %hi(0x2000), %l6 ld [%i2+32], %o5 st %o5, [%i2+32] add %i2, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] P1126: !_MEMBAR (FP) membar #StoreLoad P1127: !_BLD [9] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 fmovd %f40, %f14 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1127 nop RET1127: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1128: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1128 nop RET1128: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1129: !_REPLACEMENT [14] (Int) sethi %hi(0x2000), %l7 ld [%i2+64], %l3 st %l3, [%i2+64] add %i2, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] P1130: !_MEMBAR (FP) membar #StoreLoad P1131: !_BLD [4] (FP) (CBR) (Branch target of P1225) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovs %f19, %f0 fmovd %f34, %f18 fmovs %f18, %f1 fmovd %f36, %f2 fmovd %f40, %f18 fmovs %f18, %f3 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1131 nop RET1131: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P1132 nop TARGET1225: ba RET1225 nop P1132: !_MEMBAR (FP) P1133: !_BLD [19] (FP) (Secondary ctx) (Branch target of P1115) wr %g0, 0xf1, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f4 ba P1134 nop TARGET1115: ba RET1115 nop P1134: !_MEMBAR (FP) (Secondary ctx) P1135: !_LD [24] (Int) (Secondary ctx) wr %g0, 0x81, %asi lduwa [%i3 + 64] %asi, %o2 ! move %o2(lower) -> %o2(upper) sllx %o2, 32, %o2 P1136: !_REPLACEMENT [2] (Int) (Branch target of P1088) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+8], %l7 st %l7, [%i3+8] add %i3, %l3, %l6 ld [%l6+8], %l7 st %l7, [%l6+8] add %l6, %l3, %l6 ld [%l6+8], %l7 st %l7, [%l6+8] add %l6, %l3, %l6 ld [%l6+8], %l7 st %l7, [%l6+8] add %l6, %l3, %l6 ld [%l6+8], %l7 st %l7, [%l6+8] add %l6, %l3, %l6 ld [%l6+8], %l7 st %l7, [%l6+8] add %l6, %l3, %l6 ld [%l6+8], %l7 st %l7, [%l6+8] add %l6, %l3, %l6 ld [%l6+8], %l7 st %l7, [%l6+8] ba P1137 nop TARGET1088: ba RET1088 nop P1137: !_REPLACEMENT [23] (Int) (Secondary ctx) (Branch target of P1071) wr %g0, 0x81, %asi sethi %hi(0x2000), %o5 ld [%i3+32], %l6 st %l6, [%i3+32] add %i3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] ba P1138 nop TARGET1071: ba RET1071 nop P1138: !_MEMBAR (FP) membar #StoreLoad P1139: !_BLD [33] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 P1140: !_MEMBAR (FP) P1141: !_LD [22] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lduwa [%i3 + 4] %asi, %o5 ! move %o5(lower) -> %o2(lower) or %o5, %o2, %o2 P1142: !_REPLACEMENT [18] (Int) (Branch target of P991) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+128], %l7 st %l7, [%i2+128] add %i2, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] ba P1143 nop TARGET991: ba RET991 nop P1143: !_MEMBAR (FP) (Branch target of P1239) membar #StoreLoad ba P1144 nop TARGET1239: ba RET1239 nop P1144: !_BLD [21] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f6 fmovd %f40, %f8 P1145: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1145 nop RET1145: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1146: !_BLD [22] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f9 fmovs %f19, %f10 fmovd %f40, %f18 fmovs %f18, %f11 P1147: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1147 nop RET1147: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1148: !_REPLACEMENT [19] (Int) sethi %hi(0x2000), %l6 ld [%i2+0], %o5 st %o5, [%i2+0] add %i2, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] P1149: !_MEMBAR (FP) P1150: !_BSTC [33] (maybe <- 0x4080008d) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 0 ] %asi P1151: !_MEMBAR (FP) membar #StoreLoad P1152: !_BLD [19] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f12 P1153: !_MEMBAR (FP) P1154: !_BST [12] (maybe <- 0x4080008e) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P1155: !_MEMBAR (FP) membar #StoreLoad P1156: !_BLD [16] (FP) (CBR) (Branch target of P1272) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f36, %f18 fmovs %f18, %f13 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1156 nop RET1156: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P1157 nop TARGET1272: ba RET1272 nop P1157: !_MEMBAR (FP) (CBR) (Branch target of P721) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1157 nop RET1157: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 ba P1158 nop TARGET721: ba RET721 nop P1158: !_REPLACEMENT [31] (Int) (CBR) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+192], %l7 st %l7, [%i3+192] add %i3, %l3, %l6 ld [%l6+192], %l7 st %l7, [%l6+192] add %l6, %l3, %l6 ld [%l6+192], %l7 st %l7, [%l6+192] add %l6, %l3, %l6 ld [%l6+192], %l7 st %l7, [%l6+192] add %l6, %l3, %l6 ld [%l6+192], %l7 st %l7, [%l6+192] add %l6, %l3, %l6 ld [%l6+192], %l7 st %l7, [%l6+192] add %l6, %l3, %l6 ld [%l6+192], %l7 st %l7, [%l6+192] add %l6, %l3, %l6 ld [%l6+192], %l7 st %l7, [%l6+192] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1158 nop RET1158: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1159: !_MEMBAR (FP) (Secondary ctx) (Branch target of P1167) membar #StoreLoad ba P1160 nop TARGET1167: ba RET1167 nop P1160: !_BLD [11] (FP) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f14 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f40, %f0 P1161: !_MEMBAR (FP) (Secondary ctx) P1162: !_REPLACEMENT [4] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(0x2000), %l3 ld [%i3+32], %l7 st %l7, [%i3+32] add %i3, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] P1163: !_REPLACEMENT [24] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(0x2000), %o5 ld [%i3+64], %l6 st %l6, [%i3+64] add %i3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] P1164: !_PREFETCH [13] (Int) (CBR) prefetch [%i2 + 32], 1 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1164 nop RET1164: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1165: !_ST [29] (maybe <- 0x40800091) (FP) (CBR) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i3 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1165 nop RET1165: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1166: !_ST [32] (maybe <- 0x100000f) (Int) stw %l4, [%i3 + 256 ] add %l4, 1, %l4 P1167: !_REPLACEMENT [1] (Int) (CBR) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l7 ld [%i2+4], %l3 st %l3, [%i2+4] add %i2, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1167 nop RET1167: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1168: !_MEMBAR (FP) (Branch target of P1269) ba P1169 nop TARGET1269: ba RET1269 nop P1169: !_BSTC [33] (maybe <- 0x40800092) (FP) (CBR) wr %g0, 0xe0, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1169 nop RET1169: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1170: !_MEMBAR (FP) (Branch target of P854) ba P1171 nop TARGET854: ba RET854 nop P1171: !_BST [18] (maybe <- 0x40800093) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 128 ] %asi P1172: !_MEMBAR (FP) membar #StoreLoad P1173: !_REPLACEMENT [1] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l6 ld [%i3+4], %o5 st %o5, [%i3+4] add %i3, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] P1174: !_MEMBAR (FP) membar #StoreLoad P1175: !_BLD [1] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 fmovs %f19, %f2 fmovd %f34, %f18 fmovs %f18, %f3 fmovd %f36, %f4 fmovd %f40, %f18 fmovs %f18, %f5 P1176: !_MEMBAR (FP) P1177: !_IDC_FLIP [13] (Int) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 IDC_FLIP(1177, 1731, 2, 0x44000020, 0x20, %i2, 0x20, %l6, %l7, %o5, %l3) P1178: !_MEMBAR (FP) (CBR) (Branch target of P1058) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1178 nop RET1178: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P1179 nop TARGET1058: ba RET1058 nop P1179: !_BST [12] (maybe <- 0x40800094) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P1180: !_MEMBAR (FP) membar #StoreLoad P1181: !_ST [25] (maybe <- 0x1000010) (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stwa %l4, [%i3 + 96] %asi add %l4, 1, %l4 P1182: !_ST [5] (maybe <- 0x1000011) (Int) (Branch target of P1215) stw %l4, [%i0 + 64 ] add %l4, 1, %l4 ba P1183 nop TARGET1215: ba RET1215 nop P1183: !_MEMBAR (FP) membar #StoreLoad P1184: !_BLD [8] (FP) wr %g0, 0xf0, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f6 fmovd %f40, %f18 fmovs %f18, %f7 P1185: !_MEMBAR (FP) P1186: !_BLD [23] (FP) (Branch target of P858) wr %g0, 0xf0, %asi ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f8 fmovd %f40, %f10 ba P1187 nop TARGET858: ba RET858 nop P1187: !_MEMBAR (FP) P1188: !_BSTC [24] (maybe <- 0x40800097) (FP) (CBR) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1188 nop RET1188: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1189: !_MEMBAR (FP) membar #StoreLoad P1190: !_REPLACEMENT [21] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %o5 ld [%i2+0], %l6 st %l6, [%i2+0] add %i2, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] P1191: !_REPLACEMENT [16] (Int) (Branch target of P1241) sethi %hi(0x2000), %l7 ld [%i2+16], %l3 st %l3, [%i2+16] add %i2, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] ba P1192 nop TARGET1241: ba RET1241 nop P1192: !_REPLACEMENT [32] (Int) sethi %hi(0x2000), %l6 ld [%i2+256], %o5 st %o5, [%i2+256] add %i2, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] P1193: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1193 nop RET1193: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1194: !_BSTC [20] (maybe <- 0x40800099) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 256 ] %asi P1195: !_MEMBAR (FP) (Branch target of P920) membar #StoreLoad ba P1196 nop TARGET920: ba RET920 nop P1196: !_LD [2] (FP) (Nucleus ctx) wr %g0, 0x4, %asi lda [%i0 + 8] %asi, %f11 ! 1 addresses covered P1197: !_PREFETCH [23] (Int) (CBR) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 32], 1 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1197 nop RET1197: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1198: !_MEMBAR (FP) membar #StoreLoad P1199: !_BLD [19] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i3 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f12 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1199 nop RET1199: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1200: !_MEMBAR (FP) (Branch target of P1273) ba P1201 nop TARGET1273: ba RET1273 nop P1201: !_BLD [13] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 fmovs %f19, %f14 fmovd %f40, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- P1202: !_MEMBAR (FP) P1203: !_BLD [4] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f0 membar #Sync ! 5 addresses covered fmovs %f4, %f3 fmovd %f8, %f4 P1204: !_MEMBAR (FP) P1205: !_LD [30] (Int) (Branch target of P1199) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduw [%i2 + 128], %o3 ! move %o3(lower) -> %o3(upper) sllx %o3, 32, %o3 ba P1206 nop TARGET1199: ba RET1199 nop P1206: !_IDC_FLIP [3] (Int) IDC_FLIP(1206, 18737, 2, 0x43000010, 0x10, %i0, 0x10, %l6, %l7, %o5, %l3) P1207: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1207 nop RET1207: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1208: !_BLD [11] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 fmovs %f19, %f6 fmovd %f40, %f18 fmovs %f18, %f7 P1209: !_MEMBAR (FP) P1210: !_BLD [7] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f8 P1211: !_MEMBAR (FP) P1212: !_BST [26] (maybe <- 0x4080009a) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 128 ] %asi P1213: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1213 nop RET1213: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1214: !_BSTC [7] (maybe <- 0x4080009c) (FP) (CBR) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i0 + 128 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1214 nop RET1214: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1215: !_MEMBAR (FP) (CBR) (Branch target of P1213) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1215 nop RET1215: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P1216 nop TARGET1213: ba RET1213 nop P1216: !_BLD [21] (FP) (Secondary ctx) (Branch target of P817) wr %g0, 0xf1, %asi ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f9 fmovs %f19, %f10 fmovd %f40, %f18 fmovs %f18, %f11 ba P1217 nop TARGET817: ba RET817 nop P1217: !_MEMBAR (FP) (Secondary ctx) P1218: !_BST [30] (maybe <- 0x4080009d) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 128 ] %asi P1219: !_MEMBAR (FP) membar #StoreLoad P1220: !_LD [21] (FP) (CBR) ld [%i3 + 0], %f12 ! 1 addresses covered ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1220 nop RET1220: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1221: !_MEMBAR (FP) membar #StoreLoad P1222: !_BLD [3] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 fmovs %f19, %f14 fmovd %f34, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f36, %f0 fmovd %f40, %f18 fmovs %f18, %f1 P1223: !_MEMBAR (FP) P1224: !_REPLACEMENT [2] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %o5 ld [%i2+8], %l6 st %l6, [%i2+8] add %i2, %o5, %l3 ld [%l3+8], %l6 st %l6, [%l3+8] add %l3, %o5, %l3 ld [%l3+8], %l6 st %l6, [%l3+8] add %l3, %o5, %l3 ld [%l3+8], %l6 st %l6, [%l3+8] add %l3, %o5, %l3 ld [%l3+8], %l6 st %l6, [%l3+8] add %l3, %o5, %l3 ld [%l3+8], %l6 st %l6, [%l3+8] add %l3, %o5, %l3 ld [%l3+8], %l6 st %l6, [%l3+8] add %l3, %o5, %l3 ld [%l3+8], %l6 st %l6, [%l3+8] P1225: !_ST [5] (maybe <- 0x1000012) (Int) (CBR) (Secondary ctx) wr %g0, 0x81, %asi stwa %l4, [%i0 + 64] %asi add %l4, 1, %l4 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1225 nop RET1225: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1226: !_MEMBAR (FP) (Branch target of P1234) membar #StoreLoad ba P1227 nop TARGET1234: ba RET1234 nop P1227: !_BLD [16] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f36, %f2 P1228: !_MEMBAR (FP) (CBR) (Branch target of P816) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1228 nop RET1228: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P1229 nop TARGET816: ba RET816 nop P1229: !_REPLACEMENT [24] (Int) sethi %hi(0x2000), %o5 ld [%i2+64], %l6 st %l6, [%i2+64] add %i2, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] P1230: !_REPLACEMENT [29] (Int) sethi %hi(0x2000), %l7 ld [%i2+64], %l3 st %l3, [%i2+64] add %i2, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] P1231: !_PREFETCH [15] (Int) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 128], 1 P1232: !_MEMBAR (FP) membar #StoreLoad P1233: !_BLD [24] (FP) (CBR) (Branch target of P759) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 fmovd %f40, %f4 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1233 nop RET1233: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P1234 nop TARGET759: ba RET759 nop P1234: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1234 nop RET1234: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1235: !_REPLACEMENT [7] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %o5 ld [%i2+128], %l6 st %l6, [%i2+128] add %i2, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] P1236: !_REPLACEMENT [26] (Int) (CBR) sethi %hi(0x2000), %l7 ld [%i2+128], %l3 st %l3, [%i2+128] add %i2, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1236 nop RET1236: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1237: !_ST [10] (maybe <- 0x1000013) (Int) stw %l4, [%i1 + 64 ] add %l4, 1, %l4 P1238: !_MEMBAR (FP) P1239: !_BSTC [28] (maybe <- 0x4080009e) (FP) (CBR) wr %g0, 0xe0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1239 nop RET1239: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1240: !_MEMBAR (FP) (Branch target of P1220) membar #StoreLoad ba P1241 nop TARGET1220: ba RET1220 nop P1241: !_BLD [22] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 fmovs %f19, %f6 fmovd %f40, %f18 fmovs %f18, %f7 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1241 nop RET1241: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1242: !_MEMBAR (FP) P1243: !_LD [32] (Int) (CBR) lduw [%i3 + 256], %o5 ! move %o5(lower) -> %o3(lower) or %o5, %o3, %o3 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1243 nop RET1243: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1244: !_MEMBAR (FP) membar #StoreLoad P1245: !_BLD [3] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f8 fmovd %f34, %f10 fmovd %f36, %f18 fmovs %f18, %f11 fmovd %f40, %f12 P1246: !_MEMBAR (FP) P1247: !_LD [1] (Int) lduw [%i0 + 4], %o4 ! move %o4(lower) -> %o4(upper) sllx %o4, 32, %o4 P1248: !_MEMBAR (FP) membar #StoreLoad P1249: !_BLD [2] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 fmovs %f19, %f14 fmovd %f34, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f36, %f0 fmovd %f40, %f18 fmovs %f18, %f1 P1250: !_MEMBAR (FP) P1251: !_ST [33] (maybe <- 0x1000014) (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stwa %l4, [%i3 + 0] %asi add %l4, 1, %l4 P1252: !_LD [29] (FP) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ld [%i2 + 64], %f2 ! 1 addresses covered P1253: !_ST [17] (maybe <- 0x4080009f) (FP) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 96 ] P1254: !_PREFETCH [23] (Int) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 32], 1 P1255: !_MEMBAR (FP) membar #StoreLoad P1256: !_BLD [16] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f36, %f18 fmovs %f18, %f3 P1257: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1257 nop RET1257: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1258: !_BLD [29] (FP) (Branch target of P1214) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f4 ba P1259 nop TARGET1214: ba RET1214 nop P1259: !_MEMBAR (FP) P1260: !_REPLACEMENT [9] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l7 ld [%i2+32], %l3 st %l3, [%i2+32] add %i2, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] P1261: !_REPLACEMENT [23] (Int) (CBR) sethi %hi(0x2000), %l6 ld [%i2+32], %o5 st %o5, [%i2+32] add %i2, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1261 nop RET1261: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1262: !_MEMBAR (FP) (Branch target of P853) membar #StoreLoad ba P1263 nop TARGET853: ba RET853 nop P1263: !_BLD [3] (FP) (CBR) (Branch target of P890) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 fmovs %f19, %f6 fmovd %f34, %f18 fmovs %f18, %f7 fmovd %f36, %f8 fmovd %f40, %f18 fmovs %f18, %f9 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1263 nop RET1263: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P1264 nop TARGET890: ba RET890 nop P1264: !_MEMBAR (FP) P1265: !_REPLACEMENT [12] (Int) sethi %hi(0x2000), %l7 ld [%i2+4], %l3 st %l3, [%i2+4] add %i2, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] P1266: !_REPLACEMENT [5] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(0x2000), %l6 ld [%i2+64], %o5 st %o5, [%i2+64] add %i2, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] P1267: !_LD [16] (FP) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ld [%i3 + 16], %f10 ! 1 addresses covered P1268: !_MEMBAR (FP) (Branch target of P745) ba P1269 nop TARGET745: ba RET745 nop P1269: !_BSTC [30] (maybe <- 0x408000a0) (FP) (CBR) (Branch target of P975) wr %g0, 0xe0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 128 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1269 nop RET1269: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 ba P1270 nop TARGET975: ba RET975 nop P1270: !_MEMBAR (FP) P1271: !_BST [30] (maybe <- 0x408000a1) (FP) (Secondary ctx) wr %g0, 0xf1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 128 ] %asi P1272: !_MEMBAR (FP) (CBR) (Secondary ctx) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1272 nop RET1272: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1273: !_BLD [7] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i0 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1273 nop RET1273: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1274: !_MEMBAR (FP) P1275: !_PREFETCH [6] (Int) prefetch [%i0 + 96], 1 P1276: !_MEMBAR (FP) P1277: !_BSTC [14] (maybe <- 0x408000a2) (FP) (Branch target of P1257) wr %g0, 0xe0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 64 ] %asi ba P1278 nop TARGET1257: ba RET1257 nop P1278: !_MEMBAR (FP) P1279: !_BST [23] (maybe <- 0x408000a3) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P1280: !_MEMBAR (FP) P1281: !_BST [21] (maybe <- 0x408000a6) (FP) (CBR) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1281 nop RET1281: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1282: !_MEMBAR (FP) membar #StoreLoad P1283: !_REPLACEMENT [27] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %o5 ld [%i3+160], %l6 st %l6, [%i3+160] add %i3, %o5, %l3 ld [%l3+160], %l6 st %l6, [%l3+160] add %l3, %o5, %l3 ld [%l3+160], %l6 st %l6, [%l3+160] add %l3, %o5, %l3 ld [%l3+160], %l6 st %l6, [%l3+160] add %l3, %o5, %l3 ld [%l3+160], %l6 st %l6, [%l3+160] add %l3, %o5, %l3 ld [%l3+160], %l6 st %l6, [%l3+160] add %l3, %o5, %l3 ld [%l3+160], %l6 st %l6, [%l3+160] add %l3, %o5, %l3 ld [%l3+160], %l6 st %l6, [%l3+160] P1284: !_ST [21] (maybe <- 0x408000a9) (FP) (CBR) (Secondary ctx) wr %g0, 0x81, %asi ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i2 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1284 nop RET1284: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1285: !_MEMBAR (FP) (Secondary ctx) P1286: !_BST [33] (maybe <- 0x408000aa) (FP) (CBR) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1286 nop RET1286: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1287: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P1288: !_BLD [10] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i1 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f12 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1288 nop RET1288: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1289: !_MEMBAR (FP) P1290: !_LD [18] (Int) (Loop exit) (Secondary ctx) (Branch target of P1281) wr %g0, 0x81, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lduwa [%i3 + 128] %asi, %l3 ! move %l3(lower) -> %o4(lower) or %l3, %o4, %o4 !---- flushing int results buffer---- mov %o0, %l5 mov %o1, %l5 mov %o2, %l5 mov %o3, %l5 mov %o4, %l5 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovs %f12, %f30 !-- loop_exit_2_0: sub %l2, 1, %l2 cmp %l2, 0 bg loop_entry_2_0 nop ba P1291 nop TARGET1281: ba RET1281 nop P1291: !_MEMBAR (Int) membar #StoreLoad END_NODES2: ! Test instruction sequence for CPU 2 ends sethi %hi(0xdead0e0f), %l7 or %l7, %lo(0xdead0e0f), %l7 ! move %l7(lower) -> %o0(upper) sllx %l7, 32, %o0 sethi %hi(0xdead0e0f), %l7 or %l7, %lo(0xdead0e0f), %l7 stw %l7, [%i5] ld [%i5], %f0 !---- flushing int results buffer---- mov %o0, %l5 !---- flushing fp results buffer to %f30 ---- fmovs %f0, %f30 !-- restore retl nop !----------------- ! register usage: ! %i0 %i1 : base registers for first 2 regions ! %i2 %i3 : cache registers for 8 regions ! %i4 fixed pointer to per-cpu results area ! %l1 moving pointer to per-cpu FP results area ! %o7 moving pointer to per-cpu integer results area ! %i5 pointer to per-cpu private area ! %l0 holds lfsr, used as source of random bits ! %l2 loop count register ! %f16 running counter for unique fp store values ! %f17 holds increment value for fp counter ! %l4 running counter for unique integer store values (increment value is always 1) ! %l5 move-to register for load values (simulation only) ! %f30 move-to register for FP values (simulation only) ! %i4 holds the instructions count which is used for interrupt ordering ! %i4 holds the thread_id (OBP only) ! %l5 holds the moving pointer for interrupt bonus data (OBP only). Conflicts with RTL/simulation usage ! %l3 %l6 %l7 %o5 : 4 temporary registers ! %o0 %o1 %o2 %o3 %o4 : 5 integer results buffer registers ! %f0-f15 FP results buffer registers ! %f32-f47 FP block load/store registers func3: ! instruction sequence begins save %sp, -192, %sp ! Force %i0-%i3 to be 64-byte aligned add %i0, 63, %i0 andn %i0, 63, %i0 add %i1, 63, %i1 andn %i1, 63, %i1 add %i2, 63, %i2 andn %i2, 63, %i2 add %i3, 63, %i3 andn %i3, 63, %i3 add %i4, 63, %i4 andn %i4, 63, %i4 add %i5, 63, %i5 andn %i5, 63, %i5 ! Initialize pointer to FP load results area mov %i4, %l1 ! Initialize pointer to integer load results area sethi %hi(0x80000), %o7 or %o7, %lo(0x80000), %o7 add %o7, %l1, %o7 ! Reinitialize i4 to 0. i4 will be used to keep the count of analyzable node info mov 0x0, %i4 ! Initialize %f0-%f62 to 0xdeadbee0deadbee1 sethi %hi(0xdeadbee0), %l6 or %l6, %lo(0xdeadbee0), %l6 stw %l6, [%i5] sethi %hi(0xdeadbee1), %l6 or %l6, %lo(0xdeadbee1), %l6 stw %l6, [%i5+4] ldd [%i5], %f0 fmovd %f0, %f2 fmovd %f0, %f4 fmovd %f0, %f6 fmovd %f0, %f8 fmovd %f0, %f10 fmovd %f0, %f12 fmovd %f0, %f14 fmovd %f0, %f16 fmovd %f0, %f18 fmovd %f0, %f20 fmovd %f0, %f22 fmovd %f0, %f24 fmovd %f0, %f26 fmovd %f0, %f28 fmovd %f0, %f30 fmovd %f0, %f32 fmovd %f0, %f34 fmovd %f0, %f36 fmovd %f0, %f38 fmovd %f0, %f40 fmovd %f0, %f42 fmovd %f0, %f44 fmovd %f0, %f46 fmovd %f0, %f48 fmovd %f0, %f50 fmovd %f0, %f52 fmovd %f0, %f54 fmovd %f0, %f56 fmovd %f0, %f58 fmovd %f0, %f60 fmovd %f0, %f62 ! Signature for extract_loads script to start extracting load values for this stream sethi %hi(0x03deade1), %l6 or %l6, %lo(0x03deade1), %l6 stw %l6, [%i5] ld [%i5], %f16 ! Initialize running integer counter in register %l4 sethi %hi(0x1800001), %l4 or %l4, %lo(0x1800001), %l4 ! Initialize running FP counter in register %f16 sethi %hi(0x41000001), %l6 or %l6, %lo(0x41000001), %l6 stw %l6, [%i5] ld [%i5], %f16 ! Initialize FP counter increment value in register %f17 (constant) sethi %hi(0x35800000), %l6 or %l6, %lo(0x35800000), %l6 stw %l6, [%i5] ld [%i5], %f17 ! Initialize LFSR to 0x6ad6^4 sethi %hi(0x6ad6), %l0 or %l0, %lo(0x6ad6), %l0 mulx %l0, %l0, %l0 mulx %l0, %l0, %l0 BEGIN_NODES3: ! Test instruction sequence for ISTREAM 3 begins P1292: !_MEMBAR (FP) (Loop entry) (Branch target of P1617) sethi %hi(0x2), %l2 or %l2, %lo(0x2), %l2 loop_entry_3_0: membar #StoreLoad ba P1293 nop TARGET1617: ba RET1617 nop P1293: !_BLD [10] (FP) wr %g0, 0xf0, %asi ldda [%i1 + 64] %asi, %f0 membar #Sync ! 1 addresses covered P1294: !_MEMBAR (FP) P1295: !_BSTC [33] (maybe <- 0x41000001) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 0 ] %asi P1296: !_MEMBAR (FP) membar #StoreLoad P1297: !_BLD [28] (FP) (CBR) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1297 nop RET1297: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1298: !_MEMBAR (FP) (Secondary ctx) P1299: !_ST [31] (maybe <- 0x1800001) (Int) (CBR) stw %l4, [%i3 + 192 ] add %l4, 1, %l4 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1299 nop RET1299: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1300: !_LD [12] (Int) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduw [%i2 + 4], %o0 ! move %o0(lower) -> %o0(upper) sllx %o0, 32, %o0 P1301: !_REPLACEMENT [9] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+32], %l7 st %l7, [%i3+32] add %i3, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] P1302: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1302 nop RET1302: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1303: !_BSTC [25] (maybe <- 0x41000002) (FP) (Branch target of P1511) wr %g0, 0xe0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 64 ] %asi ba P1304 nop TARGET1511: ba RET1511 nop P1304: !_MEMBAR (FP) membar #StoreLoad P1305: !_BLD [29] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f2 P1306: !_MEMBAR (FP) P1307: !_PREFETCH [15] (Int) (CBR) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetcha [%i2 + 128] %asi, 1 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1307 nop RET1307: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1308: !_PREFETCH [16] (Int) (Secondary ctx) (Branch target of P1939) wr %g0, 0x81, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetcha [%i3 + 16] %asi, 1 ba P1309 nop TARGET1939: ba RET1939 nop P1309: !_LD [18] (Int) (CBR) lduw [%i3 + 128], %l6 ! move %l6(lower) -> %o0(lower) or %l6, %o0, %o0 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1309 nop RET1309: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1310: !_ST [3] (maybe <- 0x1800002) (Int) (Branch target of P1760) stw %l4, [%i0 + 16 ] add %l4, 1, %l4 ba P1311 nop TARGET1760: ba RET1760 nop P1311: !_LD [12] (Int) (Branch target of P1337) lduw [%i2 + 4], %o1 ! move %o1(lower) -> %o1(upper) sllx %o1, 32, %o1 ba P1312 nop TARGET1337: ba RET1337 nop P1312: !_REPLACEMENT [12] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+4], %l7 st %l7, [%i2+4] add %i2, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] P1313: !_PREFETCH [6] (Int) (CBR) prefetch [%i0 + 96], 1 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1313 nop RET1313: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1314: !_MEMBAR (FP) membar #StoreLoad P1315: !_BLD [20] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 P1316: !_MEMBAR (FP) P1317: !_LD [28] (Int) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduw [%i2 + 0], %l6 ! move %l6(lower) -> %o1(lower) or %l6, %o1, %o1 P1318: !_REPLACEMENT [31] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+192], %l3 st %l3, [%i3+192] add %i3, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] P1319: !_REPLACEMENT [11] (Int) sethi %hi(0x2000), %l6 ld [%i3+0], %o5 st %o5, [%i3+0] add %i3, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] P1320: !_IDC_FLIP [20] (Int) (CBR) (Branch target of P1555) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 IDC_FLIP(1320, 28195, 3, 0x45000100, 0x100, %i2, 0x100, %l6, %l7, %o5, %l3) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1320 nop RET1320: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P1321 nop TARGET1555: ba RET1555 nop P1321: !_REPLACEMENT [12] (Int) sethi %hi(0x2000), %l7 ld [%i3+4], %l3 st %l3, [%i3+4] add %i3, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] P1322: !_REPLACEMENT [6] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(0x2000), %l6 ld [%i3+96], %o5 st %o5, [%i3+96] add %i3, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] P1323: !_LD [24] (FP) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ld [%i3 + 64], %f4 ! 1 addresses covered P1324: !_REPLACEMENT [23] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+32], %l7 st %l7, [%i2+32] add %i2, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] P1325: !_MEMBAR (FP) P1326: !_BST [26] (maybe <- 0x41000004) (FP) (Branch target of P1476) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 128 ] %asi ba P1327 nop TARGET1476: ba RET1476 nop P1327: !_MEMBAR (FP) (Branch target of P1363) membar #StoreLoad ba P1328 nop TARGET1363: ba RET1363 nop P1328: !_LD [5] (Int) lduw [%i0 + 64], %o2 ! move %o2(lower) -> %o2(upper) sllx %o2, 32, %o2 P1329: !_MEMBAR (FP) membar #StoreLoad P1330: !_BLD [17] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f40, %f18 fmovs %f18, %f5 P1331: !_MEMBAR (FP) P1332: !_LD [28] (FP) (CBR) (Nucleus ctx) (Branch target of P1657) wr %g0, 0x4, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lda [%i2 + 0] %asi, %f6 ! 1 addresses covered ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1332 nop RET1332: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P1333 nop TARGET1657: ba RET1657 nop P1333: !_MEMBAR (FP) P1334: !_BST [17] (maybe <- 0x41000006) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f40 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 64 ] %asi P1335: !_MEMBAR (FP) (Branch target of P1404) membar #StoreLoad ba P1336 nop TARGET1404: ba RET1404 nop P1336: !_IDC_FLIP [28] (Int) IDC_FLIP(1336, 9347, 3, 0x46000000, 0x0, %i2, 0x0, %l6, %l7, %o5, %l3) P1337: !_PREFETCH [24] (Int) (CBR) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 64], 1 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1337 nop RET1337: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1338: !_PREFETCH [29] (Int) (Secondary ctx) wr %g0, 0x81, %asi prefetcha [%i2 + 64] %asi, 1 P1339: !_PREFETCH [33] (Int) sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 0], 1 P1340: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1340 nop RET1340: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1341: !_BLD [6] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 fmovd %f40, %f8 P1342: !_MEMBAR (FP) P1343: !_BSTC [23] (maybe <- 0x41000007) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P1344: !_MEMBAR (FP) P1345: !_BST [8] (maybe <- 0x4100000a) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i1 + 0 ] %asi P1346: !_MEMBAR (FP) membar #StoreLoad P1347: !_ST [6] (maybe <- 0x4100000c) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i0 + 96 ] P1348: !_MEMBAR (FP) membar #StoreLoad P1349: !_BLD [21] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f9 fmovs %f19, %f10 fmovd %f40, %f18 fmovs %f18, %f11 P1350: !_MEMBAR (FP) P1351: !_BSTC [14] (maybe <- 0x4100000d) (FP) (Secondary ctx) wr %g0, 0xe1, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 64 ] %asi P1352: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P1353: !_REPLACEMENT [19] (Int) (CBR) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %o5 ld [%i2+0], %l6 st %l6, [%i2+0] add %i2, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1353 nop RET1353: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1354: !_REPLACEMENT [0] (Int) (CBR) sethi %hi(0x2000), %o5 ld [%i2+0], %l6 st %l6, [%i2+0] add %i2, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1354 nop RET1354: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1355: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1355 nop RET1355: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1356: !_BLD [7] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f12 P1357: !_MEMBAR (FP) P1358: !_BLD [14] (FP) (Branch target of P1913) wr %g0, 0xf0, %asi ldda [%i3 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 ba P1359 nop TARGET1913: ba RET1913 nop P1359: !_MEMBAR (FP) P1360: !_PREFETCH [11] (Int) prefetch [%i3 + 0], 1 P1361: !_PREFETCH [21] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetcha [%i3 + 0] %asi, 1 P1362: !_MEMBAR (FP) membar #StoreLoad P1363: !_BLD [29] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f14 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1363 nop RET1363: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1364: !_MEMBAR (FP) P1365: !_REPLACEMENT [11] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l6 ld [%i3+0], %o5 st %o5, [%i3+0] add %i3, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] P1366: !_LD [8] (FP) ld [%i1 + 0], %f15 ! 1 addresses covered !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- P1367: !_PREFETCH [3] (Int) (LE) wr %g0, 0x88, %asi prefetcha [%i0 + 16] %asi, 1 P1368: !_MEMBAR (FP) (CBR) (Branch target of P1601) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1368 nop RET1368: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P1369 nop TARGET1601: ba RET1601 nop P1369: !_BLD [13] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f0 membar #Sync ! 3 addresses covered fmovd %f8, %f2 P1370: !_MEMBAR (FP) (Branch target of P1798) ba P1371 nop TARGET1798: ba RET1798 nop P1371: !_PREFETCH [24] (Int) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 64], 1 P1372: !_ST [28] (maybe <- 0x1800003) (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 stwa %l4, [%i2 + 0] %asi add %l4, 1, %l4 P1373: !_ST [17] (maybe <- 0x4100000e) (FP) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 96 ] P1374: !_MEMBAR (FP) (CBR) (Secondary ctx) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1374 nop RET1374: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1375: !_BLD [21] (FP) (CBR) (Secondary ctx) (Branch target of P1496) wr %g0, 0xf1, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 fmovs %f19, %f4 fmovd %f40, %f18 fmovs %f18, %f5 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1375 nop RET1375: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P1376 nop TARGET1496: ba RET1496 nop P1376: !_MEMBAR (FP) (Secondary ctx) P1377: !_BLD [24] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f6 fmovd %f40, %f18 fmovs %f18, %f7 P1378: !_MEMBAR (FP) P1379: !_BSTC [17] (maybe <- 0x4100000f) (FP) (Branch target of P1355) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f40 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 64 ] %asi ba P1380 nop TARGET1355: ba RET1355 nop P1380: !_MEMBAR (FP) P1381: !_BST [10] (maybe <- 0x41000010) (FP) (Secondary ctx) wr %g0, 0xf1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i1 + 64 ] %asi P1382: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P1383: !_ST [33] (maybe <- 0x41000011) (FP) sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 0 ] P1384: !_MEMBAR (FP) membar #StoreLoad P1385: !_BLD [19] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f8 P1386: !_MEMBAR (FP) P1387: !_BST [3] (maybe <- 0x41000012) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P1388: !_MEMBAR (FP) P1389: !_BSTC [24] (maybe <- 0x41000017) (FP) (CBR) wr %g0, 0xe0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1389 nop RET1389: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1390: !_MEMBAR (FP) membar #StoreLoad P1391: !_BLD [14] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f9 P1392: !_MEMBAR (FP) P1393: !_BLD [6] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f10 fmovd %f40, %f18 fmovs %f18, %f11 P1394: !_MEMBAR (FP) P1395: !_BLD [6] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f12 fmovd %f40, %f18 fmovs %f18, %f13 P1396: !_MEMBAR (FP) P1397: !_BLD [21] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f14 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f40, %f0 P1398: !_MEMBAR (FP) P1399: !_BLD [26] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 fmovd %f40, %f2 P1400: !_MEMBAR (FP) P1401: !_ST [31] (maybe <- 0x41000019) (FP) (CBR) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i3 + 192 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1401 nop RET1401: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1402: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P1403: !_BLD [5] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 fmovd %f40, %f4 P1404: !_MEMBAR (FP) (CBR) (Secondary ctx) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1404 nop RET1404: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1405: !_PREFETCH [19] (Int) (CBR) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 0], 1 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1405 nop RET1405: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1406: !_LD [7] (Int) (CBR) lduw [%i0 + 128], %l3 ! move %l3(lower) -> %o2(lower) or %l3, %o2, %o2 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1406 nop RET1406: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1407: !_MEMBAR (FP) P1408: !_BSTC [17] (maybe <- 0x4100001a) (FP) (CBR) (Branch target of P1480) wr %g0, 0xe0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f40 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1408 nop RET1408: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P1409 nop TARGET1480: ba RET1480 nop P1409: !_MEMBAR (FP) membar #StoreLoad P1410: !_BLD [10] (FP) wr %g0, 0xf0, %asi ldda [%i1 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 P1411: !_MEMBAR (FP) P1412: !_BSTC [33] (maybe <- 0x4100001b) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 0 ] %asi P1413: !_MEMBAR (FP) membar #StoreLoad P1414: !_IDC_FLIP [25] (Int) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 IDC_FLIP(1414, 25865, 3, 0x45800060, 0x60, %i3, 0x60, %l6, %l7, %o5, %l3) P1415: !_ST [19] (maybe <- 0x4100001c) (FP) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 0 ] P1416: !_ST [7] (maybe <- 0x1800004) (Int) stw %l4, [%i0 + 128 ] add %l4, 1, %l4 P1417: !_REPLACEMENT [3] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %o5 ld [%i3+16], %l6 st %l6, [%i3+16] add %i3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] P1418: !_ST [18] (maybe <- 0x4100001d) (FP) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 128 ] P1419: !_LD [13] (Int) (CBR) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lduw [%i3 + 32], %o3 ! move %o3(lower) -> %o3(upper) sllx %o3, 32, %o3 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1419 nop RET1419: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1420: !_REPLACEMENT [4] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+32], %l7 st %l7, [%i2+32] add %i2, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] P1421: !_MEMBAR (FP) membar #StoreLoad P1422: !_BLD [23] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f6 fmovd %f40, %f8 P1423: !_MEMBAR (FP) P1424: !_BLD [23] (FP) (Branch target of P1313) wr %g0, 0xf0, %asi ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f9 fmovs %f19, %f10 fmovd %f40, %f18 fmovs %f18, %f11 ba P1425 nop TARGET1313: ba RET1313 nop P1425: !_MEMBAR (FP) (Branch target of P1436) ba P1426 nop TARGET1436: ba RET1436 nop P1426: !_BSTC [23] (maybe <- 0x4100001e) (FP) (Secondary ctx) wr %g0, 0xe1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P1427: !_MEMBAR (FP) (Secondary ctx) P1428: !_BSTC [3] (maybe <- 0x41000021) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P1429: !_MEMBAR (FP) (Branch target of P1868) membar #StoreLoad ba P1430 nop TARGET1868: ba RET1868 nop P1430: !_LD [17] (Int) (Branch target of P1744) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduw [%i2 + 96], %l7 ! move %l7(lower) -> %o3(lower) or %l7, %o3, %o3 ba P1431 nop TARGET1744: ba RET1744 nop P1431: !_LD [21] (FP) ld [%i3 + 0], %f12 ! 1 addresses covered P1432: !_MEMBAR (FP) membar #StoreLoad P1433: !_BLD [0] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 fmovs %f19, %f14 fmovd %f34, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f36, %f0 fmovd %f40, %f18 fmovs %f18, %f1 P1434: !_MEMBAR (FP) P1435: !_PREFETCH [13] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetcha [%i3 + 32] %asi, 1 P1436: !_LD [16] (Int) (CBR) (Secondary ctx) wr %g0, 0x81, %asi lduwa [%i2 + 16] %asi, %o4 ! move %o4(lower) -> %o4(upper) sllx %o4, 32, %o4 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1436 nop RET1436: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1437: !_LD [1] (FP) (Secondary ctx) wr %g0, 0x81, %asi lda [%i0 + 4] %asi, %f2 ! 1 addresses covered P1438: !_MEMBAR (FP) P1439: !_BSTC [27] (maybe <- 0x41000026) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 128 ] %asi P1440: !_MEMBAR (FP) membar #StoreLoad P1441: !_PREFETCH [23] (Int) (CBR) (Branch target of P1642) prefetch [%i2 + 32], 1 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1441 nop RET1441: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P1442 nop TARGET1642: ba RET1642 nop P1442: !_PREFETCH [2] (Int) prefetch [%i0 + 8], 1 P1443: !_LD [0] (Int) lduw [%i0 + 0], %o5 ! move %o5(lower) -> %o4(lower) or %o5, %o4, %o4 !---- flushing int results buffer---- mov %o0, %l5 mov %o1, %l5 mov %o2, %l5 mov %o3, %l5 mov %o4, %l5 P1444: !_MEMBAR (FP) (Secondary ctx) P1445: !_BSTC [23] (maybe <- 0x41000028) (FP) (Secondary ctx) wr %g0, 0xe1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P1446: !_MEMBAR (FP) (Secondary ctx) P1447: !_BSTC [21] (maybe <- 0x4100002b) (FP) (Secondary ctx) wr %g0, 0xe1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P1448: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P1449: !_BLD [3] (FP) (Branch target of P1639) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 fmovs %f19, %f4 fmovd %f34, %f18 fmovs %f18, %f5 fmovd %f36, %f6 fmovd %f40, %f18 fmovs %f18, %f7 ba P1450 nop TARGET1639: ba RET1639 nop P1450: !_MEMBAR (FP) P1451: !_REPLACEMENT [25] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+96], %l3 st %l3, [%i3+96] add %i3, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] P1452: !_LD [15] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduwa [%i2 + 128] %asi, %o0 ! move %o0(lower) -> %o0(upper) sllx %o0, 32, %o0 P1453: !_REPLACEMENT [20] (Int) (Branch target of P1401) sethi %hi(0x2000), %o5 ld [%i3+256], %l6 st %l6, [%i3+256] add %i3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] ba P1454 nop TARGET1401: ba RET1401 nop P1454: !_LD [2] (Int) lduw [%i0 + 8], %o5 ! move %o5(lower) -> %o0(lower) or %o5, %o0, %o0 P1455: !_REPLACEMENT [6] (Int) sethi %hi(0x2000), %l3 ld [%i3+96], %l7 st %l7, [%i3+96] add %i3, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] P1456: !_MEMBAR (FP) P1457: !_BSTC [24] (maybe <- 0x4100002e) (FP) (Branch target of P1405) wr %g0, 0xe0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 64 ] %asi ba P1458 nop TARGET1405: ba RET1405 nop P1458: !_MEMBAR (FP) P1459: !_BSTC [9] (maybe <- 0x41000030) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i1 + 0 ] %asi P1460: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1460 nop RET1460: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1461: !_REPLACEMENT [18] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l7 ld [%i2+128], %l3 st %l3, [%i2+128] add %i2, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] P1462: !_MEMBAR (FP) P1463: !_BST [19] (maybe <- 0x41000032) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 0 ] %asi P1464: !_MEMBAR (FP) (Branch target of P1827) membar #StoreLoad ba P1465 nop TARGET1827: ba RET1827 nop P1465: !_BLD [23] (FP) (Branch target of P1679) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f8 fmovd %f40, %f10 ba P1466 nop TARGET1679: ba RET1679 nop P1466: !_MEMBAR (FP) (Branch target of P1683) ba P1467 nop TARGET1683: ba RET1683 nop P1467: !_ST [6] (maybe <- 0x1800005) (Int) (Branch target of P1757) stw %l4, [%i0 + 96 ] add %l4, 1, %l4 ba P1468 nop TARGET1757: ba RET1757 nop P1468: !_MEMBAR (FP) membar #StoreLoad P1469: !_BLD [18] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 P1470: !_MEMBAR (FP) P1471: !_REPLACEMENT [28] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %o5 ld [%i2+0], %l6 st %l6, [%i2+0] add %i2, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] P1472: !_ST [18] (maybe <- 0x41000033) (FP) (Secondary ctx) wr %g0, 0x81, %asi ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i3 + 128 ] %asi P1473: !_MEMBAR (FP) (Secondary ctx) (Branch target of P1556) membar #StoreLoad ba P1474 nop TARGET1556: ba RET1556 nop P1474: !_BLD [32] (FP) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f12 P1475: !_MEMBAR (FP) (Secondary ctx) (Branch target of P1577) ba P1476 nop TARGET1577: ba RET1577 nop P1476: !_MEMBAR (Int) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1476 nop RET1476: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1477: !_BLD [12] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 fmovs %f19, %f14 fmovd %f40, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- P1478: !_MEMBAR (FP) P1479: !_BLD [29] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 64] %asi, %f0 membar #Sync ! 1 addresses covered P1480: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1480 nop RET1480: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1481: !_BSTC [10] (maybe <- 0x41000034) (FP) (Secondary ctx) wr %g0, 0xe1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i1 + 64 ] %asi P1482: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P1483: !_REPLACEMENT [9] (Int) (Nucleus ctx) (Branch target of P1622) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+32], %l3 st %l3, [%i3+32] add %i3, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] ba P1484 nop TARGET1622: ba RET1622 nop P1484: !_REPLACEMENT [20] (Int) sethi %hi(0x2000), %l6 ld [%i3+256], %o5 st %o5, [%i3+256] add %i3, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] P1485: !_ST [21] (maybe <- 0x41000035) (FP) (CBR) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i2 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1485 nop RET1485: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1486: !_REPLACEMENT [21] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(0x2000), %l3 ld [%i3+0], %l7 st %l7, [%i3+0] add %i3, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] P1487: !_PREFETCH [8] (Int) (Branch target of P1502) prefetch [%i1 + 0], 1 ba P1488 nop TARGET1502: ba RET1502 nop P1488: !_REPLACEMENT [25] (Int) sethi %hi(0x2000), %o5 ld [%i3+96], %l6 st %l6, [%i3+96] add %i3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] P1489: !_REPLACEMENT [24] (Int) sethi %hi(0x2000), %l7 ld [%i3+64], %l3 st %l3, [%i3+64] add %i3, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] P1490: !_PREFETCH [33] (Int) sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 0], 1 P1491: !_REPLACEMENT [4] (Int) (CBR) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l6 ld [%i2+32], %o5 st %o5, [%i2+32] add %i2, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1491 nop RET1491: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1492: !_LD [8] (Int) lduw [%i1 + 0], %o1 ! move %o1(lower) -> %o1(upper) sllx %o1, 32, %o1 P1493: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1493 nop RET1493: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1494: !_BLD [26] (FP) (Branch target of P1719) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 fmovd %f40, %f2 ba P1495 nop TARGET1719: ba RET1719 nop P1495: !_MEMBAR (FP) (Branch target of P1368) ba P1496 nop TARGET1368: ba RET1368 nop P1496: !_ST [15] (maybe <- 0x41000036) (FP) (CBR) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 128 ] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1496 nop RET1496: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1497: !_REPLACEMENT [14] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+64], %l7 st %l7, [%i3+64] add %i3, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] P1498: !_MEMBAR (FP) P1499: !_BST [12] (maybe <- 0x41000037) (FP) (Branch target of P1799) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi ba P1500 nop TARGET1799: ba RET1799 nop P1500: !_MEMBAR (FP) membar #StoreLoad P1501: !_BLD [11] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 fmovs %f19, %f4 fmovd %f40, %f18 fmovs %f18, %f5 P1502: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1502 nop RET1502: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1503: !_LD [3] (FP) ld [%i0 + 16], %f6 ! 1 addresses covered P1504: !_REPLACEMENT [30] (Int) sethi %hi(0x2000), %o5 ld [%i3+128], %l6 st %l6, [%i3+128] add %i3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] P1505: !_REPLACEMENT [19] (Int) (Branch target of P1375) sethi %hi(0x2000), %l7 ld [%i3+0], %l3 st %l3, [%i3+0] add %i3, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] ba P1506 nop TARGET1375: ba RET1375 nop P1506: !_REPLACEMENT [17] (Int) sethi %hi(0x2000), %l6 ld [%i3+96], %o5 st %o5, [%i3+96] add %i3, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] P1507: !_PREFETCH [26] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetcha [%i2 + 128] %asi, 1 P1508: !_MEMBAR (FP) P1509: !_BST [2] (maybe <- 0x4100003a) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P1510: !_MEMBAR (FP) membar #StoreLoad P1511: !_ST [2] (maybe <- 0x4100003f) (FP) (CBR) (Branch target of P1493) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i0 + 8 ] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1511 nop RET1511: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P1512 nop TARGET1493: ba RET1493 nop P1512: !_ST [30] (maybe <- 0x41000040) (FP) (CBR) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 128 ] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1512 nop RET1512: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1513: !_MEMBAR (FP) P1514: !_BST [1] (maybe <- 0x41000041) (FP) (Branch target of P1873) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi ba P1515 nop TARGET1873: ba RET1873 nop P1515: !_MEMBAR (FP) membar #StoreLoad P1516: !_BLD [19] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 P1517: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1517 nop RET1517: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1518: !_BST [4] (maybe <- 0x41000046) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P1519: !_MEMBAR (FP) (Branch target of P1660) membar #StoreLoad ba P1520 nop TARGET1660: ba RET1660 nop P1520: !_ST [14] (maybe <- 0x4100004b) (FP) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 64 ] P1521: !_PREFETCH [14] (Int) prefetch [%i3 + 64], 1 P1522: !_LD [23] (FP) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ld [%i2 + 32], %f8 ! 1 addresses covered P1523: !_PREFETCH [13] (Int) (Nucleus ctx) wr %g0, 0x4, %asi prefetcha [%i3 + 32] %asi, 1 P1524: !_REPLACEMENT [22] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l6 ld [%i3+4], %o5 st %o5, [%i3+4] add %i3, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] P1525: !_MEMBAR (FP) P1526: !_BSTC [10] (maybe <- 0x4100004c) (FP) (Branch target of P1763) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i1 + 64 ] %asi ba P1527 nop TARGET1763: ba RET1763 nop P1527: !_MEMBAR (FP) membar #StoreLoad P1528: !_PREFETCH [24] (Int) (Branch target of P1581) prefetch [%i2 + 64], 1 ba P1529 nop TARGET1581: ba RET1581 nop P1529: !_MEMBAR (FP) (Branch target of P1701) membar #StoreLoad ba P1530 nop TARGET1701: ba RET1701 nop P1530: !_BLD [8] (FP) wr %g0, 0xf0, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f9 fmovd %f40, %f10 P1531: !_MEMBAR (FP) P1532: !_REPLACEMENT [23] (Int) sethi %hi(0x2000), %o5 ld [%i3+32], %l6 st %l6, [%i3+32] add %i3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] P1533: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1533 nop RET1533: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1534: !_BSTC [2] (maybe <- 0x4100004d) (FP) (Branch target of P1854) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi ba P1535 nop TARGET1854: ba RET1854 nop P1535: !_MEMBAR (FP) membar #StoreLoad P1536: !_BLD [6] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 fmovd %f40, %f12 P1537: !_MEMBAR (FP) P1538: !_BSTC [3] (maybe <- 0x41000052) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P1539: !_MEMBAR (FP) membar #StoreLoad P1540: !_ST [14] (maybe <- 0x1800006) (Int) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 stw %l4, [%i2 + 64 ] add %l4, 1, %l4 P1541: !_ST [5] (maybe <- 0x41000057) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i0 + 64 ] P1542: !_MEMBAR (FP) membar #StoreLoad P1543: !_BLD [21] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 fmovs %f19, %f14 fmovd %f40, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1543 nop RET1543: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1544: !_MEMBAR (FP) P1545: !_IDC_FLIP [20] (Int) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 IDC_FLIP(1545, 22276, 3, 0x45000100, 0x100, %i2, 0x100, %l6, %l7, %o5, %l3) P1546: !_MEMBAR (FP) P1547: !_BST [23] (maybe <- 0x41000058) (FP) (CBR) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1547 nop RET1547: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1548: !_MEMBAR (FP) membar #StoreLoad P1549: !_LD [28] (FP) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ld [%i3 + 0], %f0 ! 1 addresses covered P1550: !_REPLACEMENT [5] (Int) (Secondary ctx) (Branch target of P1406) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l6 ld [%i2+64], %o5 st %o5, [%i2+64] add %i2, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] ba P1551 nop TARGET1406: ba RET1406 nop P1551: !_PREFETCH [14] (Int) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 64], 1 P1552: !_MEMBAR (FP) P1553: !_BSTC [23] (maybe <- 0x4100005b) (FP) (Branch target of P1778) wr %g0, 0xe0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi ba P1554 nop TARGET1778: ba RET1778 nop P1554: !_MEMBAR (FP) membar #StoreLoad P1555: !_PREFETCH [27] (Int) (CBR) prefetch [%i2 + 160], 1 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1555 nop RET1555: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1556: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1556 nop RET1556: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1557: !_BLD [30] (FP) (CBR) (Branch target of P1302) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1557 nop RET1557: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P1558 nop TARGET1302: ba RET1302 nop P1558: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1558 nop RET1558: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1559: !_BLD [5] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f2 fmovd %f40, %f18 fmovs %f18, %f3 P1560: !_MEMBAR (FP) P1561: !_REPLACEMENT [9] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %o5 ld [%i2+32], %l6 st %l6, [%i2+32] add %i2, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] P1562: !_LD [28] (FP) (Secondary ctx) wr %g0, 0x81, %asi lda [%i3 + 0] %asi, %f4 ! 1 addresses covered P1563: !_MEMBAR (FP) membar #StoreLoad P1564: !_BLD [18] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 P1565: !_MEMBAR (FP) P1566: !_BLD [16] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f36, %f6 P1567: !_MEMBAR (FP) P1568: !_LD [13] (FP) (Branch target of P1703) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ld [%i2 + 32], %f7 ! 1 addresses covered ba P1569 nop TARGET1703: ba RET1703 nop P1569: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1569 nop RET1569: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1570: !_BSTC [6] (maybe <- 0x4100005e) (FP) (Branch target of P1340) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 64 ] %asi ba P1571 nop TARGET1340: ba RET1340 nop P1571: !_MEMBAR (FP) membar #StoreLoad P1572: !_REPLACEMENT [31] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+192], %l3 st %l3, [%i3+192] add %i3, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] P1573: !_MEMBAR (FP) membar #StoreLoad P1574: !_BLD [5] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f8 fmovd %f40, %f18 fmovs %f18, %f9 P1575: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1575 nop RET1575: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1576: !_PREFETCH [19] (Int) (Nucleus ctx) (Branch target of P1826) wr %g0, 0x4, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetcha [%i2 + 0] %asi, 1 ba P1577 nop TARGET1826: ba RET1826 nop P1577: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1577 nop RET1577: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1578: !_BST [21] (maybe <- 0x41000060) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P1579: !_MEMBAR (FP) membar #StoreLoad P1580: !_IDC_FLIP [13] (Int) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 IDC_FLIP(1580, 28407, 3, 0x44000020, 0x20, %i2, 0x20, %l6, %l7, %o5, %l3) P1581: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1581 nop RET1581: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1582: !_BSTC [16] (maybe <- 0x41000063) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f36 membar #Sync stda %f32, [%i3 + 0 ] %asi P1583: !_MEMBAR (FP) membar #StoreLoad P1584: !_ST [13] (maybe <- 0x41000064) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 32 ] P1585: !_MEMBAR (FP) membar #StoreLoad P1586: !_BLD [21] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f10 fmovd %f40, %f12 P1587: !_MEMBAR (FP) P1588: !_BSTC [29] (maybe <- 0x41000065) (FP) (CBR) (Branch target of P1543) wr %g0, 0xe0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1588 nop RET1588: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 ba P1589 nop TARGET1543: ba RET1543 nop P1589: !_MEMBAR (FP) membar #StoreLoad P1590: !_IDC_FLIP [15] (Int) (CBR) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 IDC_FLIP(1590, 16772, 3, 0x44000080, 0x80, %i2, 0x80, %l6, %l7, %o5, %l3) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1590 nop RET1590: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1591: !_MEMBAR (FP) (Secondary ctx) (Branch target of P1766) ba P1592 nop TARGET1766: ba RET1766 nop P1592: !_BSTC [33] (maybe <- 0x41000066) (FP) (Secondary ctx) wr %g0, 0xe1, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 0 ] %asi P1593: !_MEMBAR (FP) (Secondary ctx) (Branch target of P1569) ba P1594 nop TARGET1569: ba RET1569 nop P1594: !_BST [25] (maybe <- 0x41000067) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 64 ] %asi P1595: !_MEMBAR (FP) membar #StoreLoad P1596: !_LD [30] (FP) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ld [%i3 + 128], %f13 ! 1 addresses covered P1597: !_LD [26] (FP) (Secondary ctx) wr %g0, 0x81, %asi lda [%i2 + 128] %asi, %f14 ! 1 addresses covered P1598: !_ST [1] (maybe <- 0x41000069) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i0 + 4 ] P1599: !_LD [31] (Int) (Branch target of P1533) lduw [%i3 + 192], %l3 ! move %l3(lower) -> %o1(lower) or %l3, %o1, %o1 ba P1600 nop TARGET1533: ba RET1533 nop P1600: !_MEMBAR (FP) membar #StoreLoad P1601: !_BLD [12] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovs %f19, %f0 fmovd %f40, %f18 fmovs %f18, %f1 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1601 nop RET1601: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1602: !_MEMBAR (FP) P1603: !_REPLACEMENT [33] (Int) (Nucleus ctx) (Branch target of P1558) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+0], %l3 st %l3, [%i3+0] add %i3, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] ba P1604 nop TARGET1558: ba RET1558 nop P1604: !_PREFETCH [12] (Int) prefetch [%i2 + 4], 1 P1605: !_MEMBAR (FP) P1606: !_BST [18] (maybe <- 0x4100006a) (FP) (Branch target of P1309) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 128 ] %asi ba P1607 nop TARGET1309: ba RET1309 nop P1607: !_MEMBAR (FP) membar #StoreLoad P1608: !_BLD [7] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f2 P1609: !_MEMBAR (FP) P1610: !_BSTC [2] (maybe <- 0x4100006b) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P1611: !_MEMBAR (FP) membar #StoreLoad P1612: !_REPLACEMENT [11] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(0x2000), %o5 ld [%i3+0], %l6 st %l6, [%i3+0] add %i3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] P1613: !_REPLACEMENT [5] (Int) sethi %hi(0x2000), %l7 ld [%i3+64], %l3 st %l3, [%i3+64] add %i3, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] P1614: !_PREFETCH [4] (Int) (Nucleus ctx) wr %g0, 0x4, %asi prefetcha [%i0 + 32] %asi, 1 P1615: !_ST [22] (maybe <- 0x1800007) (Int) (Branch target of P1649) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stw %l4, [%i3 + 4 ] add %l4, 1, %l4 ba P1616 nop TARGET1649: ba RET1649 nop P1616: !_REPLACEMENT [5] (Int) (CBR) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+64], %l7 st %l7, [%i2+64] add %i2, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1616 nop RET1616: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1617: !_MEMBAR (FP) (CBR) (Secondary ctx) (Branch target of P1419) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1617 nop RET1617: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P1618 nop TARGET1419: ba RET1419 nop P1618: !_BSTC [5] (maybe <- 0x41000070) (FP) (CBR) (Secondary ctx) wr %g0, 0xe1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1618 nop RET1618: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1619: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P1620: !_ST [26] (maybe <- 0x41000072) (FP) (CBR) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 128 ] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1620 nop RET1620: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1621: !_ST [30] (maybe <- 0x1800008) (Int) (CBR) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stw %l4, [%i3 + 128 ] add %l4, 1, %l4 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1621 nop RET1621: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1622: !_ST [6] (maybe <- 0x1800009) (Int) (CBR) stw %l4, [%i0 + 96 ] add %l4, 1, %l4 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1622 nop RET1622: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1623: !_LD [31] (FP) (Branch target of P1624) ld [%i3 + 192], %f3 ! 1 addresses covered ba P1624 nop TARGET1624: ba RET1624 nop P1624: !_MEMBAR (FP) (CBR) (Branch target of P1916) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1624 nop RET1624: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P1625 nop TARGET1916: ba RET1916 nop P1625: !_BST [5] (maybe <- 0x41000073) (FP) (Branch target of P1907) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 64 ] %asi ba P1626 nop TARGET1907: ba RET1907 nop P1626: !_MEMBAR (FP) membar #StoreLoad P1627: !_LD [11] (FP) (CBR) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lda [%i2 + 0] %asi, %f4 ! 1 addresses covered ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1627 nop RET1627: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1628: !_MEMBAR (FP) (Secondary ctx) P1629: !_BSTC [20] (maybe <- 0x41000075) (FP) (Secondary ctx) wr %g0, 0xe1, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 256 ] %asi P1630: !_MEMBAR (FP) (CBR) (Secondary ctx) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1630 nop RET1630: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1631: !_BST [18] (maybe <- 0x41000076) (FP) (Branch target of P1860) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 128 ] %asi ba P1632 nop TARGET1860: ba RET1860 nop P1632: !_MEMBAR (FP) P1633: !_BST [13] (maybe <- 0x41000077) (FP) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P1634: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P1635: !_BLD [12] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 fmovs %f19, %f6 fmovd %f40, %f18 fmovs %f18, %f7 P1636: !_MEMBAR (FP) P1637: !_PREFETCH [29] (Int) (CBR) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 64], 1 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1637 nop RET1637: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1638: !_MEMBAR (FP) membar #StoreLoad P1639: !_BLD [11] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f8 fmovd %f40, %f10 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1639 nop RET1639: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1640: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1640 nop RET1640: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1641: !_ST [10] (maybe <- 0x180000a) (Int) (Secondary ctx) wr %g0, 0x81, %asi stwa %l4, [%i1 + 64] %asi add %l4, 1, %l4 P1642: !_LD [10] (Int) (CBR) lduw [%i1 + 64], %o2 ! move %o2(lower) -> %o2(upper) sllx %o2, 32, %o2 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1642 nop RET1642: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1643: !_ST [16] (maybe <- 0x4100007a) (FP) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 16 ] P1644: !_LD [26] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduwa [%i2 + 128] %asi, %l6 ! move %l6(lower) -> %o2(lower) or %l6, %o2, %o2 P1645: !_MEMBAR (FP) membar #StoreLoad P1646: !_BLD [29] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 P1647: !_MEMBAR (FP) P1648: !_ST [24] (maybe <- 0x4100007b) (FP) (Branch target of P1620) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 64 ] ba P1649 nop TARGET1620: ba RET1620 nop P1649: !_ST [9] (maybe <- 0x180000b) (Int) (CBR) (Branch target of P1621) stw %l4, [%i1 + 32 ] add %l4, 1, %l4 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1649 nop RET1649: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P1650 nop TARGET1621: ba RET1621 nop P1650: !_ST [28] (maybe <- 0x4100007c) (FP) (Branch target of P1588) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 0 ] ba P1651 nop TARGET1588: ba RET1588 nop P1651: !_MEMBAR (FP) (Secondary ctx) (Branch target of P1692) ba P1652 nop TARGET1692: ba RET1692 nop P1652: !_BSTC [21] (maybe <- 0x4100007d) (FP) (Secondary ctx) wr %g0, 0xe1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P1653: !_MEMBAR (FP) (Secondary ctx) (Branch target of P1859) membar #StoreLoad ba P1654 nop TARGET1859: ba RET1859 nop P1654: !_BLD [1] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f12 fmovd %f34, %f14 fmovd %f36, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f40, %f0 P1655: !_MEMBAR (FP) (Secondary ctx) (Branch target of P1726) ba P1656 nop TARGET1726: ba RET1726 nop P1656: !_BSTC [32] (maybe <- 0x41000080) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 256 ] %asi P1657: !_MEMBAR (FP) (CBR) (Branch target of P1743) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1657 nop RET1657: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P1658 nop TARGET1743: ba RET1743 nop P1658: !_IDC_FLIP [16] (Int) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 IDC_FLIP(1658, 24294, 3, 0x44800010, 0x10, %i2, 0x10, %l6, %l7, %o5, %l3) P1659: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P1660: !_BLD [1] (FP) (CBR) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 fmovs %f19, %f2 fmovd %f34, %f18 fmovs %f18, %f3 fmovd %f36, %f4 fmovd %f40, %f18 fmovs %f18, %f5 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1660 nop RET1660: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1661: !_MEMBAR (FP) (Secondary ctx) P1662: !_BLD [22] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f6 fmovd %f40, %f8 P1663: !_MEMBAR (FP) P1664: !_ST [4] (maybe <- 0x41000081) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i0 + 32 ] P1665: !_IDC_FLIP [8] (Int) IDC_FLIP(1665, 16893, 3, 0x43800000, 0x0, %i1, 0x0, %l6, %l7, %o5, %l3) P1666: !_MEMBAR (FP) (Branch target of P1618) ba P1667 nop TARGET1618: ba RET1618 nop P1667: !_BSTC [29] (maybe <- 0x41000082) (FP) (CBR) wr %g0, 0xe0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1667 nop RET1667: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1668: !_MEMBAR (FP) (Branch target of P1677) membar #StoreLoad ba P1669 nop TARGET1677: ba RET1677 nop P1669: !_BLD [33] (FP) (Branch target of P1930) wr %g0, 0xf0, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f9 ba P1670 nop TARGET1930: ba RET1930 nop P1670: !_MEMBAR (FP) P1671: !_BLD [2] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f10 fmovd %f34, %f12 fmovd %f36, %f18 fmovs %f18, %f13 fmovd %f40, %f14 P1672: !_MEMBAR (FP) P1673: !_ST [9] (maybe <- 0x41000083) (FP) (Branch target of P1781) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i1 + 32 ] ba P1674 nop TARGET1781: ba RET1781 nop P1674: !_MEMBAR (FP) P1675: !_BSTC [20] (maybe <- 0x41000084) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 256 ] %asi P1676: !_MEMBAR (FP) membar #StoreLoad P1677: !_BLD [32] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1677 nop RET1677: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1678: !_MEMBAR (FP) (Branch target of P1353) ba P1679 nop TARGET1353: ba RET1353 nop P1679: !_BSTC [30] (maybe <- 0x41000085) (FP) (CBR) (Secondary ctx) wr %g0, 0xe1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 128 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1679 nop RET1679: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1680: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P1681: !_ST [4] (maybe <- 0x180000c) (Int) (Branch target of P1575) stw %l4, [%i0 + 32 ] add %l4, 1, %l4 ba P1682 nop TARGET1575: ba RET1575 nop P1682: !_MEMBAR (FP) P1683: !_BSTC [24] (maybe <- 0x41000086) (FP) (CBR) wr %g0, 0xe0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1683 nop RET1683: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1684: !_MEMBAR (FP) P1685: !_BST [31] (maybe <- 0x41000088) (FP) (Branch target of P1590) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 192 ] %asi ba P1686 nop TARGET1590: ba RET1590 nop P1686: !_MEMBAR (FP) membar #StoreLoad P1687: !_BLD [0] (FP) (Branch target of P1374) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f0 membar #Sync ! 5 addresses covered fmovs %f4, %f3 fmovd %f8, %f4 ba P1688 nop TARGET1374: ba RET1374 nop P1688: !_MEMBAR (FP) P1689: !_LD [14] (FP) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lda [%i3 + 64] %asi, %f5 ! 1 addresses covered P1690: !_MEMBAR (FP) (CBR) (Secondary ctx) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1690 nop RET1690: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1691: !_BST [33] (maybe <- 0x41000089) (FP) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 0 ] %asi P1692: !_MEMBAR (FP) (CBR) (Secondary ctx) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1692 nop RET1692: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1693: !_LD [5] (Int) (CBR) lduw [%i0 + 64], %o3 ! move %o3(lower) -> %o3(upper) sllx %o3, 32, %o3 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1693 nop RET1693: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1694: !_MEMBAR (FP) (Branch target of P1627) ba P1695 nop TARGET1627: ba RET1627 nop P1695: !_BST [24] (maybe <- 0x4100008a) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 64 ] %asi P1696: !_MEMBAR (FP) P1697: !_BSTC [11] (maybe <- 0x4100008c) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P1698: !_MEMBAR (FP) membar #StoreLoad P1699: !_LD [13] (FP) (CBR) ld [%i2 + 32], %f6 ! 1 addresses covered ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1699 nop RET1699: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1700: !_MEMBAR (FP) (Branch target of P1879) membar #StoreLoad ba P1701 nop TARGET1879: ba RET1879 nop P1701: !_BLD [15] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i2 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1701 nop RET1701: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1702: !_MEMBAR (FP) P1703: !_BSTC [13] (maybe <- 0x4100008f) (FP) (CBR) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1703 nop RET1703: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1704: !_MEMBAR (FP) membar #StoreLoad P1705: !_LD [14] (FP) (Secondary ctx) wr %g0, 0x81, %asi lda [%i2 + 64] %asi, %f8 ! 1 addresses covered P1706: !_MEMBAR (FP) membar #StoreLoad P1707: !_BLD [5] (FP) (Branch target of P1640) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f9 fmovd %f40, %f10 ba P1708 nop TARGET1640: ba RET1640 nop P1708: !_MEMBAR (FP) (CBR) (Branch target of P1667) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1708 nop RET1708: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P1709 nop TARGET1667: ba RET1667 nop P1709: !_BLD [0] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 fmovs %f19, %f12 fmovd %f34, %f18 fmovs %f18, %f13 fmovd %f36, %f14 fmovd %f40, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- P1710: !_MEMBAR (FP) P1711: !_BLD [18] (FP) (Branch target of P1883) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f0 membar #Sync ! 1 addresses covered ba P1712 nop TARGET1883: ba RET1883 nop P1712: !_MEMBAR (FP) P1713: !_BLD [26] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 fmovd %f40, %f2 P1714: !_MEMBAR (FP) (Branch target of P1630) ba P1715 nop TARGET1630: ba RET1630 nop P1715: !_BLD [29] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 P1716: !_MEMBAR (FP) P1717: !_LD [5] (FP) ld [%i0 + 64], %f4 ! 1 addresses covered P1718: !_MEMBAR (FP) (Secondary ctx) P1719: !_BST [23] (maybe <- 0x41000092) (FP) (CBR) (Secondary ctx) (Branch target of P1690) wr %g0, 0xf1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1719 nop RET1719: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P1720 nop TARGET1690: ba RET1690 nop P1720: !_MEMBAR (FP) (Secondary ctx) (Branch target of P1746) membar #StoreLoad ba P1721 nop TARGET1746: ba RET1746 nop P1721: !_BLD [5] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 fmovd %f40, %f6 P1722: !_MEMBAR (FP) (Secondary ctx) P1723: !_REPLACEMENT [20] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %o5 ld [%i2+256], %l6 st %l6, [%i2+256] add %i2, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] P1724: !_MEMBAR (FP) P1725: !_BSTC [13] (maybe <- 0x41000095) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P1726: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1726 nop RET1726: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1727: !_PREFETCH [22] (Int) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 4], 1 P1728: !_LD [7] (FP) (CBR) (Branch target of P1307) ld [%i0 + 128], %f7 ! 1 addresses covered ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1728 nop RET1728: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P1729 nop TARGET1307: ba RET1307 nop P1729: !_MEMBAR (FP) (Branch target of P1354) membar #StoreLoad ba P1730 nop TARGET1354: ba RET1354 nop P1730: !_BLD [26] (FP) (Branch target of P1485) wr %g0, 0xf0, %asi ldda [%i2 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f8 fmovd %f40, %f18 fmovs %f18, %f9 ba P1731 nop TARGET1485: ba RET1485 nop P1731: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1731 nop RET1731: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1732: !_BSTC [24] (maybe <- 0x41000098) (FP) (Secondary ctx) wr %g0, 0xe1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 64 ] %asi P1733: !_MEMBAR (FP) (Secondary ctx) (Branch target of P1332) membar #StoreLoad ba P1734 nop TARGET1332: ba RET1332 nop P1734: !_BLD [3] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f10 fmovd %f34, %f12 fmovd %f36, %f18 fmovs %f18, %f13 fmovd %f40, %f14 P1735: !_MEMBAR (FP) P1736: !_PREFETCH [15] (Int) prefetch [%i3 + 128], 1 P1737: !_MEMBAR (FP) (Secondary ctx) (Branch target of P1299) ba P1738 nop TARGET1299: ba RET1299 nop P1738: !_BST [20] (maybe <- 0x4100009a) (FP) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 256 ] %asi P1739: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P1740: !_REPLACEMENT [4] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l7 ld [%i2+32], %l3 st %l3, [%i2+32] add %i2, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] P1741: !_IDC_FLIP [12] (Int) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 IDC_FLIP(1741, 12674, 3, 0x44000004, 0x4, %i3, 0x4, %l6, %l7, %o5, %l3) P1742: !_REPLACEMENT [31] (Int) sethi %hi(0x2000), %l6 ld [%i2+192], %o5 st %o5, [%i2+192] add %i2, %l6, %l7 ld [%l7+192], %o5 st %o5, [%l7+192] add %l7, %l6, %l7 ld [%l7+192], %o5 st %o5, [%l7+192] add %l7, %l6, %l7 ld [%l7+192], %o5 st %o5, [%l7+192] add %l7, %l6, %l7 ld [%l7+192], %o5 st %o5, [%l7+192] add %l7, %l6, %l7 ld [%l7+192], %o5 st %o5, [%l7+192] add %l7, %l6, %l7 ld [%l7+192], %o5 st %o5, [%l7+192] add %l7, %l6, %l7 ld [%l7+192], %o5 st %o5, [%l7+192] P1743: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1743 nop RET1743: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1744: !_BST [23] (maybe <- 0x4100009b) (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1744 nop RET1744: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1745: !_MEMBAR (FP) (Branch target of P1903) membar #StoreLoad ba P1746 nop TARGET1903: ba RET1903 nop P1746: !_BLD [1] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovs %f19, %f0 fmovd %f34, %f18 fmovs %f18, %f1 fmovd %f36, %f2 fmovd %f40, %f18 fmovs %f18, %f3 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1746 nop RET1746: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1747: !_MEMBAR (FP) P1748: !_REPLACEMENT [25] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+96], %l3 st %l3, [%i3+96] add %i3, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] P1749: !_MEMBAR (FP) membar #StoreLoad P1750: !_BLD [29] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f4 P1751: !_MEMBAR (FP) P1752: !_REPLACEMENT [14] (Int) sethi %hi(0x2000), %l6 ld [%i3+64], %o5 st %o5, [%i3+64] add %i3, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] P1753: !_ST [3] (maybe <- 0x180000d) (Int) stw %l4, [%i0 + 16 ] add %l4, 1, %l4 P1754: !_MEMBAR (FP) P1755: !_BST [23] (maybe <- 0x4100009e) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P1756: !_MEMBAR (FP) (CBR) (Branch target of P1835) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1756 nop RET1756: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P1757 nop TARGET1835: ba RET1835 nop P1757: !_REPLACEMENT [14] (Int) (CBR) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %o5 ld [%i2+64], %l6 st %l6, [%i2+64] add %i2, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1757 nop RET1757: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1758: !_MEMBAR (FP) P1759: !_BSTC [14] (maybe <- 0x410000a1) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 64 ] %asi P1760: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1760 nop RET1760: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1761: !_BST [32] (maybe <- 0x410000a2) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 256 ] %asi P1762: !_MEMBAR (FP) membar #StoreLoad P1763: !_BLD [18] (FP) (CBR) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1763 nop RET1763: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1764: !_MEMBAR (FP) (Secondary ctx) P1765: !_PREFETCH [9] (Int) (CBR) (Nucleus ctx) wr %g0, 0x4, %asi prefetcha [%i1 + 32] %asi, 1 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1765 nop RET1765: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1766: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1766 nop RET1766: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1767: !_BLD [22] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f6 fmovd %f40, %f8 P1768: !_MEMBAR (FP) P1769: !_LD [12] (FP) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ld [%i3 + 4], %f9 ! 1 addresses covered P1770: !_REPLACEMENT [1] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l6 ld [%i2+4], %o5 st %o5, [%i2+4] add %i2, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] add %l7, %l6, %l7 ld [%l7+4], %o5 st %o5, [%l7+4] P1771: !_MEMBAR (FP) P1772: !_BSTC [30] (maybe <- 0x410000a3) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 128 ] %asi P1773: !_MEMBAR (FP) membar #StoreLoad P1774: !_LD [9] (FP) ld [%i1 + 32], %f10 ! 1 addresses covered P1775: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P1776: !_BLD [33] (FP) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 P1777: !_MEMBAR (FP) (Secondary ctx) P1778: !_BST [22] (maybe <- 0x410000a4) (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1778 nop RET1778: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1779: !_MEMBAR (FP) membar #StoreLoad P1780: !_PREFETCH [13] (Int) (LE) wr %g0, 0x88, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetcha [%i2 + 32] %asi, 1 P1781: !_ST [6] (maybe <- 0x410000a7) (FP) (CBR) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i0 + 96 ] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1781 nop RET1781: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1782: !_LD [4] (Int) (Branch target of P1512) lduw [%i0 + 32], %l3 ! move %l3(lower) -> %o3(lower) or %l3, %o3, %o3 ba P1783 nop TARGET1512: ba RET1512 nop P1783: !_MEMBAR (FP) (Branch target of P1856) membar #StoreLoad ba P1784 nop TARGET1856: ba RET1856 nop P1784: !_BLD [3] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f12 fmovd %f34, %f14 fmovd %f36, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f40, %f0 P1785: !_MEMBAR (FP) P1786: !_BST [8] (maybe <- 0x410000a8) (FP) (Branch target of P1765) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i1 + 0 ] %asi ba P1787 nop TARGET1765: ba RET1765 nop P1787: !_MEMBAR (FP) membar #StoreLoad P1788: !_PREFETCH [15] (Int) (Branch target of P1557) prefetch [%i2 + 128], 1 ba P1789 nop TARGET1557: ba RET1557 nop P1789: !_MEMBAR (FP) membar #StoreLoad P1790: !_BLD [13] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 fmovs %f19, %f2 fmovd %f40, %f18 fmovs %f18, %f3 P1791: !_MEMBAR (FP) P1792: !_PREFETCH [10] (Int) (CBR) (Branch target of P1756) prefetch [%i1 + 64], 1 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1792 nop RET1792: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P1793 nop TARGET1756: ba RET1756 nop P1793: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P1794: !_BLD [9] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f4 fmovd %f40, %f18 fmovs %f18, %f5 P1795: !_MEMBAR (FP) (Secondary ctx) P1796: !_REPLACEMENT [28] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l6 ld [%i3+0], %o5 st %o5, [%i3+0] add %i3, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] P1797: !_MEMBAR (FP) (Branch target of P1731) ba P1798 nop TARGET1731: ba RET1731 nop P1798: !_BSTC [23] (maybe <- 0x410000aa) (FP) (CBR) (Branch target of P1904) wr %g0, 0xe0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1798 nop RET1798: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 ba P1799 nop TARGET1904: ba RET1904 nop P1799: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1799 nop RET1799: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1800: !_ST [0] (maybe <- 0x180000e) (Int) stw %l4, [%i0 + 0 ] add %l4, 1, %l4 P1801: !_MEMBAR (FP) membar #StoreLoad P1802: !_BLD [11] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f6 fmovd %f40, %f8 P1803: !_MEMBAR (FP) (Branch target of P1792) ba P1804 nop TARGET1792: ba RET1792 nop P1804: !_PREFETCH [16] (Int) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 16], 1 P1805: !_REPLACEMENT [15] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+128], %l7 st %l7, [%i3+128] add %i3, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] P1806: !_LD [8] (Int) (Branch target of P1893) lduw [%i1 + 0], %o4 ! move %o4(lower) -> %o4(upper) sllx %o4, 32, %o4 ba P1807 nop TARGET1893: ba RET1893 nop P1807: !_PREFETCH [6] (Int) prefetch [%i0 + 96], 1 P1808: !_MEMBAR (FP) membar #StoreLoad P1809: !_BLD [17] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f40, %f18 fmovs %f18, %f9 P1810: !_MEMBAR (FP) P1811: !_BLD [26] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f10 fmovd %f40, %f18 fmovs %f18, %f11 P1812: !_MEMBAR (FP) P1813: !_ST [10] (maybe <- 0x180000f) (Int) stw %l4, [%i1 + 64 ] add %l4, 1, %l4 P1814: !_REPLACEMENT [30] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(0x2000), %l3 ld [%i3+128], %l7 st %l7, [%i3+128] add %i3, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] P1815: !_PREFETCH [17] (Int) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 96], 1 P1816: !_MEMBAR (FP) P1817: !_BST [9] (maybe <- 0x410000ad) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i1 + 0 ] %asi P1818: !_MEMBAR (FP) membar #StoreLoad P1819: !_PREFETCH [12] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetcha [%i2 + 4] %asi, 1 P1820: !_REPLACEMENT [26] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+128], %l3 st %l3, [%i3+128] add %i3, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] P1821: !_LD [7] (Int) lduw [%i0 + 128], %l7 ! move %l7(lower) -> %o4(lower) or %l7, %o4, %o4 !---- flushing int results buffer---- mov %o0, %l5 mov %o1, %l5 mov %o2, %l5 mov %o3, %l5 mov %o4, %l5 P1822: !_PREFETCH [8] (Int) (Branch target of P1693) prefetch [%i1 + 0], 1 ba P1823 nop TARGET1693: ba RET1693 nop P1823: !_ST [14] (maybe <- 0x1800010) (Int) (LE) (Branch target of P1699) wr %g0, 0x88, %asi ! Change single-word-level endianess (big endian <-> little endian) sethi %hi(0xff00ff00), %l3 or %l3, %lo(0xff00ff00), %l3 and %l4, %l3, %l6 srl %l6, 8, %l6 sll %l4, 8, %o5 and %o5, %l3, %o5 or %o5, %l6, %o5 srl %o5, 16, %l6 sll %o5, 16, %o5 srl %o5, 0, %o5 or %o5, %l6, %o5 stwa %o5, [%i2 + 64] %asi add %l4, 1, %l4 ba P1824 nop TARGET1699: ba RET1699 nop P1824: !_LD [25] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduwa [%i2 + 96] %asi, %o0 ! move %o0(lower) -> %o0(upper) sllx %o0, 32, %o0 P1825: !_LD [0] (FP) (Branch target of P1547) ld [%i0 + 0], %f12 ! 1 addresses covered ba P1826 nop TARGET1547: ba RET1547 nop P1826: !_REPLACEMENT [5] (Int) (CBR) sethi %hi(0x2000), %l3 ld [%i3+64], %l7 st %l7, [%i3+64] add %i3, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1826 nop RET1826: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1827: !_REPLACEMENT [25] (Int) (CBR) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(0x2000), %l3 ld [%i3+96], %l7 st %l7, [%i3+96] add %i3, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1827 nop RET1827: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1828: !_MEMBAR (FP) membar #StoreLoad P1829: !_BLD [31] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 192] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 P1830: !_MEMBAR (FP) P1831: !_BLD [25] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f14 fmovd %f40, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- P1832: !_MEMBAR (FP) P1833: !_ST [27] (maybe <- 0x410000af) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 160 ] P1834: !_REPLACEMENT [9] (Int) (Branch target of P1728) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %o5 ld [%i2+32], %l6 st %l6, [%i2+32] add %i2, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] ba P1835 nop TARGET1728: ba RET1728 nop P1835: !_FLUSHI [24] (Int) (CBR) flush %g0 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1835 nop RET1835: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1836: !_MEMBAR (FP) membar #StoreLoad P1837: !_BLD [27] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f0 membar #Sync ! 2 addresses covered fmovs %f8, %f1 P1838: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1838 nop RET1838: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1839: !_BST [12] (maybe <- 0x410000b0) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P1840: !_MEMBAR (FP) P1841: !_BSTC [30] (maybe <- 0x410000b3) (FP) (Branch target of P1637) wr %g0, 0xe0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 128 ] %asi ba P1842 nop TARGET1637: ba RET1637 nop P1842: !_MEMBAR (FP) membar #StoreLoad P1843: !_LD [23] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduwa [%i2 + 32] %asi, %o5 ! move %o5(lower) -> %o0(lower) or %o5, %o0, %o0 P1844: !_REPLACEMENT [9] (Int) (Secondary ctx) (Branch target of P1441) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+32], %l7 st %l7, [%i3+32] add %i3, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] ba P1845 nop TARGET1441: ba RET1441 nop P1845: !_REPLACEMENT [33] (Int) sethi %hi(0x2000), %o5 ld [%i3+0], %l6 st %l6, [%i3+0] add %i3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] P1846: !_MEMBAR (FP) membar #StoreLoad P1847: !_BLD [12] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f2 fmovd %f40, %f4 P1848: !_MEMBAR (FP) P1849: !_BST [1] (maybe <- 0x410000b4) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P1850: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1850 nop RET1850: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1851: !_BSTC [15] (maybe <- 0x410000b9) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 128 ] %asi P1852: !_MEMBAR (FP) P1853: !_BST [0] (maybe <- 0x410000ba) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P1854: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1854 nop RET1854: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1855: !_REPLACEMENT [7] (Int) sethi %hi(0x2000), %l6 ld [%i3+128], %o5 st %o5, [%i3+128] add %i3, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] P1856: !_REPLACEMENT [10] (Int) (CBR) (Secondary ctx) (Branch target of P1460) wr %g0, 0x81, %asi sethi %hi(0x2000), %l3 ld [%i3+64], %l7 st %l7, [%i3+64] add %i3, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1856 nop RET1856: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 ba P1857 nop TARGET1460: ba RET1460 nop P1857: !_REPLACEMENT [9] (Int) sethi %hi(0x2000), %l3 ld [%i3+32], %l7 st %l7, [%i3+32] add %i3, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] P1858: !_REPLACEMENT [32] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(0x2000), %o5 ld [%i3+256], %l6 st %l6, [%i3+256] add %i3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] P1859: !_REPLACEMENT [8] (Int) (CBR) (Branch target of P1926) sethi %hi(0x2000), %l7 ld [%i3+0], %l3 st %l3, [%i3+0] add %i3, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1859 nop RET1859: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P1860 nop TARGET1926: ba RET1926 nop P1860: !_MEMBAR (FP) (CBR) (Secondary ctx) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1860 nop RET1860: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1861: !_BSTC [28] (maybe <- 0x410000bf) (FP) (Secondary ctx) (Branch target of P1297) wr %g0, 0xe1, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 0 ] %asi ba P1862 nop TARGET1297: ba RET1297 nop P1862: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P1863: !_BLD [23] (FP) (Secondary ctx) (Branch target of P1389) wr %g0, 0xf1, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 fmovs %f19, %f6 fmovd %f40, %f18 fmovs %f18, %f7 ba P1864 nop TARGET1389: ba RET1389 nop P1864: !_MEMBAR (FP) (Secondary ctx) P1865: !_BLD [8] (FP) wr %g0, 0xf0, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f8 fmovd %f40, %f18 fmovs %f18, %f9 P1866: !_MEMBAR (FP) P1867: !_BLD [4] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f10 fmovd %f34, %f12 fmovd %f36, %f18 fmovs %f18, %f13 fmovd %f40, %f14 P1868: !_MEMBAR (FP) (CBR) (Secondary ctx) (Branch target of P1708) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1868 nop RET1868: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P1869 nop TARGET1708: ba RET1708 nop P1869: !_BLD [18] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- P1870: !_MEMBAR (FP) P1871: !_BSTC [20] (maybe <- 0x410000c0) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 256 ] %asi P1872: !_MEMBAR (FP) (Branch target of P1408) membar #StoreLoad ba P1873 nop TARGET1408: ba RET1408 nop P1873: !_BLD [18] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i3 + 128] %asi, %f0 membar #Sync ! 1 addresses covered ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1873 nop RET1873: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1874: !_MEMBAR (FP) P1875: !_ST [9] (maybe <- 0x1800011) (Int) stw %l4, [%i1 + 32 ] add %l4, 1, %l4 P1876: !_MEMBAR (FP) membar #StoreLoad P1877: !_BLD [6] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 fmovd %f40, %f2 P1878: !_MEMBAR (FP) P1879: !_LD [9] (Int) (CBR) lduw [%i1 + 32], %o1 ! move %o1(lower) -> %o1(upper) sllx %o1, 32, %o1 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1879 nop RET1879: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1880: !_MEMBAR (FP) (Secondary ctx) P1881: !_BSTC [23] (maybe <- 0x410000c1) (FP) (Secondary ctx) wr %g0, 0xe1, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P1882: !_MEMBAR (FP) (Secondary ctx) P1883: !_BSTC [28] (maybe <- 0x410000c4) (FP) (CBR) wr %g0, 0xe0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1883 nop RET1883: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1884: !_MEMBAR (FP) membar #StoreLoad P1885: !_BLD [14] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 P1886: !_MEMBAR (FP) P1887: !_LD [25] (FP) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lda [%i2 + 96] %asi, %f4 ! 1 addresses covered P1888: !_PREFETCH [25] (Int) (Branch target of P1616) prefetch [%i2 + 96], 1 ba P1889 nop TARGET1616: ba RET1616 nop P1889: !_MEMBAR (FP) (Secondary ctx) P1890: !_BSTC [13] (maybe <- 0x410000c5) (FP) (Secondary ctx) wr %g0, 0xe1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P1891: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P1892: !_PREFETCH [32] (Int) (Nucleus ctx) (Branch target of P1850) wr %g0, 0x4, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetcha [%i3 + 256] %asi, 1 ba P1893 nop TARGET1850: ba RET1850 nop P1893: !_ST [7] (maybe <- 0x1800012) (Int) (CBR) stw %l4, [%i0 + 128 ] add %l4, 1, %l4 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1893 nop RET1893: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1894: !_REPLACEMENT [32] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %o5 ld [%i2+256], %l6 st %l6, [%i2+256] add %i2, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] P1895: !_ST [1] (maybe <- 0x1800013) (Int) stw %l4, [%i0 + 4 ] add %l4, 1, %l4 P1896: !_ST [10] (maybe <- 0x410000c8) (FP) (Secondary ctx) wr %g0, 0x81, %asi ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i1 + 64 ] %asi P1897: !_PREFETCH [3] (Int) (Branch target of P1517) prefetch [%i0 + 16], 1 ba P1898 nop TARGET1517: ba RET1517 nop P1898: !_REPLACEMENT [31] (Int) sethi %hi(0x2000), %l3 ld [%i2+192], %l7 st %l7, [%i2+192] add %i2, %l3, %l6 ld [%l6+192], %l7 st %l7, [%l6+192] add %l6, %l3, %l6 ld [%l6+192], %l7 st %l7, [%l6+192] add %l6, %l3, %l6 ld [%l6+192], %l7 st %l7, [%l6+192] add %l6, %l3, %l6 ld [%l6+192], %l7 st %l7, [%l6+192] add %l6, %l3, %l6 ld [%l6+192], %l7 st %l7, [%l6+192] add %l6, %l3, %l6 ld [%l6+192], %l7 st %l7, [%l6+192] add %l6, %l3, %l6 ld [%l6+192], %l7 st %l7, [%l6+192] P1899: !_MEMBAR (FP) P1900: !_BST [23] (maybe <- 0x410000c9) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P1901: !_MEMBAR (FP) membar #StoreLoad P1902: !_BLD [6] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 fmovd %f40, %f6 P1903: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1903 nop RET1903: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1904: !_PREFETCH [5] (Int) (CBR) prefetch [%i0 + 64], 1 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1904 nop RET1904: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1905: !_PREFETCH [10] (Int) prefetch [%i1 + 64], 1 P1906: !_REPLACEMENT [5] (Int) sethi %hi(0x2000), %l3 ld [%i2+64], %l7 st %l7, [%i2+64] add %i2, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] P1907: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1907 nop RET1907: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1908: !_BLD [22] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 fmovs %f19, %f8 fmovd %f40, %f18 fmovs %f18, %f9 P1909: !_MEMBAR (FP) P1910: !_BLD [25] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f10 fmovd %f40, %f18 fmovs %f18, %f11 P1911: !_MEMBAR (FP) P1912: !_LD [23] (FP) ld [%i3 + 32], %f12 ! 1 addresses covered P1913: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1913 nop RET1913: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1914: !_BLD [10] (FP) wr %g0, 0xf0, %asi ldda [%i1 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 P1915: !_MEMBAR (FP) P1916: !_BST [14] (maybe <- 0x410000cc) (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1916 nop RET1916: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P1917: !_MEMBAR (FP) membar #StoreLoad P1918: !_BLD [32] (FP) (Branch target of P1922) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f14 ba P1919 nop TARGET1922: ba RET1922 nop P1919: !_MEMBAR (FP) P1920: !_PREFETCH [27] (Int) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 160], 1 P1921: !_MEMBAR (FP) membar #StoreLoad P1922: !_BLD [3] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovs %f19, %f0 fmovd %f34, %f18 fmovs %f18, %f1 fmovd %f36, %f2 fmovd %f40, %f18 fmovs %f18, %f3 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1922 nop RET1922: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1923: !_MEMBAR (FP) P1924: !_BSTC [5] (maybe <- 0x410000cd) (FP) (Secondary ctx) wr %g0, 0xe1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 64 ] %asi P1925: !_MEMBAR (FP) (Secondary ctx) (Branch target of P1838) membar #StoreLoad ba P1926 nop TARGET1838: ba RET1838 nop P1926: !_BLD [8] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f4 fmovd %f40, %f18 fmovs %f18, %f5 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1926 nop RET1926: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1927: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1927 nop RET1927: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1928: !_LD [25] (Int) lduw [%i2 + 96], %l3 ! move %l3(lower) -> %o1(lower) or %l3, %o1, %o1 P1929: !_MEMBAR (FP) membar #StoreLoad P1930: !_BLD [10] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i1 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f6 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1930 nop RET1930: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1931: !_MEMBAR (FP) P1932: !_ST [33] (maybe <- 0x1800014) (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stwa %l4, [%i3 + 0] %asi add %l4, 1, %l4 P1933: !_PREFETCH [30] (Int) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 128], 1 P1934: !_MEMBAR (FP) (Branch target of P1491) ba P1935 nop TARGET1491: ba RET1491 nop P1935: !_BST [32] (maybe <- 0x410000cf) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 256 ] %asi P1936: !_MEMBAR (FP) membar #StoreLoad P1937: !_LD [3] (Int) (Nucleus ctx) wr %g0, 0x4, %asi lduwa [%i0 + 16] %asi, %o2 ! move %o2(lower) -> %o2(upper) sllx %o2, 32, %o2 P1938: !_MEMBAR (FP) (Branch target of P1927) membar #StoreLoad ba P1939 nop TARGET1927: ba RET1927 nop P1939: !_BLD [33] (FP) (CBR) (Branch target of P1320) wr %g0, 0xf0, %asi ldda [%i3 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1939 nop RET1939: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P1940 nop TARGET1320: ba RET1320 nop P1940: !_MEMBAR (FP) P1941: !_LD [14] (Int) (Loop exit) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lduw [%i3 + 64], %l3 ! move %l3(lower) -> %o2(lower) or %l3, %o2, %o2 !---- flushing int results buffer---- mov %o0, %l5 mov %o1, %l5 mov %o2, %l5 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 !-- loop_exit_3_0: sub %l2, 1, %l2 cmp %l2, 0 bg loop_entry_3_0 nop P1942: !_MEMBAR (Int) membar #StoreLoad END_NODES3: ! Test instruction sequence for CPU 3 ends sethi %hi(0xdead0e0f), %l7 or %l7, %lo(0xdead0e0f), %l7 ! move %l7(lower) -> %o0(upper) sllx %l7, 32, %o0 sethi %hi(0xdead0e0f), %l7 or %l7, %lo(0xdead0e0f), %l7 stw %l7, [%i5] ld [%i5], %f0 !---- flushing int results buffer---- mov %o0, %l5 !---- flushing fp results buffer to %f30 ---- fmovs %f0, %f30 !-- restore retl nop !----------------- ! register usage: ! %i0 %i1 : base registers for first 2 regions ! %i2 %i3 : cache registers for 8 regions ! %i4 fixed pointer to per-cpu results area ! %l1 moving pointer to per-cpu FP results area ! %o7 moving pointer to per-cpu integer results area ! %i5 pointer to per-cpu private area ! %l0 holds lfsr, used as source of random bits ! %l2 loop count register ! %f16 running counter for unique fp store values ! %f17 holds increment value for fp counter ! %l4 running counter for unique integer store values (increment value is always 1) ! %l5 move-to register for load values (simulation only) ! %f30 move-to register for FP values (simulation only) ! %i4 holds the instructions count which is used for interrupt ordering ! %i4 holds the thread_id (OBP only) ! %l5 holds the moving pointer for interrupt bonus data (OBP only). Conflicts with RTL/simulation usage ! %l3 %l6 %l7 %o5 : 4 temporary registers ! %o0 %o1 %o2 %o3 %o4 : 5 integer results buffer registers ! %f0-f15 FP results buffer registers ! %f32-f47 FP block load/store registers func4: ! instruction sequence begins save %sp, -192, %sp ! Force %i0-%i3 to be 64-byte aligned add %i0, 63, %i0 andn %i0, 63, %i0 add %i1, 63, %i1 andn %i1, 63, %i1 add %i2, 63, %i2 andn %i2, 63, %i2 add %i3, 63, %i3 andn %i3, 63, %i3 add %i4, 63, %i4 andn %i4, 63, %i4 add %i5, 63, %i5 andn %i5, 63, %i5 ! Initialize pointer to FP load results area mov %i4, %l1 ! Initialize pointer to integer load results area sethi %hi(0x80000), %o7 or %o7, %lo(0x80000), %o7 add %o7, %l1, %o7 ! Reinitialize i4 to 0. i4 will be used to keep the count of analyzable node info mov 0x0, %i4 ! Initialize %f0-%f62 to 0xdeadbee0deadbee1 sethi %hi(0xdeadbee0), %l6 or %l6, %lo(0xdeadbee0), %l6 stw %l6, [%i5] sethi %hi(0xdeadbee1), %l6 or %l6, %lo(0xdeadbee1), %l6 stw %l6, [%i5+4] ldd [%i5], %f0 fmovd %f0, %f2 fmovd %f0, %f4 fmovd %f0, %f6 fmovd %f0, %f8 fmovd %f0, %f10 fmovd %f0, %f12 fmovd %f0, %f14 fmovd %f0, %f16 fmovd %f0, %f18 fmovd %f0, %f20 fmovd %f0, %f22 fmovd %f0, %f24 fmovd %f0, %f26 fmovd %f0, %f28 fmovd %f0, %f30 fmovd %f0, %f32 fmovd %f0, %f34 fmovd %f0, %f36 fmovd %f0, %f38 fmovd %f0, %f40 fmovd %f0, %f42 fmovd %f0, %f44 fmovd %f0, %f46 fmovd %f0, %f48 fmovd %f0, %f50 fmovd %f0, %f52 fmovd %f0, %f54 fmovd %f0, %f56 fmovd %f0, %f58 fmovd %f0, %f60 fmovd %f0, %f62 ! Signature for extract_loads script to start extracting load values for this stream sethi %hi(0x04deade1), %l6 or %l6, %lo(0x04deade1), %l6 stw %l6, [%i5] ld [%i5], %f16 ! Initialize running integer counter in register %l4 sethi %hi(0x2000001), %l4 or %l4, %lo(0x2000001), %l4 ! Initialize running FP counter in register %f16 sethi %hi(0x41800001), %l6 or %l6, %lo(0x41800001), %l6 stw %l6, [%i5] ld [%i5], %f16 ! Initialize FP counter increment value in register %f17 (constant) sethi %hi(0x36000000), %l6 or %l6, %lo(0x36000000), %l6 stw %l6, [%i5] ld [%i5], %f17 ! Initialize LFSR to 0x6fc4^4 sethi %hi(0x6fc4), %l0 or %l0, %lo(0x6fc4), %l0 mulx %l0, %l0, %l0 mulx %l0, %l0, %l0 BEGIN_NODES4: ! Test instruction sequence for ISTREAM 4 begins P1943: !_MEMBAR (FP) (Loop entry) sethi %hi(0x5), %l2 or %l2, %lo(0x5), %l2 loop_entry_4_0: P1944: !_BST [6] (maybe <- 0x41800001) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 64 ] %asi P1945: !_MEMBAR (FP) membar #StoreLoad P1946: !_LD [29] (FP) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ld [%i2 + 64], %f0 ! 1 addresses covered P1947: !_ST [26] (maybe <- 0x2000001) (Int) (Branch target of P2173) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stw %l4, [%i3 + 128 ] add %l4, 1, %l4 ba P1948 nop TARGET2173: ba RET2173 nop P1948: !_ST [14] (maybe <- 0x41800003) (FP) (CBR) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 64 ] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1948 nop RET1948: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P1949: !_MEMBAR (Int) (Branch target of P2175) membar #StoreLoad ba P1950 nop TARGET2175: ba RET2175 nop P1950: !_REPLACEMENT [4] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+32], %l7 st %l7, [%i3+32] add %i3, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] P1951: !_MEMBAR (FP) membar #StoreLoad P1952: !_BLD [12] (FP) (Branch target of P2041) wr %g0, 0xf0, %asi ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 fmovs %f19, %f2 fmovd %f40, %f18 fmovs %f18, %f3 ba P1953 nop TARGET2041: ba RET2041 nop P1953: !_MEMBAR (FP) P1954: !_BST [33] (maybe <- 0x41800004) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 0 ] %asi P1955: !_MEMBAR (FP) membar #StoreLoad P1956: !_REPLACEMENT [28] (Int) (Nucleus ctx) (Branch target of P2017) wr %g0, 0x4, %asi sethi %hi(0x2000), %l7 ld [%i3+0], %l3 st %l3, [%i3+0] add %i3, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] ba P1957 nop TARGET2017: ba RET2017 nop P1957: !_PREFETCH [27] (Int) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 160], 1 P1958: !_REPLACEMENT [26] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l6 ld [%i2+128], %o5 st %o5, [%i2+128] add %i2, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] P1959: !_MEMBAR (FP) (Secondary ctx) P1960: !_BST [12] (maybe <- 0x41800005) (FP) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P1961: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P1962: !_REPLACEMENT [1] (Int) (Branch target of P2192) sethi %hi(0x2000), %o5 ld [%i2+4], %l6 st %l6, [%i2+4] add %i2, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] ba P1963 nop TARGET2192: ba RET2192 nop P1963: !_MEMBAR (FP) (Secondary ctx) (Branch target of P2098) ba P1964 nop TARGET2098: ba RET2098 nop P1964: !_BSTC [5] (maybe <- 0x41800008) (FP) (Secondary ctx) wr %g0, 0xe1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 64 ] %asi P1965: !_MEMBAR (FP) (CBR) (Secondary ctx) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1965 nop RET1965: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1966: !_BSTC [27] (maybe <- 0x4180000a) (FP) (CBR) wr %g0, 0xe0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 128 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1966 nop RET1966: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P1967: !_MEMBAR (FP) membar #StoreLoad P1968: !_LD [9] (Int) lduw [%i1 + 32], %o0 ! move %o0(lower) -> %o0(upper) sllx %o0, 32, %o0 P1969: !_MEMBAR (FP) membar #StoreLoad P1970: !_BLD [6] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f4 fmovd %f40, %f18 fmovs %f18, %f5 P1971: !_MEMBAR (FP) P1972: !_BST [15] (maybe <- 0x4180000c) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 128 ] %asi P1973: !_MEMBAR (FP) membar #StoreLoad P1974: !_BLD [24] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f6 fmovd %f40, %f18 fmovs %f18, %f7 P1975: !_MEMBAR (FP) P1976: !_REPLACEMENT [24] (Int) (CBR) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %o5 ld [%i3+64], %l6 st %l6, [%i3+64] add %i3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1976 nop RET1976: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1977: !_MEMBAR (FP) (Branch target of P2115) ba P1978 nop TARGET2115: ba RET2115 nop P1978: !_BST [20] (maybe <- 0x4180000d) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 256 ] %asi P1979: !_MEMBAR (FP) membar #StoreLoad P1980: !_PREFETCH [30] (Int) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 128], 1 P1981: !_MEMBAR (FP) membar #StoreLoad P1982: !_BLD [11] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f8 fmovd %f40, %f10 P1983: !_MEMBAR (FP) (CBR) (Branch target of P2008) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1983 nop RET1983: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P1984 nop TARGET2008: ba RET2008 nop P1984: !_BSTC [17] (maybe <- 0x4180000e) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f40 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 64 ] %asi P1985: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1985 nop RET1985: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P1986: !_BSTC [13] (maybe <- 0x4180000f) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P1987: !_MEMBAR (FP) membar #StoreLoad P1988: !_ST [27] (maybe <- 0x41800012) (FP) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i2 + 160 ] %asi P1989: !_MEMBAR (FP) (CBR) (Branch target of P2205) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET1989 nop RET1989: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P1990 nop TARGET2205: ba RET2205 nop P1990: !_BLD [10] (FP) wr %g0, 0xf0, %asi ldda [%i1 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 P1991: !_MEMBAR (FP) P1992: !_BLD [20] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f12 P1993: !_MEMBAR (FP) P1994: !_REPLACEMENT [32] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l7 ld [%i2+256], %l3 st %l3, [%i2+256] add %i2, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] P1995: !_ST [8] (maybe <- 0x41800013) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i1 + 0 ] P1996: !_MEMBAR (FP) P1997: !_BSTC [15] (maybe <- 0x41800014) (FP) (CBR) (Branch target of P2053) wr %g0, 0xe0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 128 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET1997 nop RET1997: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 ba P1998 nop TARGET2053: ba RET2053 nop P1998: !_MEMBAR (FP) membar #StoreLoad P1999: !_ST [10] (maybe <- 0x41800015) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i1 + 64 ] P2000: !_PREFETCH [30] (Int) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 128], 1 P2001: !_REPLACEMENT [31] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %o5 ld [%i3+192], %l6 st %l6, [%i3+192] add %i3, %o5, %l3 ld [%l3+192], %l6 st %l6, [%l3+192] add %l3, %o5, %l3 ld [%l3+192], %l6 st %l6, [%l3+192] add %l3, %o5, %l3 ld [%l3+192], %l6 st %l6, [%l3+192] add %l3, %o5, %l3 ld [%l3+192], %l6 st %l6, [%l3+192] add %l3, %o5, %l3 ld [%l3+192], %l6 st %l6, [%l3+192] add %l3, %o5, %l3 ld [%l3+192], %l6 st %l6, [%l3+192] add %l3, %o5, %l3 ld [%l3+192], %l6 st %l6, [%l3+192] P2002: !_MEMBAR (FP) P2003: !_BSTC [7] (maybe <- 0x41800016) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i0 + 128 ] %asi P2004: !_MEMBAR (FP) membar #StoreLoad P2005: !_REPLACEMENT [14] (Int) sethi %hi(0x2000), %l6 ld [%i3+64], %o5 st %o5, [%i3+64] add %i3, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] P2006: !_MEMBAR (FP) membar #StoreLoad P2007: !_BLD [20] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 P2008: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2008 nop RET2008: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2009: !_PREFETCH [30] (Int) (CBR) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetcha [%i3 + 128] %asi, 1 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2009 nop RET2009: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2010: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2010 nop RET2010: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2011: !_BLD [14] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f14 P2012: !_MEMBAR (FP) P2013: !_BST [31] (maybe <- 0x41800017) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 192 ] %asi P2014: !_MEMBAR (FP) (Branch target of P2045) membar #StoreLoad ba P2015 nop TARGET2045: ba RET2045 nop P2015: !_BLD [4] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovs %f19, %f0 fmovd %f34, %f18 fmovs %f18, %f1 fmovd %f36, %f2 fmovd %f40, %f18 fmovs %f18, %f3 P2016: !_MEMBAR (FP) P2017: !_BST [24] (maybe <- 0x41800018) (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2017 nop RET2017: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2018: !_MEMBAR (FP) membar #StoreLoad P2019: !_BLD [27] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i3 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f4 fmovd %f40, %f18 fmovs %f18, %f5 P2020: !_MEMBAR (FP) (Secondary ctx) P2021: !_PREFETCH [19] (Int) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 0], 1 P2022: !_REPLACEMENT [26] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+128], %l3 st %l3, [%i3+128] add %i3, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] P2023: !_LD [3] (Int) (Secondary ctx) wr %g0, 0x81, %asi lduwa [%i0 + 16] %asi, %l7 ! move %l7(lower) -> %o0(lower) or %l7, %o0, %o0 P2024: !_MEMBAR (FP) membar #StoreLoad P2025: !_BLD [30] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f6 P2026: !_MEMBAR (FP) P2027: !_BLD [25] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 fmovd %f40, %f8 P2028: !_MEMBAR (FP) P2029: !_BLD [5] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f9 fmovd %f40, %f10 P2030: !_MEMBAR (FP) P2031: !_REPLACEMENT [5] (Int) (CBR) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %o5 ld [%i2+64], %l6 st %l6, [%i2+64] add %i2, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2031 nop RET2031: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2032: !_LD [16] (FP) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lda [%i3 + 16] %asi, %f11 ! 1 addresses covered P2033: !_REPLACEMENT [22] (Int) sethi %hi(0x2000), %o5 ld [%i2+4], %l6 st %l6, [%i2+4] add %i2, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] P2034: !_ST [18] (maybe <- 0x2000002) (Int) (Secondary ctx) wr %g0, 0x81, %asi stwa %l4, [%i3 + 128] %asi add %l4, 1, %l4 P2035: !_ST [24] (maybe <- 0x2000003) (Int) (LE) (Nucleus ctx) wr %g0, 0xc, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! Change single-word-level endianess (big endian <-> little endian) sethi %hi(0xff00ff00), %l7 or %l7, %lo(0xff00ff00), %l7 and %l4, %l7, %o5 srl %o5, 8, %o5 sll %l4, 8, %l6 and %l6, %l7, %l6 or %l6, %o5, %l6 srl %l6, 16, %o5 sll %l6, 16, %l6 srl %l6, 0, %l6 or %l6, %o5, %l6 stwa %l6, [%i2 + 64] %asi add %l4, 1, %l4 P2036: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2036 nop RET2036: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2037: !_BLD [26] (FP) (CBR) (Branch target of P2109) wr %g0, 0xf0, %asi ldda [%i2 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f12 fmovd %f40, %f18 fmovs %f18, %f13 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2037 nop RET2037: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P2038 nop TARGET2109: ba RET2109 nop P2038: !_MEMBAR (FP) (Branch target of P2092) ba P2039 nop TARGET2092: ba RET2092 nop P2039: !_BLD [0] (FP) (Branch target of P2037) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f14 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f34, %f0 fmovd %f36, %f18 fmovs %f18, %f1 fmovd %f40, %f2 ba P2040 nop TARGET2037: ba RET2037 nop P2040: !_MEMBAR (FP) P2041: !_IDC_FLIP [22] (Int) (CBR) IDC_FLIP(2041, 15483, 4, 0x45800004, 0x4, %i2, 0x4, %l6, %l7, %o5, %l3) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2041 nop RET2041: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2042: !_MEMBAR (FP) membar #StoreLoad P2043: !_BLD [11] (FP) (Branch target of P1997) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 fmovs %f19, %f4 fmovd %f40, %f18 fmovs %f18, %f5 ba P2044 nop TARGET1997: ba RET1997 nop P2044: !_MEMBAR (FP) P2045: !_BLD [27] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i2 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f6 fmovd %f40, %f18 fmovs %f18, %f7 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2045 nop RET2045: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2046: !_MEMBAR (FP) P2047: !_PREFETCH [4] (Int) (CBR) prefetch [%i0 + 32], 1 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2047 nop RET2047: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2048: !_MEMBAR (FP) (Branch target of P2052) membar #StoreLoad ba P2049 nop TARGET2052: ba RET2052 nop P2049: !_BLD [5] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f8 fmovd %f40, %f18 fmovs %f18, %f9 P2050: !_MEMBAR (FP) P2051: !_BLD [26] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f10 fmovd %f40, %f18 fmovs %f18, %f11 P2052: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2052 nop RET2052: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2053: !_BLD [28] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f12 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2053 nop RET2053: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2054: !_MEMBAR (FP) P2055: !_REPLACEMENT [9] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+32], %l3 st %l3, [%i3+32] add %i3, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] P2056: !_REPLACEMENT [3] (Int) sethi %hi(0x2000), %l6 ld [%i3+16], %o5 st %o5, [%i3+16] add %i3, %l6, %l7 ld [%l7+16], %o5 st %o5, [%l7+16] add %l7, %l6, %l7 ld [%l7+16], %o5 st %o5, [%l7+16] add %l7, %l6, %l7 ld [%l7+16], %o5 st %o5, [%l7+16] add %l7, %l6, %l7 ld [%l7+16], %o5 st %o5, [%l7+16] add %l7, %l6, %l7 ld [%l7+16], %o5 st %o5, [%l7+16] add %l7, %l6, %l7 ld [%l7+16], %o5 st %o5, [%l7+16] add %l7, %l6, %l7 ld [%l7+16], %o5 st %o5, [%l7+16] P2057: !_ST [13] (maybe <- 0x2000004) (Int) (Branch target of P2060) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 stw %l4, [%i2 + 32 ] add %l4, 1, %l4 ba P2058 nop TARGET2060: ba RET2060 nop P2058: !_MEMBAR (FP) (Secondary ctx) P2059: !_BSTC [25] (maybe <- 0x4180001a) (FP) (Secondary ctx) wr %g0, 0xe1, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 64 ] %asi P2060: !_MEMBAR (FP) (CBR) (Secondary ctx) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2060 nop RET2060: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2061: !_LD [22] (Int) (Secondary ctx) wr %g0, 0x81, %asi lduwa [%i3 + 4] %asi, %o1 ! move %o1(lower) -> %o1(upper) sllx %o1, 32, %o1 P2062: !_MEMBAR (FP) (CBR) (Secondary ctx) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2062 nop RET2062: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2063: !_BLD [10] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i1 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 P2064: !_MEMBAR (FP) (Secondary ctx) P2065: !_REPLACEMENT [2] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l7 ld [%i2+8], %l3 st %l3, [%i2+8] add %i2, %l7, %o5 ld [%o5+8], %l3 st %l3, [%o5+8] add %o5, %l7, %o5 ld [%o5+8], %l3 st %l3, [%o5+8] add %o5, %l7, %o5 ld [%o5+8], %l3 st %l3, [%o5+8] add %o5, %l7, %o5 ld [%o5+8], %l3 st %l3, [%o5+8] add %o5, %l7, %o5 ld [%o5+8], %l3 st %l3, [%o5+8] add %o5, %l7, %o5 ld [%o5+8], %l3 st %l3, [%o5+8] add %o5, %l7, %o5 ld [%o5+8], %l3 st %l3, [%o5+8] P2066: !_PREFETCH [17] (Int) (CBR) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 96], 1 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2066 nop RET2066: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2067: !_REPLACEMENT [17] (Int) sethi %hi(0x2000), %l7 ld [%i2+96], %l3 st %l3, [%i2+96] add %i2, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] P2068: !_ST [29] (maybe <- 0x2000005) (Int) (LE) wr %g0, 0x88, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! Change single-word-level endianess (big endian <-> little endian) sethi %hi(0xff00ff00), %l7 or %l7, %lo(0xff00ff00), %l7 and %l4, %l7, %o5 srl %o5, 8, %o5 sll %l4, 8, %l6 and %l6, %l7, %l6 or %l6, %o5, %l6 srl %l6, 16, %o5 sll %l6, 16, %l6 srl %l6, 0, %l6 or %l6, %o5, %l6 stwa %l6, [%i2 + 64] %asi add %l4, 1, %l4 P2069: !_MEMBAR (FP) membar #StoreLoad P2070: !_BLD [17] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f40, %f14 P2071: !_MEMBAR (FP) P2072: !_BLD [22] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovs %f19, %f0 fmovd %f40, %f18 fmovs %f18, %f1 P2073: !_MEMBAR (FP) P2074: !_LD [14] (Int) (Branch target of P2164) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduw [%i2 + 64], %l6 ! move %l6(lower) -> %o1(lower) or %l6, %o1, %o1 ba P2075 nop TARGET2164: ba RET2164 nop P2075: !_REPLACEMENT [6] (Int) (Branch target of P2047) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+96], %l3 st %l3, [%i3+96] add %i3, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] ba P2076 nop TARGET2047: ba RET2047 nop P2076: !_MEMBAR (FP) P2077: !_BST [24] (maybe <- 0x4180001c) (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2077 nop RET2077: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2078: !_MEMBAR (FP) membar #StoreLoad P2079: !_BLD [20] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f2 P2080: !_MEMBAR (FP) (Branch target of P2031) ba P2081 nop TARGET2031: ba RET2031 nop P2081: !_BLD [22] (FP) (CBR) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 fmovs %f19, %f4 fmovd %f40, %f18 fmovs %f18, %f5 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2081 nop RET2081: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2082: !_MEMBAR (FP) (Secondary ctx) P2083: !_LD [32] (FP) (Branch target of P2151) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ld [%i2 + 256], %f6 ! 1 addresses covered ba P2084 nop TARGET2151: ba RET2151 nop P2084: !_MEMBAR (FP) (Branch target of P2117) ba P2085 nop TARGET2117: ba RET2117 nop P2085: !_BSTC [9] (maybe <- 0x4180001e) (FP) (Branch target of P2066) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i1 + 0 ] %asi ba P2086 nop TARGET2066: ba RET2066 nop P2086: !_MEMBAR (FP) membar #StoreLoad P2087: !_BLD [20] (FP) (Branch target of P1985) wr %g0, 0xf0, %asi ldda [%i3 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 ba P2088 nop TARGET1985: ba RET1985 nop P2088: !_MEMBAR (FP) P2089: !_LD [27] (FP) (CBR) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ld [%i3 + 160], %f8 ! 1 addresses covered ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2089 nop RET2089: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2090: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P2091: !_BLD [29] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i2 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f9 P2092: !_MEMBAR (FP) (CBR) (Secondary ctx) (Branch target of P1948) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2092 nop RET2092: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P2093 nop TARGET1948: ba RET1948 nop P2093: !_BLD [7] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i0 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f10 P2094: !_MEMBAR (FP) (Secondary ctx) P2095: !_BLD [22] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 fmovs %f19, %f12 fmovd %f40, %f18 fmovs %f18, %f13 P2096: !_MEMBAR (FP) (Secondary ctx) P2097: !_LD [6] (FP) (Secondary ctx) wr %g0, 0x81, %asi lda [%i0 + 96] %asi, %f14 ! 1 addresses covered P2098: !_LD [8] (Int) (CBR) (Branch target of P2122) lduw [%i1 + 0], %o2 ! move %o2(lower) -> %o2(upper) sllx %o2, 32, %o2 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2098 nop RET2098: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P2099 nop TARGET2122: ba RET2122 nop P2099: !_MEMBAR (FP) membar #StoreLoad P2100: !_BLD [8] (FP) wr %g0, 0xf0, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f40, %f0 P2101: !_MEMBAR (FP) P2102: !_BLD [21] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 fmovs %f19, %f2 fmovd %f40, %f18 fmovs %f18, %f3 P2103: !_MEMBAR (FP) P2104: !_REPLACEMENT [23] (Int) (CBR) (Secondary ctx) (Branch target of P2181) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l7 ld [%i2+32], %l3 st %l3, [%i2+32] add %i2, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2104 nop RET2104: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P2105 nop TARGET2181: ba RET2181 nop P2105: !_ST [26] (maybe <- 0x41800020) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 128 ] P2106: !_REPLACEMENT [6] (Int) sethi %hi(0x2000), %l6 ld [%i2+96], %o5 st %o5, [%i2+96] add %i2, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] P2107: !_LD [27] (FP) (Nucleus ctx) wr %g0, 0x4, %asi lda [%i3 + 160] %asi, %f4 ! 1 addresses covered P2108: !_LD [21] (FP) ld [%i3 + 0], %f5 ! 1 addresses covered P2109: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2109 nop RET2109: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2110: !_BST [26] (maybe <- 0x41800021) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 128 ] %asi P2111: !_MEMBAR (FP) membar #StoreLoad P2112: !_ST [14] (maybe <- 0x2000006) (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stwa %l4, [%i3 + 64] %asi add %l4, 1, %l4 P2113: !_REPLACEMENT [2] (Int) (Branch target of P1983) sethi %hi(0x2000), %o5 ld [%i2+8], %l6 st %l6, [%i2+8] add %i2, %o5, %l3 ld [%l3+8], %l6 st %l6, [%l3+8] add %l3, %o5, %l3 ld [%l3+8], %l6 st %l6, [%l3+8] add %l3, %o5, %l3 ld [%l3+8], %l6 st %l6, [%l3+8] add %l3, %o5, %l3 ld [%l3+8], %l6 st %l6, [%l3+8] add %l3, %o5, %l3 ld [%l3+8], %l6 st %l6, [%l3+8] add %l3, %o5, %l3 ld [%l3+8], %l6 st %l6, [%l3+8] add %l3, %o5, %l3 ld [%l3+8], %l6 st %l6, [%l3+8] ba P2114 nop TARGET1983: ba RET1983 nop P2114: !_REPLACEMENT [16] (Int) sethi %hi(0x2000), %l7 ld [%i2+16], %l3 st %l3, [%i2+16] add %i2, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] P2115: !_REPLACEMENT [24] (Int) (CBR) (Branch target of P2139) sethi %hi(0x2000), %l6 ld [%i2+64], %o5 st %o5, [%i2+64] add %i2, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2115 nop RET2115: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P2116 nop TARGET2139: ba RET2139 nop P2116: !_REPLACEMENT [24] (Int) sethi %hi(0x2000), %l6 ld [%i2+64], %o5 st %o5, [%i2+64] add %i2, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] P2117: !_REPLACEMENT [23] (Int) (CBR) sethi %hi(0x2000), %l3 ld [%i2+32], %l7 st %l7, [%i2+32] add %i2, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2117 nop RET2117: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2118: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2118 nop RET2118: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2119: !_BSTC [33] (maybe <- 0x41800023) (FP) (Branch target of P2216) wr %g0, 0xe0, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 0 ] %asi ba P2120 nop TARGET2216: ba RET2216 nop P2120: !_MEMBAR (FP) (Branch target of P2152) membar #StoreLoad ba P2121 nop TARGET2152: ba RET2152 nop P2121: !_PREFETCH [19] (Int) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 0], 1 P2122: !_LD [0] (Int) (Loop exit) (CBR) lduw [%i0 + 0], %l6 ! move %l6(lower) -> %o2(lower) or %l6, %o2, %o2 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2122 nop RET2122: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 !---- flushing int results buffer---- mov %o0, %l5 mov %o1, %l5 mov %o2, %l5 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 !-- loop_exit_4_0: sub %l2, 1, %l2 cmp %l2, 0 bg loop_entry_4_0 nop P2123: !_MEMBAR (FP) (Loop entry) (CBR) sethi %hi(0x1), %l2 or %l2, %lo(0x1), %l2 loop_entry_4_1: membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2123 nop RET2123: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2124: !_BLD [32] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 256] %asi, %f0 membar #Sync ! 1 addresses covered P2125: !_MEMBAR (FP) P2126: !_BLD [31] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i2 + 192] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 P2127: !_MEMBAR (FP) (Secondary ctx) P2128: !_BSTC [15] (maybe <- 0x41800024) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 128 ] %asi P2129: !_MEMBAR (FP) membar #StoreLoad P2130: !_REPLACEMENT [4] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+32], %l7 st %l7, [%i2+32] add %i2, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] P2131: !_REPLACEMENT [20] (Int) sethi %hi(0x2000), %o5 ld [%i2+256], %l6 st %l6, [%i2+256] add %i2, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] P2132: !_ST [8] (maybe <- 0x2000007) (Int) stw %l4, [%i1 + 0 ] add %l4, 1, %l4 P2133: !_MEMBAR (FP) membar #StoreLoad P2134: !_BLD [29] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f2 P2135: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2135 nop RET2135: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2136: !_REPLACEMENT [12] (Int) sethi %hi(0x2000), %l7 ld [%i2+4], %l3 st %l3, [%i2+4] add %i2, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] P2137: !_REPLACEMENT [26] (Int) (CBR) sethi %hi(0x2000), %l6 ld [%i2+128], %o5 st %o5, [%i2+128] add %i2, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2137 nop RET2137: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2138: !_ST [21] (maybe <- 0x41800025) (FP) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 0 ] P2139: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2139 nop RET2139: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2140: !_BST [27] (maybe <- 0x41800026) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 128 ] %asi P2141: !_MEMBAR (FP) membar #StoreLoad P2142: !_REPLACEMENT [19] (Int) (CBR) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+0], %l7 st %l7, [%i3+0] add %i3, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2142 nop RET2142: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2143: !_MEMBAR (FP) P2144: !_BSTC [12] (maybe <- 0x41800028) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P2145: !_MEMBAR (FP) membar #StoreLoad P2146: !_BLD [5] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 fmovd %f40, %f4 P2147: !_MEMBAR (FP) P2148: !_BLD [30] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 P2149: !_MEMBAR (FP) P2150: !_BLD [30] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f6 P2151: !_MEMBAR (FP) (CBR) (Branch target of P2123) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2151 nop RET2151: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 ba P2152 nop TARGET2123: ba RET2123 nop P2152: !_BLD [1] (FP) (CBR) (Branch target of P2157) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 fmovs %f19, %f8 fmovd %f34, %f18 fmovs %f18, %f9 fmovd %f36, %f10 fmovd %f40, %f18 fmovs %f18, %f11 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2152 nop RET2152: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P2153 nop TARGET2157: ba RET2157 nop P2153: !_MEMBAR (FP) (Branch target of P2062) ba P2154 nop TARGET2062: ba RET2062 nop P2154: !_BSTC [9] (maybe <- 0x4180002b) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i1 + 0 ] %asi P2155: !_MEMBAR (FP) membar #StoreLoad P2156: !_REPLACEMENT [31] (Int) (Branch target of P2009) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+192], %l7 st %l7, [%i2+192] add %i2, %l3, %l6 ld [%l6+192], %l7 st %l7, [%l6+192] add %l6, %l3, %l6 ld [%l6+192], %l7 st %l7, [%l6+192] add %l6, %l3, %l6 ld [%l6+192], %l7 st %l7, [%l6+192] add %l6, %l3, %l6 ld [%l6+192], %l7 st %l7, [%l6+192] add %l6, %l3, %l6 ld [%l6+192], %l7 st %l7, [%l6+192] add %l6, %l3, %l6 ld [%l6+192], %l7 st %l7, [%l6+192] add %l6, %l3, %l6 ld [%l6+192], %l7 st %l7, [%l6+192] ba P2157 nop TARGET2009: ba RET2009 nop P2157: !_LD [27] (FP) (CBR) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ld [%i3 + 160], %f12 ! 1 addresses covered ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2157 nop RET2157: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2158: !_REPLACEMENT [16] (Int) (Branch target of P1966) sethi %hi(0x2000), %l3 ld [%i2+16], %l7 st %l7, [%i2+16] add %i2, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] ba P2159 nop TARGET1966: ba RET1966 nop P2159: !_MEMBAR (FP) (Secondary ctx) P2160: !_BSTC [32] (maybe <- 0x4180002d) (FP) (Secondary ctx) wr %g0, 0xe1, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 256 ] %asi P2161: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P2162: !_REPLACEMENT [8] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+0], %l3 st %l3, [%i3+0] add %i3, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] P2163: !_MEMBAR (FP) P2164: !_BST [9] (maybe <- 0x4180002e) (FP) (CBR) (Branch target of P2036) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i1 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2164 nop RET2164: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P2165 nop TARGET2036: ba RET2036 nop P2165: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2165 nop RET2165: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2166: !_BST [23] (maybe <- 0x41800030) (FP) (Branch target of P2196) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi ba P2167 nop TARGET2196: ba RET2196 nop P2167: !_MEMBAR (FP) membar #StoreLoad P2168: !_ST [10] (maybe <- 0x41800033) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i1 + 64 ] P2169: !_PREFETCH [18] (Int) (CBR) (Branch target of P1965) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 128], 1 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2169 nop RET2169: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P2170 nop TARGET1965: ba RET1965 nop P2170: !_REPLACEMENT [23] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l6 ld [%i2+32], %o5 st %o5, [%i2+32] add %i2, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] P2171: !_MEMBAR (FP) membar #StoreLoad P2172: !_BLD [7] (FP) (Branch target of P2089) wr %g0, 0xf0, %asi ldda [%i0 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 ba P2173 nop TARGET2089: ba RET2089 nop P2173: !_MEMBAR (FP) (CBR) (Branch target of P1989) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2173 nop RET2173: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P2174 nop TARGET1989: ba RET1989 nop P2174: !_BST [33] (maybe <- 0x41800034) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 0 ] %asi P2175: !_MEMBAR (FP) (CBR) (Branch target of P2191) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2175 nop RET2175: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P2176 nop TARGET2191: ba RET2191 nop P2176: !_PREFETCH [32] (Int) (LE) (Secondary ctx) wr %g0, 0x89, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetcha [%i2 + 256] %asi, 1 P2177: !_ST [18] (maybe <- 0x41800035) (FP) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 128 ] P2178: !_PREFETCH [7] (Int) prefetch [%i0 + 128], 1 P2179: !_LD [0] (FP) (Branch target of P2010) ld [%i0 + 0], %f14 ! 1 addresses covered ba P2180 nop TARGET2010: ba RET2010 nop P2180: !_MEMBAR (FP) (Branch target of P2118) ba P2181 nop TARGET2118: ba RET2118 nop P2181: !_BST [22] (maybe <- 0x41800036) (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2181 nop RET2181: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2182: !_MEMBAR (FP) (Branch target of P2142) membar #StoreLoad ba P2183 nop TARGET2142: ba RET2142 nop P2183: !_ST [33] (maybe <- 0x41800039) (FP) sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 0 ] P2184: !_REPLACEMENT [12] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %o5 ld [%i2+4], %l6 st %l6, [%i2+4] add %i2, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] P2185: !_REPLACEMENT [24] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(0x2000), %l7 ld [%i2+64], %l3 st %l3, [%i2+64] add %i2, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] P2186: !_ST [15] (maybe <- 0x2000008) (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stwa %l4, [%i3 + 128] %asi add %l4, 1, %l4 P2187: !_REPLACEMENT [10] (Int) sethi %hi(0x2000), %l3 ld [%i2+64], %l7 st %l7, [%i2+64] add %i2, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] P2188: !_PREFETCH [15] (Int) (LE) wr %g0, 0x88, %asi prefetcha [%i3 + 128] %asi, 1 P2189: !_MEMBAR (FP) membar #StoreLoad P2190: !_BLD [18] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- P2191: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2191 nop RET2191: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2192: !_ST [27] (maybe <- 0x4180003a) (FP) (CBR) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i3 + 160 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2192 nop RET2192: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2193: !_ST [14] (maybe <- 0x2000009) (Int) (Branch target of P2137) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 stw %l4, [%i2 + 64 ] add %l4, 1, %l4 ba P2194 nop TARGET2137: ba RET2137 nop P2194: !_MEMBAR (FP) (Secondary ctx) (Branch target of P2135) ba P2195 nop TARGET2135: ba RET2135 nop P2195: !_BST [23] (maybe <- 0x4180003b) (FP) (Secondary ctx) wr %g0, 0xf1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P2196: !_MEMBAR (FP) (CBR) (Secondary ctx) (Branch target of P2081) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2196 nop RET2196: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P2197 nop TARGET2081: ba RET2081 nop P2197: !_REPLACEMENT [16] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %o5 ld [%i3+16], %l6 st %l6, [%i3+16] add %i3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] add %l3, %o5, %l3 ld [%l3+16], %l6 st %l6, [%l3+16] P2198: !_REPLACEMENT [6] (Int) sethi %hi(0x2000), %l7 ld [%i3+96], %l3 st %l3, [%i3+96] add %i3, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] P2199: !_MEMBAR (FP) membar #StoreLoad P2200: !_BLD [31] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 192] %asi, %f0 membar #Sync ! 1 addresses covered P2201: !_MEMBAR (FP) (Branch target of P2165) ba P2202 nop TARGET2165: ba RET2165 nop P2202: !_BLD [27] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 fmovd %f40, %f2 P2203: !_MEMBAR (FP) P2204: !_BLD [24] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 fmovd %f40, %f4 P2205: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2205 nop RET2205: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2206: !_PREFETCH [32] (Int) (Nucleus ctx) wr %g0, 0x4, %asi prefetcha [%i2 + 256] %asi, 1 P2207: !_ST [1] (maybe <- 0x200000a) (Int) stw %l4, [%i0 + 4 ] add %l4, 1, %l4 P2208: !_MEMBAR (FP) membar #StoreLoad P2209: !_BLD [20] (FP) (Branch target of P1976) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 ba P2210 nop TARGET1976: ba RET1976 nop P2210: !_MEMBAR (FP) (Branch target of P2169) ba P2211 nop TARGET2169: ba RET2169 nop P2211: !_REPLACEMENT [26] (Int) (Branch target of P2077) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l6 ld [%i3+128], %o5 st %o5, [%i3+128] add %i3, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] ba P2212 nop TARGET2077: ba RET2077 nop P2212: !_MEMBAR (FP) membar #StoreLoad P2213: !_BLD [27] (FP) (Branch target of P2104) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f6 fmovd %f40, %f18 fmovs %f18, %f7 ba P2214 nop TARGET2104: ba RET2104 nop P2214: !_MEMBAR (FP) P2215: !_BLD [19] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f8 P2216: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2216 nop RET2216: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2217: !_BST [10] (maybe <- 0x4180003e) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i1 + 64 ] %asi P2218: !_MEMBAR (FP) membar #StoreLoad P2219: !_IDC_FLIP [20] (Int) IDC_FLIP(2219, 11767, 4, 0x45000100, 0x100, %i3, 0x100, %l6, %l7, %o5, %l3) P2220: !_ST [16] (maybe <- 0x200000b) (Int) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 stw %l4, [%i2 + 16 ] add %l4, 1, %l4 P2221: !_REPLACEMENT [21] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+0], %l7 st %l7, [%i3+0] add %i3, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] P2222: !_MEMBAR (FP) membar #StoreLoad P2223: !_BLD [3] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f9 fmovs %f19, %f10 fmovd %f34, %f18 fmovs %f18, %f11 fmovd %f36, %f12 fmovd %f40, %f18 fmovs %f18, %f13 P2224: !_MEMBAR (FP) (Loop exit) !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 !-- loop_exit_4_1: sub %l2, 1, %l2 cmp %l2, 0 bg loop_entry_4_1 nop P2225: !_MEMBAR (Int) membar #StoreLoad END_NODES4: ! Test instruction sequence for CPU 4 ends sethi %hi(0xdead0e0f), %l3 or %l3, %lo(0xdead0e0f), %l3 ! move %l3(lower) -> %o0(upper) sllx %l3, 32, %o0 sethi %hi(0xdead0e0f), %l3 or %l3, %lo(0xdead0e0f), %l3 stw %l3, [%i5] ld [%i5], %f0 !---- flushing int results buffer---- mov %o0, %l5 !---- flushing fp results buffer to %f30 ---- fmovs %f0, %f30 !-- restore retl nop !----------------- ! register usage: ! %i0 %i1 : base registers for first 2 regions ! %i2 %i3 : cache registers for 8 regions ! %i4 fixed pointer to per-cpu results area ! %l1 moving pointer to per-cpu FP results area ! %o7 moving pointer to per-cpu integer results area ! %i5 pointer to per-cpu private area ! %l0 holds lfsr, used as source of random bits ! %l2 loop count register ! %f16 running counter for unique fp store values ! %f17 holds increment value for fp counter ! %l4 running counter for unique integer store values (increment value is always 1) ! %l5 move-to register for load values (simulation only) ! %f30 move-to register for FP values (simulation only) ! %i4 holds the instructions count which is used for interrupt ordering ! %i4 holds the thread_id (OBP only) ! %l5 holds the moving pointer for interrupt bonus data (OBP only). Conflicts with RTL/simulation usage ! %l3 %l6 %l7 %o5 : 4 temporary registers ! %o0 %o1 %o2 %o3 %o4 : 5 integer results buffer registers ! %f0-f15 FP results buffer registers ! %f32-f47 FP block load/store registers func5: ! instruction sequence begins save %sp, -192, %sp ! Force %i0-%i3 to be 64-byte aligned add %i0, 63, %i0 andn %i0, 63, %i0 add %i1, 63, %i1 andn %i1, 63, %i1 add %i2, 63, %i2 andn %i2, 63, %i2 add %i3, 63, %i3 andn %i3, 63, %i3 add %i4, 63, %i4 andn %i4, 63, %i4 add %i5, 63, %i5 andn %i5, 63, %i5 ! Initialize pointer to FP load results area mov %i4, %l1 ! Initialize pointer to integer load results area sethi %hi(0x80000), %o7 or %o7, %lo(0x80000), %o7 add %o7, %l1, %o7 ! Reinitialize i4 to 0. i4 will be used to keep the count of analyzable node info mov 0x0, %i4 ! Initialize %f0-%f62 to 0xdeadbee0deadbee1 sethi %hi(0xdeadbee0), %o5 or %o5, %lo(0xdeadbee0), %o5 stw %o5, [%i5] sethi %hi(0xdeadbee1), %o5 or %o5, %lo(0xdeadbee1), %o5 stw %o5, [%i5+4] ldd [%i5], %f0 fmovd %f0, %f2 fmovd %f0, %f4 fmovd %f0, %f6 fmovd %f0, %f8 fmovd %f0, %f10 fmovd %f0, %f12 fmovd %f0, %f14 fmovd %f0, %f16 fmovd %f0, %f18 fmovd %f0, %f20 fmovd %f0, %f22 fmovd %f0, %f24 fmovd %f0, %f26 fmovd %f0, %f28 fmovd %f0, %f30 fmovd %f0, %f32 fmovd %f0, %f34 fmovd %f0, %f36 fmovd %f0, %f38 fmovd %f0, %f40 fmovd %f0, %f42 fmovd %f0, %f44 fmovd %f0, %f46 fmovd %f0, %f48 fmovd %f0, %f50 fmovd %f0, %f52 fmovd %f0, %f54 fmovd %f0, %f56 fmovd %f0, %f58 fmovd %f0, %f60 fmovd %f0, %f62 ! Signature for extract_loads script to start extracting load values for this stream sethi %hi(0x05deade1), %o5 or %o5, %lo(0x05deade1), %o5 stw %o5, [%i5] ld [%i5], %f16 ! Initialize running integer counter in register %l4 sethi %hi(0x2800001), %l4 or %l4, %lo(0x2800001), %l4 ! Initialize running FP counter in register %f16 sethi %hi(0x42000001), %o5 or %o5, %lo(0x42000001), %o5 stw %o5, [%i5] ld [%i5], %f16 ! Initialize FP counter increment value in register %f17 (constant) sethi %hi(0x36800000), %o5 or %o5, %lo(0x36800000), %o5 stw %o5, [%i5] ld [%i5], %f17 ! Initialize LFSR to 0xb71^4 sethi %hi(0xb71), %l0 or %l0, %lo(0xb71), %l0 mulx %l0, %l0, %l0 mulx %l0, %l0, %l0 BEGIN_NODES5: ! Test instruction sequence for ISTREAM 5 begins P2226: !_MEMBAR (FP) (Loop entry) (CBR) sethi %hi(0x3), %l2 or %l2, %lo(0x3), %l2 loop_entry_5_0: ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2226 nop RET2226: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2227: !_BST [5] (maybe <- 0x42000001) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 64 ] %asi P2228: !_MEMBAR (FP) (Branch target of P2399) membar #StoreLoad ba P2229 nop TARGET2399: ba RET2399 nop P2229: !_BLD [12] (FP) (CBR) (Secondary ctx) (Branch target of P2591) wr %g0, 0xf1, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f0 membar #Sync ! 3 addresses covered fmovd %f8, %f2 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2229 nop RET2229: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P2230 nop TARGET2591: ba RET2591 nop P2230: !_MEMBAR (FP) (Secondary ctx) P2231: !_BST [13] (maybe <- 0x42000003) (FP) (Secondary ctx) (Branch target of P2621) wr %g0, 0xf1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi ba P2232 nop TARGET2621: ba RET2621 nop P2232: !_MEMBAR (FP) (Secondary ctx) (Branch target of P2563) membar #StoreLoad ba P2233 nop TARGET2563: ba RET2563 nop P2233: !_ST [32] (maybe <- 0x2800001) (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stwa %l4, [%i3 + 256] %asi add %l4, 1, %l4 P2234: !_MEMBAR (FP) membar #StoreLoad P2235: !_BLD [33] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 P2236: !_MEMBAR (FP) (Branch target of P2309) ba P2237 nop TARGET2309: ba RET2309 nop P2237: !_REPLACEMENT [27] (Int) (CBR) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %o5 ld [%i3+160], %l6 st %l6, [%i3+160] add %i3, %o5, %l3 ld [%l3+160], %l6 st %l6, [%l3+160] add %l3, %o5, %l3 ld [%l3+160], %l6 st %l6, [%l3+160] add %l3, %o5, %l3 ld [%l3+160], %l6 st %l6, [%l3+160] add %l3, %o5, %l3 ld [%l3+160], %l6 st %l6, [%l3+160] add %l3, %o5, %l3 ld [%l3+160], %l6 st %l6, [%l3+160] add %l3, %o5, %l3 ld [%l3+160], %l6 st %l6, [%l3+160] add %l3, %o5, %l3 ld [%l3+160], %l6 st %l6, [%l3+160] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2237 nop RET2237: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2238: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P2239: !_BLD [17] (FP) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f40, %f4 P2240: !_MEMBAR (FP) (Secondary ctx) P2241: !_REPLACEMENT [23] (Int) (CBR) (Nucleus ctx) (Branch target of P2379) wr %g0, 0x4, %asi sethi %hi(0x2000), %o5 ld [%i3+32], %l6 st %l6, [%i3+32] add %i3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2241 nop RET2241: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P2242 nop TARGET2379: ba RET2379 nop P2242: !_MEMBAR (FP) (Branch target of P2365) membar #StoreLoad ba P2243 nop TARGET2365: ba RET2365 nop P2243: !_BLD [20] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2243 nop RET2243: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2244: !_MEMBAR (FP) (CBR) (Branch target of P2237) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2244 nop RET2244: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P2245 nop TARGET2237: ba RET2237 nop P2245: !_BST [10] (maybe <- 0x42000006) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i1 + 64 ] %asi P2246: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2246 nop RET2246: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2247: !_ST [20] (maybe <- 0x42000007) (FP) (CBR) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 256 ] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2247 nop RET2247: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2248: !_PREFETCH [11] (Int) (LE) (Branch target of P2491) wr %g0, 0x88, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetcha [%i2 + 0] %asi, 1 ba P2249 nop TARGET2491: ba RET2491 nop P2249: !_ST [31] (maybe <- 0x2800002) (Int) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stw %l4, [%i3 + 192 ] add %l4, 1, %l4 P2250: !_LD [26] (FP) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lda [%i2 + 128] %asi, %f6 ! 1 addresses covered P2251: !_MEMBAR (FP) membar #StoreLoad P2252: !_BLD [20] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 P2253: !_MEMBAR (FP) (CBR) (Branch target of P2525) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2253 nop RET2253: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P2254 nop TARGET2525: ba RET2525 nop P2254: !_PREFETCH [7] (Int) (Nucleus ctx) wr %g0, 0x4, %asi prefetcha [%i0 + 128] %asi, 1 P2255: !_MEMBAR (FP) P2256: !_BST [15] (maybe <- 0x42000008) (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 128 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2256 nop RET2256: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2257: !_MEMBAR (FP) P2258: !_BSTC [0] (maybe <- 0x42000009) (FP) (Branch target of P2600) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi ba P2259 nop TARGET2600: ba RET2600 nop P2259: !_MEMBAR (FP) membar #StoreLoad P2260: !_REPLACEMENT [13] (Int) (CBR) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+32], %l7 st %l7, [%i3+32] add %i3, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2260 nop RET2260: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2261: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2261 nop RET2261: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2262: !_BST [11] (maybe <- 0x4200000e) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P2263: !_MEMBAR (FP) membar #StoreLoad P2264: !_ST [20] (maybe <- 0x2800003) (Int) (Branch target of P2340) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 stw %l4, [%i2 + 256 ] add %l4, 1, %l4 ba P2265 nop TARGET2340: ba RET2340 nop P2265: !_MEMBAR (FP) membar #StoreLoad P2266: !_BLD [10] (FP) wr %g0, 0xf0, %asi ldda [%i1 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f8 P2267: !_MEMBAR (FP) P2268: !_REPLACEMENT [2] (Int) sethi %hi(0x2000), %o5 ld [%i3+8], %l6 st %l6, [%i3+8] add %i3, %o5, %l3 ld [%l3+8], %l6 st %l6, [%l3+8] add %l3, %o5, %l3 ld [%l3+8], %l6 st %l6, [%l3+8] add %l3, %o5, %l3 ld [%l3+8], %l6 st %l6, [%l3+8] add %l3, %o5, %l3 ld [%l3+8], %l6 st %l6, [%l3+8] add %l3, %o5, %l3 ld [%l3+8], %l6 st %l6, [%l3+8] add %l3, %o5, %l3 ld [%l3+8], %l6 st %l6, [%l3+8] add %l3, %o5, %l3 ld [%l3+8], %l6 st %l6, [%l3+8] P2269: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P2270: !_BLD [5] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f9 fmovd %f40, %f10 P2271: !_MEMBAR (FP) (Secondary ctx) P2272: !_PREFETCH [5] (Int) (Nucleus ctx) wr %g0, 0x4, %asi prefetcha [%i0 + 64] %asi, 1 P2273: !_ST [13] (maybe <- 0x42000011) (FP) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i3 + 32 ] %asi P2274: !_REPLACEMENT [7] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l6 ld [%i2+128], %o5 st %o5, [%i2+128] add %i2, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] P2275: !_LD [11] (Int) (CBR) lduw [%i3 + 0], %o0 ! move %o0(lower) -> %o0(upper) sllx %o0, 32, %o0 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2275 nop RET2275: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2276: !_ST [12] (maybe <- 0x2800004) (Int) (Secondary ctx) wr %g0, 0x81, %asi stwa %l4, [%i3 + 4] %asi add %l4, 1, %l4 P2277: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2277 nop RET2277: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2278: !_BLD [31] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 192] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 P2279: !_MEMBAR (FP) P2280: !_BST [20] (maybe <- 0x42000012) (FP) (CBR) (Branch target of P2455) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 256 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2280 nop RET2280: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P2281 nop TARGET2455: ba RET2455 nop P2281: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2281 nop RET2281: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2282: !_REPLACEMENT [19] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+0], %l7 st %l7, [%i3+0] add %i3, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] P2283: !_MEMBAR (FP) (Branch target of P2326) ba P2284 nop TARGET2326: ba RET2326 nop P2284: !_BST [17] (maybe <- 0x42000013) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f40 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 64 ] %asi P2285: !_MEMBAR (FP) P2286: !_BST [16] (maybe <- 0x42000014) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f36 membar #Sync stda %f32, [%i2 + 0 ] %asi P2287: !_MEMBAR (FP) membar #StoreLoad P2288: !_ST [11] (maybe <- 0x2800005) (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stwa %l4, [%i3 + 0] %asi add %l4, 1, %l4 P2289: !_REPLACEMENT [17] (Int) (Branch target of P2298) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+96], %l7 st %l7, [%i2+96] add %i2, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] ba P2290 nop TARGET2298: ba RET2298 nop P2290: !_REPLACEMENT [17] (Int) (CBR) sethi %hi(0x2000), %o5 ld [%i2+96], %l6 st %l6, [%i2+96] add %i2, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2290 nop RET2290: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2291: !_MEMBAR (FP) (Secondary ctx) P2292: !_BSTC [14] (maybe <- 0x42000015) (FP) (Secondary ctx) wr %g0, 0xe1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 64 ] %asi P2293: !_MEMBAR (FP) (Secondary ctx) P2294: !_BST [1] (maybe <- 0x42000016) (FP) (CBR) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2294 nop RET2294: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2295: !_MEMBAR (FP) membar #StoreLoad P2296: !_REPLACEMENT [13] (Int) sethi %hi(0x2000), %l7 ld [%i2+32], %l3 st %l3, [%i2+32] add %i2, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] P2297: !_MEMBAR (FP) P2298: !_BST [20] (maybe <- 0x4200001b) (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 256 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2298 nop RET2298: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2299: !_MEMBAR (FP) membar #StoreLoad P2300: !_BLD [8] (FP) wr %g0, 0xf0, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f12 fmovd %f40, %f18 fmovs %f18, %f13 P2301: !_MEMBAR (FP) (CBR) (Branch target of P2406) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2301 nop RET2301: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P2302 nop TARGET2406: ba RET2406 nop P2302: !_LD [27] (FP) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ld [%i2 + 160], %f14 ! 1 addresses covered P2303: !_MEMBAR (FP) (Branch target of P2275) membar #StoreLoad ba P2304 nop TARGET2275: ba RET2275 nop P2304: !_BLD [8] (FP) (Branch target of P2441) wr %g0, 0xf0, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f40, %f0 ba P2305 nop TARGET2441: ba RET2441 nop P2305: !_MEMBAR (FP) P2306: !_REPLACEMENT [25] (Int) (CBR) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+96], %l3 st %l3, [%i3+96] add %i3, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2306 nop RET2306: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2307: !_REPLACEMENT [5] (Int) sethi %hi(0x2000), %l7 ld [%i3+64], %l3 st %l3, [%i3+64] add %i3, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] P2308: !_REPLACEMENT [15] (Int) sethi %hi(0x2000), %l6 ld [%i3+128], %o5 st %o5, [%i3+128] add %i3, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] P2309: !_MEMBAR (FP) (CBR) (Secondary ctx) (Branch target of P2552) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2309 nop RET2309: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P2310 nop TARGET2552: ba RET2552 nop P2310: !_BLD [0] (FP) (CBR) (Secondary ctx) (Branch target of P2322) wr %g0, 0xf1, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 fmovs %f19, %f2 fmovd %f34, %f18 fmovs %f18, %f3 fmovd %f36, %f4 fmovd %f40, %f18 fmovs %f18, %f5 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2310 nop RET2310: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P2311 nop TARGET2322: ba RET2322 nop P2311: !_MEMBAR (FP) (CBR) (Secondary ctx) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2311 nop RET2311: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2312: !_LD [15] (Int) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduw [%i2 + 128], %l3 ! move %l3(lower) -> %o0(lower) or %l3, %o0, %o0 P2313: !_PREFETCH [0] (Int) (CBR) prefetch [%i0 + 0], 1 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2313 nop RET2313: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2314: !_MEMBAR (FP) membar #StoreLoad P2315: !_BLD [22] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f6 fmovd %f40, %f8 P2316: !_MEMBAR (FP) P2317: !_BST [10] (maybe <- 0x4200001c) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i1 + 64 ] %asi P2318: !_MEMBAR (FP) membar #StoreLoad P2319: !_LD [13] (Int) lduw [%i2 + 32], %o1 ! move %o1(lower) -> %o1(upper) sllx %o1, 32, %o1 P2320: !_MEMBAR (FP) (Branch target of P2356) ba P2321 nop TARGET2356: ba RET2356 nop P2321: !_BST [9] (maybe <- 0x4200001d) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i1 + 0 ] %asi P2322: !_MEMBAR (FP) (CBR) (Branch target of P2533) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2322 nop RET2322: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P2323 nop TARGET2533: ba RET2533 nop P2323: !_REPLACEMENT [25] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %o5 ld [%i2+96], %l6 st %l6, [%i2+96] add %i2, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] add %l3, %o5, %l3 ld [%l3+96], %l6 st %l6, [%l3+96] P2324: !_LD [4] (FP) ld [%i0 + 32], %f9 ! 1 addresses covered P2325: !_LD [14] (Int) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lduw [%i3 + 64], %o5 ! move %o5(lower) -> %o1(lower) or %o5, %o1, %o1 P2326: !_PREFETCH [18] (Int) (CBR) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetcha [%i2 + 128] %asi, 1 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2326 nop RET2326: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2327: !_IDC_FLIP [11] (Int) IDC_FLIP(2327, 23339, 5, 0x44000000, 0x0, %i3, 0x0, %l6, %l7, %o5, %l3) P2328: !_ST [14] (maybe <- 0x4200001f) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 64 ] P2329: !_MEMBAR (FP) P2330: !_BST [25] (maybe <- 0x42000020) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 64 ] %asi P2331: !_MEMBAR (FP) membar #StoreLoad P2332: !_ST [3] (maybe <- 0x2800006) (Int) (CBR) (Secondary ctx) wr %g0, 0x81, %asi stwa %l4, [%i0 + 16] %asi add %l4, 1, %l4 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2332 nop RET2332: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2333: !_REPLACEMENT [9] (Int) (Nucleus ctx) (Branch target of P2310) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %o5 ld [%i2+32], %l6 st %l6, [%i2+32] add %i2, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] ba P2334 nop TARGET2310: ba RET2310 nop P2334: !_REPLACEMENT [16] (Int) sethi %hi(0x2000), %l7 ld [%i2+16], %l3 st %l3, [%i2+16] add %i2, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] P2335: !_PREFETCH [25] (Int) prefetch [%i3 + 96], 1 P2336: !_MEMBAR (FP) membar #StoreLoad P2337: !_BLD [8] (FP) (CBR) (Branch target of P2548) wr %g0, 0xf0, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f10 fmovd %f40, %f18 fmovs %f18, %f11 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2337 nop RET2337: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P2338 nop TARGET2548: ba RET2548 nop P2338: !_MEMBAR (FP) P2339: !_LD [21] (FP) ld [%i3 + 0], %f12 ! 1 addresses covered P2340: !_MEMBAR (FP) (CBR) (Branch target of P2557) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2340 nop RET2340: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P2341 nop TARGET2557: ba RET2557 nop P2341: !_BLD [15] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2341 nop RET2341: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2342: !_MEMBAR (FP) P2343: !_PREFETCH [3] (Int) prefetch [%i0 + 16], 1 P2344: !_MEMBAR (FP) membar #StoreLoad P2345: !_BLD [17] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f40, %f14 P2346: !_MEMBAR (FP) P2347: !_BST [31] (maybe <- 0x42000022) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 192 ] %asi P2348: !_MEMBAR (FP) membar #StoreLoad P2349: !_ST [9] (maybe <- 0x42000023) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i1 + 32 ] P2350: !_PREFETCH [8] (Int) (Secondary ctx) wr %g0, 0x81, %asi prefetcha [%i1 + 0] %asi, 1 P2351: !_PREFETCH [22] (Int) (Branch target of P2400) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 4], 1 ba P2352 nop TARGET2400: ba RET2400 nop P2352: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P2353: !_BLD [32] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i3 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- P2354: !_MEMBAR (FP) (Secondary ctx) (Branch target of P2521) ba P2355 nop TARGET2521: ba RET2521 nop P2355: !_REPLACEMENT [18] (Int) (Branch target of P2474) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+128], %l3 st %l3, [%i3+128] add %i3, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] ba P2356 nop TARGET2474: ba RET2474 nop P2356: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2356 nop RET2356: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2357: !_BST [13] (maybe <- 0x42000024) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P2358: !_MEMBAR (FP) membar #StoreLoad P2359: !_BLD [3] (FP) (Branch target of P2630) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f0 membar #Sync ! 5 addresses covered fmovs %f4, %f3 fmovd %f8, %f4 ba P2360 nop TARGET2630: ba RET2630 nop P2360: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2360 nop RET2360: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2361: !_BSTC [0] (maybe <- 0x42000027) (FP) (Secondary ctx) wr %g0, 0xe1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P2362: !_MEMBAR (FP) (Secondary ctx) (Branch target of P2311) membar #StoreLoad ba P2363 nop TARGET2311: ba RET2311 nop P2363: !_REPLACEMENT [13] (Int) sethi %hi(0x2000), %l6 ld [%i3+32], %o5 st %o5, [%i3+32] add %i3, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] P2364: !_MEMBAR (FP) membar #StoreLoad P2365: !_BLD [18] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2365 nop RET2365: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2366: !_MEMBAR (FP) P2367: !_BLD [29] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f6 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2367 nop RET2367: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2368: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2368 nop RET2368: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2369: !_LD [14] (Int) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lduw [%i3 + 64], %o2 ! move %o2(lower) -> %o2(upper) sllx %o2, 32, %o2 P2370: !_LD [26] (Int) (CBR) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduw [%i2 + 128], %l7 ! move %l7(lower) -> %o2(lower) or %l7, %o2, %o2 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2370 nop RET2370: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2371: !_REPLACEMENT [1] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+4], %l7 st %l7, [%i3+4] add %i3, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] P2372: !_MEMBAR (FP) (Secondary ctx) P2373: !_BSTC [14] (maybe <- 0x4200002c) (FP) (Secondary ctx) wr %g0, 0xe1, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 64 ] %asi P2374: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P2375: !_BLD [3] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 fmovs %f19, %f8 fmovd %f34, %f18 fmovs %f18, %f9 fmovd %f36, %f10 fmovd %f40, %f18 fmovs %f18, %f11 P2376: !_MEMBAR (FP) (Secondary ctx) P2377: !_LD [11] (Int) lduw [%i2 + 0], %o3 ! move %o3(lower) -> %o3(upper) sllx %o3, 32, %o3 P2378: !_MEMBAR (FP) P2379: !_BSTC [17] (maybe <- 0x4200002d) (FP) (CBR) wr %g0, 0xe0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f40 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2379 nop RET2379: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2380: !_MEMBAR (FP) (Branch target of P2306) ba P2381 nop TARGET2306: ba RET2306 nop P2381: !_BSTC [32] (maybe <- 0x4200002e) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 256 ] %asi P2382: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2382 nop RET2382: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2383: !_BLD [23] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f12 fmovd %f40, %f14 P2384: !_MEMBAR (FP) (Branch target of P2229) ba P2385 nop TARGET2229: ba RET2229 nop P2385: !_ST [13] (maybe <- 0x2800007) (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 stwa %l4, [%i2 + 32] %asi add %l4, 1, %l4 P2386: !_LD [26] (Int) lduw [%i3 + 128], %l3 ! move %l3(lower) -> %o3(lower) or %l3, %o3, %o3 P2387: !_REPLACEMENT [4] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l6 ld [%i3+32], %o5 st %o5, [%i3+32] add %i3, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] P2388: !_MEMBAR (FP) (Branch target of P2337) membar #StoreLoad ba P2389 nop TARGET2337: ba RET2337 nop P2389: !_BLD [32] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- P2390: !_MEMBAR (FP) P2391: !_ST [11] (maybe <- 0x2800008) (Int) (Branch target of P2520) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stw %l4, [%i3 + 0 ] add %l4, 1, %l4 ba P2392 nop TARGET2520: ba RET2520 nop P2392: !_REPLACEMENT [7] (Int) (Branch target of P2301) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %o5 ld [%i2+128], %l6 st %l6, [%i2+128] add %i2, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] ba P2393 nop TARGET2301: ba RET2301 nop P2393: !_PREFETCH [26] (Int) (CBR) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 128], 1 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2393 nop RET2393: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2394: !_MEMBAR (FP) P2395: !_BSTC [10] (maybe <- 0x4200002f) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i1 + 64 ] %asi P2396: !_MEMBAR (FP) P2397: !_BSTC [33] (maybe <- 0x42000030) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 0 ] %asi P2398: !_MEMBAR (FP) (Branch target of P2537) membar #StoreLoad ba P2399 nop TARGET2537: ba RET2537 nop P2399: !_ST [18] (maybe <- 0x42000031) (FP) (CBR) (Branch target of P2508) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 128 ] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2399 nop RET2399: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P2400 nop TARGET2508: ba RET2508 nop P2400: !_REPLACEMENT [8] (Int) (CBR) (Branch target of P2370) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l6 ld [%i2+0], %o5 st %o5, [%i2+0] add %i2, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2400 nop RET2400: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P2401 nop TARGET2370: ba RET2370 nop P2401: !_MEMBAR (FP) P2402: !_BST [19] (maybe <- 0x42000032) (FP) (CBR) (Branch target of P2405) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2402 nop RET2402: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P2403 nop TARGET2405: ba RET2405 nop P2403: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2403 nop RET2403: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2404: !_BSTC [25] (maybe <- 0x42000033) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 64 ] %asi P2405: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2405 nop RET2405: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2406: !_BLD [17] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 64] %asi, %f0 membar #Sync ! 1 addresses covered fmovd %f8, %f0 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2406 nop RET2406: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2407: !_MEMBAR (FP) P2408: !_REPLACEMENT [23] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %o5 ld [%i2+32], %l6 st %l6, [%i2+32] add %i2, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] P2409: !_REPLACEMENT [14] (Int) (CBR) sethi %hi(0x2000), %l7 ld [%i2+64], %l3 st %l3, [%i2+64] add %i2, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2409 nop RET2409: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2410: !_MEMBAR (FP) membar #StoreLoad P2411: !_BLD [27] (FP) (Branch target of P2246) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 fmovd %f40, %f2 ba P2412 nop TARGET2246: ba RET2246 nop P2412: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2412 nop RET2412: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2413: !_BLD [13] (FP) (Branch target of P2486) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 fmovs %f19, %f4 fmovd %f40, %f18 fmovs %f18, %f5 ba P2414 nop TARGET2486: ba RET2486 nop P2414: !_MEMBAR (FP) P2415: !_REPLACEMENT [30] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %o5 ld [%i3+128], %l6 st %l6, [%i3+128] add %i3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] P2416: !_MEMBAR (FP) (Branch target of P2368) membar #StoreLoad ba P2417 nop TARGET2368: ba RET2368 nop P2417: !_BLD [15] (FP) (Branch target of P2460) wr %g0, 0xf0, %asi ldda [%i2 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f6 ba P2418 nop TARGET2460: ba RET2460 nop P2418: !_MEMBAR (FP) P2419: !_BSTC [3] (maybe <- 0x42000035) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P2420: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2420 nop RET2420: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2421: !_BSTC [26] (maybe <- 0x4200003a) (FP) (CBR) wr %g0, 0xe0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 128 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2421 nop RET2421: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2422: !_MEMBAR (FP) membar #StoreLoad P2423: !_REPLACEMENT [3] (Int) (Branch target of P2503) sethi %hi(0x2000), %l7 ld [%i3+16], %l3 st %l3, [%i3+16] add %i3, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] ba P2424 nop TARGET2503: ba RET2503 nop P2424: !_ST [21] (maybe <- 0x2800009) (Int) stw %l4, [%i2 + 0 ] add %l4, 1, %l4 P2425: !_IDC_FLIP [29] (Int) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 IDC_FLIP(2425, 20594, 5, 0x46000040, 0x40, %i3, 0x40, %l6, %l7, %o5, %l3) P2426: !_MEMBAR (FP) (Branch target of P2499) ba P2427 nop TARGET2499: ba RET2499 nop P2427: !_BSTC [4] (maybe <- 0x4200003c) (FP) (CBR) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2427 nop RET2427: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2428: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2428 nop RET2428: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2429: !_LD [33] (FP) sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ld [%i2 + 0], %f7 ! 1 addresses covered P2430: !_MEMBAR (FP) membar #StoreLoad P2431: !_BLD [6] (FP) (Branch target of P2294) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f8 fmovd %f40, %f18 fmovs %f18, %f9 ba P2432 nop TARGET2294: ba RET2294 nop P2432: !_MEMBAR (FP) P2433: !_ST [18] (maybe <- 0x280000a) (Int) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stw %l4, [%i3 + 128 ] add %l4, 1, %l4 P2434: !_LD [8] (Int) (Secondary ctx) (Branch target of P2428) wr %g0, 0x81, %asi lduwa [%i1 + 0] %asi, %o4 ! move %o4(lower) -> %o4(upper) sllx %o4, 32, %o4 ba P2435 nop TARGET2428: ba RET2428 nop P2435: !_MEMBAR (FP) (Branch target of P2469) ba P2436 nop TARGET2469: ba RET2469 nop P2436: !_BST [3] (maybe <- 0x42000041) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P2437: !_MEMBAR (FP) P2438: !_BST [27] (maybe <- 0x42000046) (FP) (Branch target of P2341) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 128 ] %asi ba P2439 nop TARGET2341: ba RET2341 nop P2439: !_MEMBAR (FP) membar #StoreLoad P2440: !_LD [5] (FP) ld [%i0 + 64], %f10 ! 1 addresses covered P2441: !_MEMBAR (FP) (CBR) (Secondary ctx) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2441 nop RET2441: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2442: !_BLD [16] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i3 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f36, %f18 fmovs %f18, %f11 P2443: !_MEMBAR (FP) (Secondary ctx) P2444: !_BSTC [15] (maybe <- 0x42000048) (FP) (Secondary ctx) (Branch target of P2538) wr %g0, 0xe1, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 128 ] %asi ba P2445 nop TARGET2538: ba RET2538 nop P2445: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P2446: !_PREFETCH [15] (Int) (CBR) (Secondary ctx) (Branch target of P2277) wr %g0, 0x81, %asi prefetcha [%i3 + 128] %asi, 1 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2446 nop RET2446: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P2447 nop TARGET2277: ba RET2277 nop P2447: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P2448: !_BLD [31] (FP) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 192] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f12 P2449: !_MEMBAR (FP) (CBR) (Secondary ctx) (Branch target of P2393) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2449 nop RET2449: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P2450 nop TARGET2393: ba RET2393 nop P2450: !_BLD [29] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 P2451: !_MEMBAR (FP) P2452: !_PREFETCH [31] (Int) prefetch [%i2 + 192], 1 P2453: !_ST [20] (maybe <- 0x280000b) (Int) (Branch target of P2585) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stw %l4, [%i3 + 256 ] add %l4, 1, %l4 ba P2454 nop TARGET2585: ba RET2585 nop P2454: !_IDC_FLIP [0] (Int) IDC_FLIP(2454, 23269, 5, 0x43000000, 0x0, %i0, 0x0, %l6, %l7, %o5, %l3) P2455: !_LD [9] (FP) (CBR) ld [%i1 + 32], %f14 ! 1 addresses covered ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2455 nop RET2455: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2456: !_MEMBAR (FP) membar #StoreLoad P2457: !_BLD [32] (FP) (Branch target of P2420) wr %g0, 0xf0, %asi ldda [%i2 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- ba P2458 nop TARGET2420: ba RET2420 nop P2458: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2458 nop RET2458: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2459: !_LD [25] (FP) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ld [%i2 + 96], %f0 ! 1 addresses covered P2460: !_ST [19] (maybe <- 0x280000c) (Int) (CBR) stw %l4, [%i3 + 0 ] add %l4, 1, %l4 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2460 nop RET2460: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2461: !_ST [1] (maybe <- 0x280000d) (Int) (Branch target of P2403) stw %l4, [%i0 + 4 ] add %l4, 1, %l4 ba P2462 nop TARGET2403: ba RET2403 nop P2462: !_PREFETCH [31] (Int) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 192], 1 P2463: !_LD [2] (FP) (Secondary ctx) wr %g0, 0x81, %asi lda [%i0 + 8] %asi, %f1 ! 1 addresses covered P2464: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2464 nop RET2464: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2465: !_BSTC [24] (maybe <- 0x42000049) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 64 ] %asi P2466: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2466 nop RET2466: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2467: !_BLD [33] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f2 P2468: !_MEMBAR (FP) P2469: !_BSTC [32] (maybe <- 0x4200004b) (FP) (CBR) (Secondary ctx) wr %g0, 0xe1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 256 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2469 nop RET2469: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2470: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P2471: !_ST [7] (maybe <- 0x4200004c) (FP) (Nucleus ctx) (Branch target of P2409) wr %g0, 0x4, %asi ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i0 + 128 ] %asi ba P2472 nop TARGET2409: ba RET2409 nop P2472: !_REPLACEMENT [22] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+4], %l3 st %l3, [%i3+4] add %i3, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] P2473: !_MEMBAR (FP) membar #StoreLoad P2474: !_BLD [8] (FP) (CBR) (Branch target of P2256) wr %g0, 0xf0, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 fmovd %f40, %f4 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2474 nop RET2474: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P2475 nop TARGET2256: ba RET2256 nop P2475: !_MEMBAR (FP) P2476: !_BLD [11] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 fmovs %f19, %f6 fmovd %f40, %f18 fmovs %f18, %f7 P2477: !_MEMBAR (FP) (Branch target of P2616) ba P2478 nop TARGET2616: ba RET2616 nop P2478: !_BLD [8] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f8 fmovd %f40, %f18 fmovs %f18, %f9 P2479: !_MEMBAR (FP) (Secondary ctx) P2480: !_ST [15] (maybe <- 0x280000e) (Int) stw %l4, [%i2 + 128 ] add %l4, 1, %l4 P2481: !_MEMBAR (FP) (Branch target of P2466) membar #StoreLoad ba P2482 nop TARGET2466: ba RET2466 nop P2482: !_BLD [29] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f10 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2482 nop RET2482: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2483: !_MEMBAR (FP) P2484: !_BLD [22] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 fmovs %f19, %f12 fmovd %f40, %f18 fmovs %f18, %f13 P2485: !_MEMBAR (FP) P2486: !_BLD [18] (FP) (CBR) (Branch target of P2226) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f14 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2486 nop RET2486: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P2487 nop TARGET2226: ba RET2226 nop P2487: !_MEMBAR (FP) P2488: !_PREFETCH [16] (Int) (CBR) prefetch [%i3 + 16], 1 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2488 nop RET2488: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2489: !_LD [30] (FP) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ld [%i2 + 128], %f15 ! 1 addresses covered !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- P2490: !_ST [19] (maybe <- 0x280000f) (Int) (Branch target of P2253) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stw %l4, [%i3 + 0 ] add %l4, 1, %l4 ba P2491 nop TARGET2253: ba RET2253 nop P2491: !_LD [26] (Int) (CBR) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduw [%i2 + 128], %l3 ! move %l3(lower) -> %o4(lower) or %l3, %o4, %o4 !---- flushing int results buffer---- mov %o0, %l5 mov %o1, %l5 mov %o2, %l5 mov %o3, %l5 mov %o4, %l5 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2491 nop RET2491: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2492: !_REPLACEMENT [28] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+0], %l3 st %l3, [%i3+0] add %i3, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] P2493: !_ST [29] (maybe <- 0x2800010) (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 stwa %l4, [%i2 + 64] %asi add %l4, 1, %l4 P2494: !_LD [28] (Int) (LE) wr %g0, 0x88, %asi lduwa [%i2 + 0] %asi, %o0 ! move %o0(lower) -> %o0(upper) sllx %o0, 32, %o0 P2495: !_LD [1] (Int) lduw [%i0 + 4], %o5 ! move %o5(lower) -> %o0(lower) or %o5, %o0, %o0 P2496: !_ST [16] (maybe <- 0x2800011) (Int) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stw %l4, [%i3 + 16 ] add %l4, 1, %l4 P2497: !_ST [20] (maybe <- 0x4200004d) (FP) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i2 + 256 ] %asi P2498: !_MEMBAR (FP) (Branch target of P2544) ba P2499 nop TARGET2544: ba RET2544 nop P2499: !_BSTC [1] (maybe <- 0x4200004e) (FP) (CBR) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2499 nop RET2499: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2500: !_MEMBAR (FP) membar #StoreLoad P2501: !_BLD [8] (FP) wr %g0, 0xf0, %asi ldda [%i1 + 0] %asi, %f0 membar #Sync ! 2 addresses covered fmovs %f8, %f1 P2502: !_MEMBAR (FP) P2503: !_REPLACEMENT [5] (Int) (CBR) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+64], %l3 st %l3, [%i3+64] add %i3, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2503 nop RET2503: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2504: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P2505: !_BLD [21] (FP) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f2 fmovd %f40, %f4 P2506: !_MEMBAR (FP) (Secondary ctx) P2507: !_ST [18] (maybe <- 0x42000053) (FP) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 128 ] P2508: !_REPLACEMENT [18] (Int) (CBR) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l6 ld [%i2+128], %o5 st %o5, [%i2+128] add %i2, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2508 nop RET2508: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2509: !_MEMBAR (FP) P2510: !_BST [11] (maybe <- 0x42000054) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P2511: !_MEMBAR (FP) (Branch target of P2570) membar #StoreLoad ba P2512 nop TARGET2570: ba RET2570 nop P2512: !_BLD [32] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 P2513: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2513 nop RET2513: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2514: !_BLD [27] (FP) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f6 fmovd %f40, %f18 fmovs %f18, %f7 P2515: !_MEMBAR (FP) (Secondary ctx) P2516: !_BLD [0] (FP) (Branch target of P2382) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f8 fmovd %f34, %f10 fmovd %f36, %f18 fmovs %f18, %f11 fmovd %f40, %f12 ba P2517 nop TARGET2382: ba RET2382 nop P2517: !_MEMBAR (FP) P2518: !_LD [21] (FP) (Branch target of P2612) ld [%i3 + 0], %f13 ! 1 addresses covered ba P2519 nop TARGET2612: ba RET2612 nop P2519: !_IDC_FLIP [23] (Int) IDC_FLIP(2519, 5037, 5, 0x45800020, 0x20, %i3, 0x20, %l6, %l7, %o5, %l3) P2520: !_ST [3] (maybe <- 0x42000057) (FP) (CBR) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i0 + 16 ] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2520 nop RET2520: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2521: !_ST [28] (maybe <- 0x42000058) (FP) (CBR) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 0 ] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2521 nop RET2521: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2522: !_ST [27] (maybe <- 0x42000059) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 160 ] P2523: !_REPLACEMENT [18] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+128], %l7 st %l7, [%i2+128] add %i2, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] P2524: !_LD [29] (FP) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ld [%i3 + 64], %f14 ! 1 addresses covered P2525: !_IDC_FLIP [20] (Int) (CBR) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 IDC_FLIP(2525, 30167, 5, 0x45000100, 0x100, %i2, 0x100, %l6, %l7, %o5, %l3) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2525 nop RET2525: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2526: !_LD [3] (Int) lduw [%i0 + 16], %o1 ! move %o1(lower) -> %o1(upper) sllx %o1, 32, %o1 P2527: !_PREFETCH [14] (Int) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 64], 1 P2528: !_ST [12] (maybe <- 0x2800012) (Int) (CBR) stw %l4, [%i3 + 4 ] add %l4, 1, %l4 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2528 nop RET2528: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2529: !_PREFETCH [21] (Int) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 0], 1 P2530: !_REPLACEMENT [16] (Int) (CBR) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+16], %l7 st %l7, [%i3+16] add %i3, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2530 nop RET2530: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2531: !_ST [20] (maybe <- 0x4200005a) (FP) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 256 ] P2532: !_ST [6] (maybe <- 0x2800013) (Int) (Nucleus ctx) wr %g0, 0x4, %asi stwa %l4, [%i0 + 96] %asi add %l4, 1, %l4 P2533: !_REPLACEMENT [4] (Int) (CBR) sethi %hi(0x2000), %l7 ld [%i3+32], %l3 st %l3, [%i3+32] add %i3, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2533 nop RET2533: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2534: !_REPLACEMENT [5] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(0x2000), %l7 ld [%i3+64], %l3 st %l3, [%i3+64] add %i3, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] P2535: !_MEMBAR (FP) P2536: !_BSTC [15] (maybe <- 0x4200005b) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 128 ] %asi P2537: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2537 nop RET2537: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2538: !_ST [22] (maybe <- 0x4200005c) (FP) (CBR) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 4 ] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2538 nop RET2538: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2539: !_ST [16] (maybe <- 0x4200005d) (FP) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 16 ] P2540: !_MEMBAR (FP) (Secondary ctx) P2541: !_BST [21] (maybe <- 0x4200005e) (FP) (Secondary ctx) wr %g0, 0xf1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P2542: !_MEMBAR (FP) (Secondary ctx) P2543: !_BST [5] (maybe <- 0x42000061) (FP) (Branch target of P2367) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 64 ] %asi ba P2544 nop TARGET2367: ba RET2367 nop P2544: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2544 nop RET2544: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2545: !_BLD [0] (FP) (Branch target of P2446) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovs %f19, %f0 fmovd %f34, %f18 fmovs %f18, %f1 fmovd %f36, %f2 fmovd %f40, %f18 fmovs %f18, %f3 ba P2546 nop TARGET2446: ba RET2446 nop P2546: !_MEMBAR (FP) P2547: !_BLD [6] (FP) (Branch target of P2464) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f4 fmovd %f40, %f18 fmovs %f18, %f5 ba P2548 nop TARGET2464: ba RET2464 nop P2548: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2548 nop RET2548: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2549: !_BST [24] (maybe <- 0x42000063) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 64 ] %asi P2550: !_MEMBAR (FP) (Branch target of P2261) membar #StoreLoad ba P2551 nop TARGET2261: ba RET2261 nop P2551: !_REPLACEMENT [21] (Int) (Branch target of P2280) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %o5 ld [%i2+0], %l6 st %l6, [%i2+0] add %i2, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] ba P2552 nop TARGET2280: ba RET2280 nop P2552: !_REPLACEMENT [3] (Int) (CBR) (Branch target of P2427) sethi %hi(0x2000), %l7 ld [%i2+16], %l3 st %l3, [%i2+16] add %i2, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2552 nop RET2552: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P2553 nop TARGET2427: ba RET2427 nop P2553: !_MEMBAR (FP) P2554: !_BST [32] (maybe <- 0x42000065) (FP) (Branch target of P2241) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 256 ] %asi ba P2555 nop TARGET2241: ba RET2241 nop P2555: !_MEMBAR (FP) membar #StoreLoad P2556: !_PREFETCH [30] (Int) prefetch [%i3 + 128], 1 P2557: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2557 nop RET2557: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2558: !_BLD [4] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f6 fmovd %f34, %f8 fmovd %f36, %f18 fmovs %f18, %f9 fmovd %f40, %f10 P2559: !_MEMBAR (FP) P2560: !_BST [14] (maybe <- 0x42000066) (FP) (Branch target of P2488) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 64 ] %asi ba P2561 nop TARGET2488: ba RET2488 nop P2561: !_MEMBAR (FP) membar #StoreLoad P2562: !_BLD [21] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 fmovs %f19, %f12 fmovd %f40, %f18 fmovs %f18, %f13 P2563: !_MEMBAR (FP) (CBR) (Branch target of P2627) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2563 nop RET2563: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P2564 nop TARGET2627: ba RET2627 nop P2564: !_BSTC [24] (maybe <- 0x42000067) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 64 ] %asi P2565: !_MEMBAR (FP) membar #StoreLoad P2566: !_BLD [13] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f14 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f40, %f0 P2567: !_MEMBAR (FP) P2568: !_LD [10] (FP) (Branch target of P2528) ld [%i1 + 64], %f1 ! 1 addresses covered ba P2569 nop TARGET2528: ba RET2528 nop P2569: !_MEMBAR (FP) (Secondary ctx) (Branch target of P2412) membar #StoreLoad ba P2570 nop TARGET2412: ba RET2412 nop P2570: !_BLD [21] (FP) (CBR) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f2 fmovd %f40, %f4 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2570 nop RET2570: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2571: !_MEMBAR (FP) (Secondary ctx) P2572: !_BLD [5] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 fmovd %f40, %f6 P2573: !_MEMBAR (FP) P2574: !_REPLACEMENT [7] (Int) (Branch target of P2449) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l7 ld [%i2+128], %l3 st %l3, [%i2+128] add %i2, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] ba P2575 nop TARGET2449: ba RET2449 nop P2575: !_MEMBAR (FP) (Secondary ctx) P2576: !_BST [21] (maybe <- 0x42000069) (FP) (Secondary ctx) wr %g0, 0xf1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P2577: !_MEMBAR (FP) (Secondary ctx) (Branch target of P2243) membar #StoreLoad ba P2578 nop TARGET2243: ba RET2243 nop P2578: !_BLD [8] (FP) (Branch target of P2360) wr %g0, 0xf0, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 fmovd %f40, %f8 ba P2579 nop TARGET2360: ba RET2360 nop P2579: !_MEMBAR (FP) P2580: !_BSTC [26] (maybe <- 0x4200006c) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 128 ] %asi P2581: !_MEMBAR (FP) P2582: !_BSTC [4] (maybe <- 0x4200006e) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P2583: !_MEMBAR (FP) (Branch target of P2402) membar #StoreLoad ba P2584 nop TARGET2402: ba RET2402 nop P2584: !_BLD [27] (FP) (Branch target of P2530) wr %g0, 0xf0, %asi ldda [%i3 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f9 fmovd %f40, %f10 ba P2585 nop TARGET2530: ba RET2530 nop P2585: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2585 nop RET2585: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2586: !_BLD [29] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 P2587: !_MEMBAR (FP) P2588: !_REPLACEMENT [33] (Int) (Branch target of P2290) sethi %hi(0x2000), %o5 ld [%i2+0], %l6 st %l6, [%i2+0] add %i2, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] ba P2589 nop TARGET2290: ba RET2290 nop P2589: !_MEMBAR (FP) (Branch target of P2458) ba P2590 nop TARGET2458: ba RET2458 nop P2590: !_BST [15] (maybe <- 0x42000073) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 128 ] %asi P2591: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2591 nop RET2591: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2592: !_LD [30] (FP) (Nucleus ctx) wr %g0, 0x4, %asi lda [%i3 + 128] %asi, %f12 ! 1 addresses covered P2593: !_MEMBAR (FP) P2594: !_BST [26] (maybe <- 0x42000074) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 128 ] %asi P2595: !_MEMBAR (FP) P2596: !_BSTC [30] (maybe <- 0x42000076) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 128 ] %asi P2597: !_MEMBAR (FP) membar #StoreLoad P2598: !_REPLACEMENT [2] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+8], %l7 st %l7, [%i3+8] add %i3, %l3, %l6 ld [%l6+8], %l7 st %l7, [%l6+8] add %l6, %l3, %l6 ld [%l6+8], %l7 st %l7, [%l6+8] add %l6, %l3, %l6 ld [%l6+8], %l7 st %l7, [%l6+8] add %l6, %l3, %l6 ld [%l6+8], %l7 st %l7, [%l6+8] add %l6, %l3, %l6 ld [%l6+8], %l7 st %l7, [%l6+8] add %l6, %l3, %l6 ld [%l6+8], %l7 st %l7, [%l6+8] add %l6, %l3, %l6 ld [%l6+8], %l7 st %l7, [%l6+8] P2599: !_MEMBAR (FP) (Branch target of P2244) membar #StoreLoad ba P2600 nop TARGET2244: ba RET2244 nop P2600: !_BLD [18] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2600 nop RET2600: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2601: !_MEMBAR (FP) P2602: !_BLD [21] (FP) (Branch target of P2332) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f14 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f40, %f0 ba P2603 nop TARGET2332: ba RET2332 nop P2603: !_MEMBAR (FP) P2604: !_BLD [4] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 fmovs %f19, %f2 fmovd %f34, %f18 fmovs %f18, %f3 fmovd %f36, %f4 fmovd %f40, %f18 fmovs %f18, %f5 P2605: !_MEMBAR (FP) P2606: !_REPLACEMENT [22] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+4], %l7 st %l7, [%i2+4] add %i2, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] P2607: !_LD [31] (FP) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ld [%i3 + 192], %f6 ! 1 addresses covered P2608: !_MEMBAR (FP) P2609: !_BST [13] (maybe <- 0x42000077) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P2610: !_MEMBAR (FP) membar #StoreLoad P2611: !_BLD [2] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 fmovs %f19, %f8 fmovd %f34, %f18 fmovs %f18, %f9 fmovd %f36, %f10 fmovd %f40, %f18 fmovs %f18, %f11 P2612: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2612 nop RET2612: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2613: !_LD [1] (FP) (Branch target of P2247) ld [%i0 + 4], %f12 ! 1 addresses covered ba P2614 nop TARGET2247: ba RET2247 nop P2614: !_MEMBAR (FP) (Secondary ctx) P2615: !_BSTC [15] (maybe <- 0x4200007a) (FP) (Secondary ctx) wr %g0, 0xe1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 128 ] %asi P2616: !_MEMBAR (FP) (CBR) (Secondary ctx) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2616 nop RET2616: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2617: !_ST [8] (maybe <- 0x4200007b) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i1 + 0 ] P2618: !_MEMBAR (FP) P2619: !_BSTC [11] (maybe <- 0x4200007c) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P2620: !_MEMBAR (FP) membar #StoreLoad P2621: !_ST [27] (maybe <- 0x4200007f) (FP) (CBR) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i3 + 160 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2621 nop RET2621: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2622: !_MEMBAR (FP) (Branch target of P2260) membar #StoreLoad ba P2623 nop TARGET2260: ba RET2260 nop P2623: !_BLD [12] (FP) (Branch target of P2281) wr %g0, 0xf0, %asi ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 fmovs %f19, %f14 fmovd %f40, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- ba P2624 nop TARGET2281: ba RET2281 nop P2624: !_MEMBAR (FP) P2625: !_REPLACEMENT [30] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l6 ld [%i2+128], %o5 st %o5, [%i2+128] add %i2, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] P2626: !_MEMBAR (FP) (Branch target of P2421) ba P2627 nop TARGET2421: ba RET2421 nop P2627: !_BSTC [3] (maybe <- 0x42000080) (FP) (CBR) (Branch target of P2513) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2627 nop RET2627: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 ba P2628 nop TARGET2513: ba RET2513 nop P2628: !_MEMBAR (FP) membar #StoreLoad P2629: !_REPLACEMENT [12] (Int) sethi %hi(0x2000), %l3 ld [%i2+4], %l7 st %l7, [%i2+4] add %i2, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] P2630: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2630 nop RET2630: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2631: !_BLD [11] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f0 membar #Sync ! 3 addresses covered fmovd %f8, %f2 P2632: !_MEMBAR (FP) (Branch target of P2482) ba P2633 nop TARGET2482: ba RET2482 nop P2633: !_BSTC [20] (maybe <- 0x42000085) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 256 ] %asi P2634: !_MEMBAR (FP) membar #StoreLoad P2635: !_PREFETCH [18] (Int) (Branch target of P2313) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 128], 1 ba P2636 nop TARGET2313: ba RET2313 nop P2636: !_LD [19] (Int) (Loop exit) lduw [%i2 + 0], %l3 ! move %l3(lower) -> %o1(lower) or %l3, %o1, %o1 !---- flushing int results buffer---- mov %o0, %l5 mov %o1, %l5 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovs %f2, %f30 !-- loop_exit_5_0: sub %l2, 1, %l2 cmp %l2, 0 bg loop_entry_5_0 nop P2637: !_MEMBAR (Int) membar #StoreLoad END_NODES5: ! Test instruction sequence for CPU 5 ends sethi %hi(0xdead0e0f), %l7 or %l7, %lo(0xdead0e0f), %l7 ! move %l7(lower) -> %o0(upper) sllx %l7, 32, %o0 sethi %hi(0xdead0e0f), %l7 or %l7, %lo(0xdead0e0f), %l7 stw %l7, [%i5] ld [%i5], %f0 !---- flushing int results buffer---- mov %o0, %l5 !---- flushing fp results buffer to %f30 ---- fmovs %f0, %f30 !-- restore retl nop !----------------- ! register usage: ! %i0 %i1 : base registers for first 2 regions ! %i2 %i3 : cache registers for 8 regions ! %i4 fixed pointer to per-cpu results area ! %l1 moving pointer to per-cpu FP results area ! %o7 moving pointer to per-cpu integer results area ! %i5 pointer to per-cpu private area ! %l0 holds lfsr, used as source of random bits ! %l2 loop count register ! %f16 running counter for unique fp store values ! %f17 holds increment value for fp counter ! %l4 running counter for unique integer store values (increment value is always 1) ! %l5 move-to register for load values (simulation only) ! %f30 move-to register for FP values (simulation only) ! %i4 holds the instructions count which is used for interrupt ordering ! %i4 holds the thread_id (OBP only) ! %l5 holds the moving pointer for interrupt bonus data (OBP only). Conflicts with RTL/simulation usage ! %l3 %l6 %l7 %o5 : 4 temporary registers ! %o0 %o1 %o2 %o3 %o4 : 5 integer results buffer registers ! %f0-f15 FP results buffer registers ! %f32-f47 FP block load/store registers func6: ! instruction sequence begins save %sp, -192, %sp ! Force %i0-%i3 to be 64-byte aligned add %i0, 63, %i0 andn %i0, 63, %i0 add %i1, 63, %i1 andn %i1, 63, %i1 add %i2, 63, %i2 andn %i2, 63, %i2 add %i3, 63, %i3 andn %i3, 63, %i3 add %i4, 63, %i4 andn %i4, 63, %i4 add %i5, 63, %i5 andn %i5, 63, %i5 ! Initialize pointer to FP load results area mov %i4, %l1 ! Initialize pointer to integer load results area sethi %hi(0x80000), %o7 or %o7, %lo(0x80000), %o7 add %o7, %l1, %o7 ! Reinitialize i4 to 0. i4 will be used to keep the count of analyzable node info mov 0x0, %i4 ! Initialize %f0-%f62 to 0xdeadbee0deadbee1 sethi %hi(0xdeadbee0), %l6 or %l6, %lo(0xdeadbee0), %l6 stw %l6, [%i5] sethi %hi(0xdeadbee1), %l6 or %l6, %lo(0xdeadbee1), %l6 stw %l6, [%i5+4] ldd [%i5], %f0 fmovd %f0, %f2 fmovd %f0, %f4 fmovd %f0, %f6 fmovd %f0, %f8 fmovd %f0, %f10 fmovd %f0, %f12 fmovd %f0, %f14 fmovd %f0, %f16 fmovd %f0, %f18 fmovd %f0, %f20 fmovd %f0, %f22 fmovd %f0, %f24 fmovd %f0, %f26 fmovd %f0, %f28 fmovd %f0, %f30 fmovd %f0, %f32 fmovd %f0, %f34 fmovd %f0, %f36 fmovd %f0, %f38 fmovd %f0, %f40 fmovd %f0, %f42 fmovd %f0, %f44 fmovd %f0, %f46 fmovd %f0, %f48 fmovd %f0, %f50 fmovd %f0, %f52 fmovd %f0, %f54 fmovd %f0, %f56 fmovd %f0, %f58 fmovd %f0, %f60 fmovd %f0, %f62 ! Signature for extract_loads script to start extracting load values for this stream sethi %hi(0x06deade1), %l6 or %l6, %lo(0x06deade1), %l6 stw %l6, [%i5] ld [%i5], %f16 ! Initialize running integer counter in register %l4 sethi %hi(0x3000001), %l4 or %l4, %lo(0x3000001), %l4 ! Initialize running FP counter in register %f16 sethi %hi(0x42800001), %l6 or %l6, %lo(0x42800001), %l6 stw %l6, [%i5] ld [%i5], %f16 ! Initialize FP counter increment value in register %f17 (constant) sethi %hi(0x37000000), %l6 or %l6, %lo(0x37000000), %l6 stw %l6, [%i5] ld [%i5], %f17 ! Initialize LFSR to 0x194e^4 sethi %hi(0x194e), %l0 or %l0, %lo(0x194e), %l0 mulx %l0, %l0, %l0 mulx %l0, %l0, %l0 BEGIN_NODES6: ! Test instruction sequence for ISTREAM 6 begins P2638: !_MEMBAR (FP) (Loop entry) (Secondary ctx) sethi %hi(0x1), %l2 or %l2, %lo(0x1), %l2 loop_entry_6_0: membar #StoreLoad P2639: !_BLD [10] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i1 + 64] %asi, %f0 membar #Sync ! 1 addresses covered P2640: !_MEMBAR (FP) (Secondary ctx) P2641: !_BLD [7] (FP) (CBR) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i0 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2641 nop RET2641: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2642: !_MEMBAR (FP) (Secondary ctx) P2643: !_PREFETCH [31] (Int) (Nucleus ctx) (Branch target of P2705) wr %g0, 0x4, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetcha [%i2 + 192] %asi, 1 ba P2644 nop TARGET2705: ba RET2705 nop P2644: !_MEMBAR (FP) membar #StoreLoad P2645: !_BLD [22] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f2 fmovd %f40, %f4 P2646: !_MEMBAR (FP) P2647: !_LD [22] (Int) (CBR) (Branch target of P2960) lduw [%i3 + 4], %o0 ! move %o0(lower) -> %o0(upper) sllx %o0, 32, %o0 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2647 nop RET2647: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P2648 nop TARGET2960: ba RET2960 nop P2648: !_REPLACEMENT [21] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l7 ld [%i2+0], %l3 st %l3, [%i2+0] add %i2, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] P2649: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P2650: !_BLD [2] (FP) (CBR) (Secondary ctx) (Branch target of P2975) wr %g0, 0xf1, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 fmovs %f19, %f6 fmovd %f34, %f18 fmovs %f18, %f7 fmovd %f36, %f8 fmovd %f40, %f18 fmovs %f18, %f9 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2650 nop RET2650: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P2651 nop TARGET2975: ba RET2975 nop P2651: !_MEMBAR (FP) (Secondary ctx) (Branch target of P3101) ba P2652 nop TARGET3101: ba RET3101 nop P2652: !_BSTC [13] (maybe <- 0x42800001) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P2653: !_MEMBAR (FP) (Branch target of P3018) membar #StoreLoad ba P2654 nop TARGET3018: ba RET3018 nop P2654: !_BLD [0] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f10 fmovd %f34, %f12 fmovd %f36, %f18 fmovs %f18, %f13 fmovd %f40, %f14 P2655: !_MEMBAR (FP) P2656: !_REPLACEMENT [4] (Int) sethi %hi(0x2000), %l6 ld [%i2+32], %o5 st %o5, [%i2+32] add %i2, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] P2657: !_MEMBAR (FP) membar #StoreLoad P2658: !_BLD [22] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovs %f19, %f0 fmovd %f40, %f18 fmovs %f18, %f1 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2658 nop RET2658: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2659: !_MEMBAR (FP) P2660: !_BLD [27] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f2 fmovd %f40, %f18 fmovs %f18, %f3 P2661: !_MEMBAR (FP) P2662: !_BST [8] (maybe <- 0x42800004) (FP) (Secondary ctx) wr %g0, 0xf1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i1 + 0 ] %asi P2663: !_MEMBAR (FP) (CBR) (Secondary ctx) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2663 nop RET2663: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2664: !_PREFETCH [33] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetcha [%i3 + 0] %asi, 1 P2665: !_LD [18] (Int) (Branch target of P3278) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduw [%i2 + 128], %l7 ! move %l7(lower) -> %o0(lower) or %l7, %o0, %o0 ba P2666 nop TARGET3278: ba RET3278 nop P2666: !_LD [6] (Int) lduw [%i0 + 96], %o1 ! move %o1(lower) -> %o1(upper) sllx %o1, 32, %o1 P2667: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2667 nop RET2667: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2668: !_BST [14] (maybe <- 0x42800006) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 64 ] %asi P2669: !_MEMBAR (FP) membar #StoreLoad P2670: !_LD [29] (FP) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ld [%i2 + 64], %f4 ! 1 addresses covered P2671: !_MEMBAR (FP) membar #StoreLoad P2672: !_BLD [25] (FP) (CBR) (Branch target of P3359) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 fmovd %f40, %f6 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2672 nop RET2672: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P2673 nop TARGET3359: ba RET3359 nop P2673: !_MEMBAR (FP) P2674: !_REPLACEMENT [12] (Int) (Nucleus ctx) (Branch target of P3151) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l7 ld [%i2+4], %l3 st %l3, [%i2+4] add %i2, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] ba P2675 nop TARGET3151: ba RET3151 nop P2675: !_IDC_FLIP [5] (Int) IDC_FLIP(2675, 31029, 6, 0x43000040, 0x40, %i0, 0x40, %l6, %l7, %o5, %l3) P2676: !_LD [18] (Int) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lduw [%i3 + 128], %l7 ! move %l7(lower) -> %o1(lower) or %l7, %o1, %o1 P2677: !_REPLACEMENT [24] (Int) (CBR) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(0x2000), %o5 ld [%i2+64], %l6 st %l6, [%i2+64] add %i2, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2677 nop RET2677: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2678: !_REPLACEMENT [30] (Int) sethi %hi(0x2000), %o5 ld [%i2+128], %l6 st %l6, [%i2+128] add %i2, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] P2679: !_MEMBAR (FP) (Branch target of P3576) ba P2680 nop TARGET3576: ba RET3576 nop P2680: !_BSTC [32] (maybe <- 0x42800007) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 256 ] %asi P2681: !_MEMBAR (FP) membar #StoreLoad P2682: !_BLD [29] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 P2683: !_MEMBAR (FP) (Branch target of P3002) ba P2684 nop TARGET3002: ba RET3002 nop P2684: !_BST [32] (maybe <- 0x42800008) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 256 ] %asi P2685: !_MEMBAR (FP) (Branch target of P3477) membar #StoreLoad ba P2686 nop TARGET3477: ba RET3477 nop P2686: !_BLD [4] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f8 fmovd %f34, %f10 fmovd %f36, %f18 fmovs %f18, %f11 fmovd %f40, %f12 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2686 nop RET2686: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2687: !_MEMBAR (FP) (Branch target of P3269) ba P2688 nop TARGET3269: ba RET3269 nop P2688: !_REPLACEMENT [7] (Int) (Branch target of P2846) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l6 ld [%i3+128], %o5 st %o5, [%i3+128] add %i3, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] ba P2689 nop TARGET2846: ba RET2846 nop P2689: !_MEMBAR (FP) membar #StoreLoad P2690: !_BLD [29] (FP) (CBR) (Branch target of P3337) wr %g0, 0xf0, %asi ldda [%i2 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2690 nop RET2690: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P2691 nop TARGET3337: ba RET3337 nop P2691: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2691 nop RET2691: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2692: !_LD [12] (FP) (CBR) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ld [%i2 + 4], %f14 ! 1 addresses covered ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2692 nop RET2692: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2693: !_MEMBAR (FP) P2694: !_BST [5] (maybe <- 0x42800009) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 64 ] %asi P2695: !_MEMBAR (FP) membar #StoreLoad P2696: !_PREFETCH [14] (Int) (CBR) prefetch [%i2 + 64], 1 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2696 nop RET2696: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2697: !_PREFETCH [1] (Int) (CBR) (Nucleus ctx) wr %g0, 0x4, %asi prefetcha [%i0 + 4] %asi, 1 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2697 nop RET2697: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2698: !_LD [13] (Int) (LE) wr %g0, 0x88, %asi lduwa [%i2 + 32] %asi, %o2 ! move %o2(lower) -> %o2(upper) sllx %o2, 32, %o2 P2699: !_MEMBAR (FP) P2700: !_BST [21] (maybe <- 0x4280000b) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P2701: !_MEMBAR (FP) (CBR) (Branch target of P3523) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2701 nop RET2701: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P2702 nop TARGET3523: ba RET3523 nop P2702: !_BLD [9] (FP) wr %g0, 0xf0, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f40, %f0 P2703: !_MEMBAR (FP) P2704: !_LD [13] (FP) (CBR) ld [%i2 + 32], %f1 ! 1 addresses covered ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2704 nop RET2704: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2705: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2705 nop RET2705: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2706: !_BST [8] (maybe <- 0x4280000e) (FP) (CBR) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i1 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2706 nop RET2706: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2707: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2707 nop RET2707: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2708: !_ST [13] (maybe <- 0x42800010) (FP) (CBR) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 32 ] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2708 nop RET2708: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2709: !_REPLACEMENT [32] (Int) (CBR) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l6 ld [%i2+256], %o5 st %o5, [%i2+256] add %i2, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2709 nop RET2709: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2710: !_REPLACEMENT [17] (Int) sethi %hi(0x2000), %l6 ld [%i2+96], %o5 st %o5, [%i2+96] add %i2, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] P2711: !_REPLACEMENT [19] (Int) sethi %hi(0x2000), %l3 ld [%i2+0], %l7 st %l7, [%i2+0] add %i2, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] P2712: !_MEMBAR (FP) P2713: !_BSTC [8] (maybe <- 0x42800011) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i1 + 0 ] %asi P2714: !_MEMBAR (FP) membar #StoreLoad P2715: !_MEMBAR (Int) membar #StoreLoad P2716: !_LD [32] (Int) (Loop exit) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lduw [%i3 + 256], %o5 ! move %o5(lower) -> %o2(lower) or %o5, %o2, %o2 !---- flushing int results buffer---- mov %o0, %l5 mov %o1, %l5 mov %o2, %l5 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 !-- loop_exit_6_0: sub %l2, 1, %l2 cmp %l2, 0 bg loop_entry_6_0 nop P2717: !_PREFETCH [31] (Int) (Loop entry) sethi %hi(0x1), %l2 or %l2, %lo(0x1), %l2 loop_entry_6_1: sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 192], 1 P2718: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2718 nop RET2718: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2719: !_BLD [5] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f0 membar #Sync ! 2 addresses covered fmovs %f8, %f1 P2720: !_MEMBAR (FP) (Branch target of P3433) ba P2721 nop TARGET3433: ba RET3433 nop P2721: !_PREFETCH [24] (Int) (Branch target of P2706) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 64], 1 ba P2722 nop TARGET2706: ba RET2706 nop P2722: !_LD [24] (FP) (Nucleus ctx) wr %g0, 0x4, %asi lda [%i3 + 64] %asi, %f2 ! 1 addresses covered P2723: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2723 nop RET2723: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2724: !_BLD [18] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2724 nop RET2724: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2725: !_MEMBAR (FP) P2726: !_REPLACEMENT [10] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+64], %l7 st %l7, [%i3+64] add %i3, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] P2727: !_ST [12] (maybe <- 0x3000001) (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 stwa %l4, [%i2 + 4] %asi add %l4, 1, %l4 P2728: !_MEMBAR (FP) P2729: !_BSTC [25] (maybe <- 0x42800013) (FP) (CBR) wr %g0, 0xe0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2729 nop RET2729: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2730: !_MEMBAR (FP) (Branch target of P3397) membar #StoreLoad ba P2731 nop TARGET3397: ba RET3397 nop P2731: !_BLD [19] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f4 P2732: !_MEMBAR (FP) P2733: !_REPLACEMENT [31] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+192], %l3 st %l3, [%i3+192] add %i3, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] P2734: !_PREFETCH [22] (Int) (Branch target of P2827) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 4], 1 ba P2735 nop TARGET2827: ba RET2827 nop P2735: !_LD [8] (Int) lduw [%i1 + 0], %o0 ! move %o0(lower) -> %o0(upper) sllx %o0, 32, %o0 P2736: !_MEMBAR (FP) (Branch target of P2998) ba P2737 nop TARGET2998: ba RET2998 nop P2737: !_BST [17] (maybe <- 0x42800015) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f40 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 64 ] %asi P2738: !_MEMBAR (FP) membar #StoreLoad P2739: !_ST [4] (maybe <- 0x3000002) (Int) stw %l4, [%i0 + 32 ] add %l4, 1, %l4 P2740: !_PREFETCH [31] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetcha [%i2 + 192] %asi, 1 P2741: !_PREFETCH [3] (Int) prefetch [%i0 + 16], 1 P2742: !_ST [14] (maybe <- 0x42800016) (FP) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 64 ] P2743: !_MEMBAR (FP) membar #StoreLoad P2744: !_BLD [12] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 fmovs %f19, %f6 fmovd %f40, %f18 fmovs %f18, %f7 P2745: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2745 nop RET2745: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2746: !_BSTC [7] (maybe <- 0x42800017) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i0 + 128 ] %asi P2747: !_MEMBAR (FP) membar #StoreLoad P2748: !_ST [33] (maybe <- 0x42800018) (FP) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i2 + 0 ] %asi P2749: !_MEMBAR (FP) membar #StoreLoad P2750: !_BLD [4] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f8 fmovd %f34, %f10 fmovd %f36, %f18 fmovs %f18, %f11 fmovd %f40, %f12 P2751: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2751 nop RET2751: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2752: !_PREFETCH [26] (Int) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 128], 1 P2753: !_ST [10] (maybe <- 0x42800019) (FP) (Nucleus ctx) wr %g0, 0x4, %asi ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i1 + 64 ] %asi P2754: !_PREFETCH [6] (Int) prefetch [%i0 + 96], 1 P2755: !_MEMBAR (FP) membar #StoreLoad P2756: !_BLD [20] (FP) (Branch target of P3154) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 ba P2757 nop TARGET3154: ba RET3154 nop P2757: !_MEMBAR (FP) P2758: !_BLD [28] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f14 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2758 nop RET2758: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2759: !_MEMBAR (FP) P2760: !_BLD [9] (FP) wr %g0, 0xf0, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f40, %f0 P2761: !_MEMBAR (FP) (Branch target of P3293) ba P2762 nop TARGET3293: ba RET3293 nop P2762: !_REPLACEMENT [26] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+128], %l7 st %l7, [%i2+128] add %i2, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] P2763: !_MEMBAR (FP) P2764: !_BSTC [20] (maybe <- 0x4280001a) (FP) (Branch target of P3631) wr %g0, 0xe0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 256 ] %asi ba P2765 nop TARGET3631: ba RET3631 nop P2765: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2765 nop RET2765: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2766: !_BST [6] (maybe <- 0x4280001b) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 64 ] %asi P2767: !_MEMBAR (FP) membar #StoreLoad P2768: !_REPLACEMENT [1] (Int) sethi %hi(0x2000), %l7 ld [%i2+4], %l3 st %l3, [%i2+4] add %i2, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] P2769: !_MEMBAR (FP) membar #StoreLoad P2770: !_BLD [22] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 fmovs %f19, %f2 fmovd %f40, %f18 fmovs %f18, %f3 P2771: !_MEMBAR (FP) (Branch target of P3105) ba P2772 nop TARGET3105: ba RET3105 nop P2772: !_ST [23] (maybe <- 0x4280001d) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 32 ] P2773: !_LD [25] (Int) lduw [%i2 + 96], %l6 ! move %l6(lower) -> %o0(lower) or %l6, %o0, %o0 P2774: !_MEMBAR (FP) membar #StoreLoad P2775: !_BLD [2] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f4 fmovd %f34, %f6 fmovd %f36, %f18 fmovs %f18, %f7 fmovd %f40, %f8 P2776: !_MEMBAR (FP) (CBR) (Branch target of P2822) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2776 nop RET2776: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P2777 nop TARGET2822: ba RET2822 nop P2777: !_BSTC [29] (maybe <- 0x4280001e) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 64 ] %asi P2778: !_MEMBAR (FP) membar #StoreLoad P2779: !_PREFETCH [7] (Int) (Branch target of P3547) prefetch [%i0 + 128], 1 ba P2780 nop TARGET3547: ba RET3547 nop P2780: !_MEMBAR (FP) (Secondary ctx) P2781: !_BSTC [2] (maybe <- 0x4280001f) (FP) (Secondary ctx) wr %g0, 0xe1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P2782: !_MEMBAR (FP) (Secondary ctx) (Branch target of P3458) membar #StoreLoad ba P2783 nop TARGET3458: ba RET3458 nop P2783: !_BLD [17] (FP) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f40, %f18 fmovs %f18, %f9 P2784: !_MEMBAR (FP) (CBR) (Secondary ctx) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2784 nop RET2784: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2785: !_BST [24] (maybe <- 0x42800024) (FP) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 64 ] %asi P2786: !_MEMBAR (FP) (Secondary ctx) (Branch target of P2878) ba P2787 nop TARGET2878: ba RET2878 nop P2787: !_BSTC [27] (maybe <- 0x42800026) (FP) (Branch target of P3405) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 128 ] %asi ba P2788 nop TARGET3405: ba RET3405 nop P2788: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2788 nop RET2788: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2789: !_BST [10] (maybe <- 0x42800028) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i1 + 64 ] %asi P2790: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2790 nop RET2790: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2791: !_BLD [12] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f10 fmovd %f40, %f12 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2791 nop RET2791: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2792: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2792 nop RET2792: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2793: !_BSTC [4] (maybe <- 0x42800029) (FP) (Branch target of P3180) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi ba P2794 nop TARGET3180: ba RET3180 nop P2794: !_MEMBAR (FP) membar #StoreLoad P2795: !_BLD [30] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 P2796: !_MEMBAR (FP) (Branch target of P3095) ba P2797 nop TARGET3095: ba RET3095 nop P2797: !_BSTC [22] (maybe <- 0x4280002e) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P2798: !_MEMBAR (FP) membar #StoreLoad P2799: !_BLD [0] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f14 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f34, %f0 fmovd %f36, %f18 fmovs %f18, %f1 fmovd %f40, %f2 P2800: !_MEMBAR (FP) (Branch target of P2877) ba P2801 nop TARGET2877: ba RET2877 nop P2801: !_BLD [29] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 P2802: !_MEMBAR (FP) (Loop exit) !---- flushing int results buffer---- mov %o0, %l5 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 !-- loop_exit_6_1: sub %l2, 1, %l2 cmp %l2, 0 bg loop_entry_6_1 nop P2803: !_REPLACEMENT [31] (Int) (Loop entry) (Branch target of P2913) sethi %hi(0x1), %l2 or %l2, %lo(0x1), %l2 loop_entry_6_2: sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+192], %l3 st %l3, [%i3+192] add %i3, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] ba P2804 nop TARGET2913: ba RET2913 nop P2804: !_MEMBAR (FP) membar #StoreLoad P2805: !_BLD [6] (FP) (CBR) (Branch target of P3634) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f0 membar #Sync ! 2 addresses covered fmovs %f8, %f1 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2805 nop RET2805: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P2806 nop TARGET3634: ba RET3634 nop P2806: !_MEMBAR (FP) P2807: !_BSTC [23] (maybe <- 0x42800031) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P2808: !_MEMBAR (FP) membar #StoreLoad P2809: !_MEMBAR (Int) membar #StoreLoad P2810: !_REPLACEMENT [32] (Int) (Branch target of P3153) sethi %hi(0x2000), %l6 ld [%i3+256], %o5 st %o5, [%i3+256] add %i3, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] add %l7, %l6, %l7 ld [%l7+256], %o5 st %o5, [%l7+256] ba P2811 nop TARGET3153: ba RET3153 nop P2811: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P2812: !_BLD [4] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f2 fmovd %f34, %f4 fmovd %f36, %f18 fmovs %f18, %f5 fmovd %f40, %f6 P2813: !_MEMBAR (FP) (CBR) (Secondary ctx) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2813 nop RET2813: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2814: !_REPLACEMENT [31] (Int) sethi %hi(0x2000), %l6 ld [%i3+192], %o5 st %o5, [%i3+192] add %i3, %l6, %l7 ld [%l7+192], %o5 st %o5, [%l7+192] add %l7, %l6, %l7 ld [%l7+192], %o5 st %o5, [%l7+192] add %l7, %l6, %l7 ld [%l7+192], %o5 st %o5, [%l7+192] add %l7, %l6, %l7 ld [%l7+192], %o5 st %o5, [%l7+192] add %l7, %l6, %l7 ld [%l7+192], %o5 st %o5, [%l7+192] add %l7, %l6, %l7 ld [%l7+192], %o5 st %o5, [%l7+192] add %l7, %l6, %l7 ld [%l7+192], %o5 st %o5, [%l7+192] P2815: !_MEMBAR (FP) membar #StoreLoad P2816: !_BLD [20] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 P2817: !_MEMBAR (FP) P2818: !_BLD [30] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f8 P2819: !_MEMBAR (FP) P2820: !_REPLACEMENT [6] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+96], %l7 st %l7, [%i3+96] add %i3, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] P2821: !_REPLACEMENT [27] (Int) sethi %hi(0x2000), %o5 ld [%i3+160], %l6 st %l6, [%i3+160] add %i3, %o5, %l3 ld [%l3+160], %l6 st %l6, [%l3+160] add %l3, %o5, %l3 ld [%l3+160], %l6 st %l6, [%l3+160] add %l3, %o5, %l3 ld [%l3+160], %l6 st %l6, [%l3+160] add %l3, %o5, %l3 ld [%l3+160], %l6 st %l6, [%l3+160] add %l3, %o5, %l3 ld [%l3+160], %l6 st %l6, [%l3+160] add %l3, %o5, %l3 ld [%l3+160], %l6 st %l6, [%l3+160] add %l3, %o5, %l3 ld [%l3+160], %l6 st %l6, [%l3+160] P2822: !_ST [3] (maybe <- 0x3000003) (Int) (CBR) (Nucleus ctx) wr %g0, 0x4, %asi stwa %l4, [%i0 + 16] %asi add %l4, 1, %l4 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2822 nop RET2822: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2823: !_PREFETCH [5] (Int) (Branch target of P3423) prefetch [%i0 + 64], 1 ba P2824 nop TARGET3423: ba RET3423 nop P2824: !_MEMBAR (FP) (Branch target of P3283) ba P2825 nop TARGET3283: ba RET3283 nop P2825: !_BST [10] (maybe <- 0x42800034) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i1 + 64 ] %asi P2826: !_MEMBAR (FP) membar #StoreLoad P2827: !_BLD [28] (FP) (CBR) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f9 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2827 nop RET2827: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2828: !_MEMBAR (FP) (Secondary ctx) P2829: !_BSTC [11] (maybe <- 0x42800035) (FP) (Secondary ctx) wr %g0, 0xe1, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P2830: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P2831: !_BLD [6] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f10 fmovd %f40, %f18 fmovs %f18, %f11 P2832: !_MEMBAR (FP) P2833: !_BLD [26] (FP) (Branch target of P2925) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f12 fmovd %f40, %f18 fmovs %f18, %f13 ba P2834 nop TARGET2925: ba RET2925 nop P2834: !_MEMBAR (FP) P2835: !_BST [3] (maybe <- 0x42800038) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P2836: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2836 nop RET2836: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2837: !_BSTC [19] (maybe <- 0x4280003d) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 0 ] %asi P2838: !_MEMBAR (FP) membar #StoreLoad P2839: !_MEMBAR (Int) P2840: !_BST [7] (maybe <- 0x4280003e) (FP) (Branch target of P2890) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i0 + 128 ] %asi ba P2841 nop TARGET2890: ba RET2890 nop P2841: !_MEMBAR (FP) (Branch target of P3422) ba P2842 nop TARGET3422: ba RET3422 nop P2842: !_BSTC [5] (maybe <- 0x4280003f) (FP) (Branch target of P2869) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 64 ] %asi ba P2843 nop TARGET2869: ba RET2869 nop P2843: !_MEMBAR (FP) (Branch target of P2939) membar #StoreLoad ba P2844 nop TARGET2939: ba RET2939 nop P2844: !_PREFETCH [17] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetcha [%i3 + 96] %asi, 1 P2845: !_MEMBAR (FP) (Secondary ctx) P2846: !_BST [14] (maybe <- 0x42800041) (FP) (CBR) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2846 nop RET2846: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2847: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P2848: !_BLD [7] (FP) (Branch target of P3303) wr %g0, 0xf0, %asi ldda [%i0 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f14 ba P2849 nop TARGET3303: ba RET3303 nop P2849: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2849 nop RET2849: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2850: !_ST [19] (maybe <- 0x3000004) (Int) (CBR) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stw %l4, [%i3 + 0 ] add %l4, 1, %l4 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2850 nop RET2850: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2851: !_MEMBAR (FP) membar #StoreLoad P2852: !_BLD [17] (FP) (CBR) (Branch target of P3461) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f40, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2852 nop RET2852: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 ba P2853 nop TARGET3461: ba RET3461 nop P2853: !_MEMBAR (FP) (Branch target of P3097) ba P2854 nop TARGET3097: ba RET3097 nop P2854: !_BLD [21] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f0 membar #Sync ! 3 addresses covered fmovd %f8, %f2 P2855: !_MEMBAR (FP) P2856: !_ST [18] (maybe <- 0x3000005) (Int) stw %l4, [%i2 + 128 ] add %l4, 1, %l4 P2857: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2857 nop RET2857: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2858: !_BSTC [18] (maybe <- 0x42800042) (FP) (CBR) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 128 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2858 nop RET2858: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2859: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2859 nop RET2859: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2860: !_BST [31] (maybe <- 0x42800043) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 192 ] %asi P2861: !_MEMBAR (FP) P2862: !_BST [22] (maybe <- 0x42800044) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P2863: !_MEMBAR (FP) P2864: !_BSTC [22] (maybe <- 0x42800047) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P2865: !_MEMBAR (FP) (Branch target of P3382) ba P2866 nop TARGET3382: ba RET3382 nop P2866: !_BSTC [14] (maybe <- 0x4280004a) (FP) (Branch target of P2876) wr %g0, 0xe0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 64 ] %asi ba P2867 nop TARGET2876: ba RET2876 nop P2867: !_MEMBAR (FP) P2868: !_BST [6] (maybe <- 0x4280004b) (FP) (Branch target of P3192) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 64 ] %asi ba P2869 nop TARGET3192: ba RET3192 nop P2869: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2869 nop RET2869: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2870: !_LD [22] (Int) (CBR) (Secondary ctx) (Branch target of P3309) wr %g0, 0x81, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduwa [%i2 + 4] %asi, %o0 ! move %o0(lower) -> %o0(upper) sllx %o0, 32, %o0 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2870 nop RET2870: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 ba P2871 nop TARGET3309: ba RET3309 nop P2871: !_LD [13] (FP) (Nucleus ctx) wr %g0, 0x4, %asi lda [%i3 + 32] %asi, %f3 ! 1 addresses covered P2872: !_MEMBAR (FP) membar #StoreLoad P2873: !_BLD [25] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i2 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f4 fmovd %f40, %f18 fmovs %f18, %f5 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2873 nop RET2873: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2874: !_MEMBAR (FP) P2875: !_BSTC [10] (maybe <- 0x4280004d) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i1 + 64 ] %asi P2876: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2876 nop RET2876: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2877: !_REPLACEMENT [5] (Int) (CBR) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l6 ld [%i3+64], %o5 st %o5, [%i3+64] add %i3, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2877 nop RET2877: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2878: !_ST [19] (maybe <- 0x4280004e) (FP) (CBR) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 0 ] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2878 nop RET2878: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2879: !_ST [3] (maybe <- 0x4280004f) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i0 + 16 ] P2880: !_MEMBAR (FP) P2881: !_BST [26] (maybe <- 0x42800050) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 128 ] %asi P2882: !_MEMBAR (FP) membar #StoreLoad P2883: !_BLD [18] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f6 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2883 nop RET2883: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2884: !_MEMBAR (FP) P2885: !_PREFETCH [28] (Int) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 0], 1 P2886: !_LD [33] (Int) (Branch target of P3400) sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduw [%i2 + 0], %l6 ! move %l6(lower) -> %o0(lower) or %l6, %o0, %o0 ba P2887 nop TARGET3400: ba RET3400 nop P2887: !_ST [18] (maybe <- 0x42800052) (FP) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i3 + 128 ] %asi P2888: !_MEMBAR (FP) (Branch target of P3453) ba P2889 nop TARGET3453: ba RET3453 nop P2889: !_BSTC [30] (maybe <- 0x42800053) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 128 ] %asi P2890: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2890 nop RET2890: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2891: !_BLD [25] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 fmovd %f40, %f8 P2892: !_MEMBAR (FP) P2893: !_LD [20] (FP) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lda [%i2 + 256] %asi, %f9 ! 1 addresses covered P2894: !_REPLACEMENT [18] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l6 ld [%i3+128], %o5 st %o5, [%i3+128] add %i3, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] P2895: !_IDC_FLIP [23] (Int) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 IDC_FLIP(2895, 11677, 6, 0x45800020, 0x20, %i2, 0x20, %l6, %l7, %o5, %l3) P2896: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P2897: !_BLD [20] (FP) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f10 P2898: !_MEMBAR (FP) (Secondary ctx) (Branch target of P2900) ba P2899 nop TARGET2900: ba RET2900 nop P2899: !_REPLACEMENT [23] (Int) (Branch target of P3232) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l6 ld [%i2+32], %o5 st %o5, [%i2+32] add %i2, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] ba P2900 nop TARGET3232: ba RET3232 nop P2900: !_LD [32] (Int) (CBR) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lduw [%i3 + 256], %o1 ! move %o1(lower) -> %o1(upper) sllx %o1, 32, %o1 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2900 nop RET2900: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2901: !_MEMBAR (FP) P2902: !_BST [1] (maybe <- 0x42800054) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P2903: !_MEMBAR (FP) P2904: !_BST [3] (maybe <- 0x42800059) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P2905: !_MEMBAR (FP) membar #StoreLoad P2906: !_BLD [3] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 fmovs %f19, %f12 fmovd %f34, %f18 fmovs %f18, %f13 fmovd %f36, %f14 fmovd %f40, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2906 nop RET2906: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2907: !_MEMBAR (FP) P2908: !_BST [9] (maybe <- 0x4280005e) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i1 + 0 ] %asi P2909: !_MEMBAR (FP) membar #StoreLoad P2910: !_PREFETCH [10] (Int) prefetch [%i1 + 64], 1 P2911: !_REPLACEMENT [23] (Int) (Branch target of P2918) sethi %hi(0x2000), %l6 ld [%i2+32], %o5 st %o5, [%i2+32] add %i2, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] ba P2912 nop TARGET2918: ba RET2918 nop P2912: !_ST [27] (maybe <- 0x3000006) (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 stwa %l4, [%i2 + 160] %asi add %l4, 1, %l4 P2913: !_REPLACEMENT [2] (Int) (CBR) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %o5 ld [%i3+8], %l6 st %l6, [%i3+8] add %i3, %o5, %l3 ld [%l3+8], %l6 st %l6, [%l3+8] add %l3, %o5, %l3 ld [%l3+8], %l6 st %l6, [%l3+8] add %l3, %o5, %l3 ld [%l3+8], %l6 st %l6, [%l3+8] add %l3, %o5, %l3 ld [%l3+8], %l6 st %l6, [%l3+8] add %l3, %o5, %l3 ld [%l3+8], %l6 st %l6, [%l3+8] add %l3, %o5, %l3 ld [%l3+8], %l6 st %l6, [%l3+8] add %l3, %o5, %l3 ld [%l3+8], %l6 st %l6, [%l3+8] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2913 nop RET2913: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2914: !_ST [9] (maybe <- 0x42800060) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i1 + 32 ] P2915: !_ST [30] (maybe <- 0x3000007) (Int) (Secondary ctx) (Branch target of P3223) wr %g0, 0x81, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 stwa %l4, [%i2 + 128] %asi add %l4, 1, %l4 ba P2916 nop TARGET3223: ba RET3223 nop P2916: !_MEMBAR (FP) membar #StoreLoad P2917: !_BLD [27] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f0 membar #Sync ! 2 addresses covered fmovs %f8, %f1 P2918: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2918 nop RET2918: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2919: !_PREFETCH [24] (Int) (Nucleus ctx) wr %g0, 0x4, %asi prefetcha [%i3 + 64] %asi, 1 P2920: !_ST [20] (maybe <- 0x42800061) (FP) (Branch target of P2883) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 256 ] ba P2921 nop TARGET2883: ba RET2883 nop P2921: !_MEMBAR (FP) P2922: !_BSTC [4] (maybe <- 0x42800062) (FP) (Branch target of P3603) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi ba P2923 nop TARGET3603: ba RET3603 nop P2923: !_MEMBAR (FP) membar #StoreLoad P2924: !_PREFETCH [32] (Int) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 256], 1 P2925: !_ST [0] (maybe <- 0x42800067) (FP) (CBR) (Secondary ctx) (Branch target of P2852) wr %g0, 0x81, %asi ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i0 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2925 nop RET2925: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 ba P2926 nop TARGET2852: ba RET2852 nop P2926: !_REPLACEMENT [0] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+0], %l7 st %l7, [%i2+0] add %i2, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] P2927: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2927 nop RET2927: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2928: !_BLD [4] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f2 fmovd %f34, %f4 fmovd %f36, %f18 fmovs %f18, %f5 fmovd %f40, %f6 P2929: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2929 nop RET2929: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2930: !_LD [22] (FP) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lda [%i3 + 4] %asi, %f7 ! 1 addresses covered P2931: !_REPLACEMENT [9] (Int) (Secondary ctx) (Branch target of P2697) wr %g0, 0x81, %asi sethi %hi(0x2000), %l6 ld [%i2+32], %o5 st %o5, [%i2+32] add %i2, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] add %l7, %l6, %l7 ld [%l7+32], %o5 st %o5, [%l7+32] ba P2932 nop TARGET2697: ba RET2697 nop P2932: !_LD [26] (Int) (Branch target of P3533) lduw [%i3 + 128], %l6 ! move %l6(lower) -> %o1(lower) or %l6, %o1, %o1 ba P2933 nop TARGET3533: ba RET3533 nop P2933: !_PREFETCH [33] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetcha [%i2 + 0] %asi, 1 P2934: !_MEMBAR (FP) P2935: !_BST [11] (maybe <- 0x42800068) (FP) (Branch target of P2849) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi ba P2936 nop TARGET2849: ba RET2849 nop P2936: !_MEMBAR (FP) (Branch target of P3282) membar #StoreLoad ba P2937 nop TARGET3282: ba RET3282 nop P2937: !_LD [9] (Int) (Branch target of P3356) lduw [%i1 + 32], %o2 ! move %o2(lower) -> %o2(upper) sllx %o2, 32, %o2 ba P2938 nop TARGET3356: ba RET3356 nop P2938: !_ST [29] (maybe <- 0x4280006b) (FP) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 64 ] P2939: !_REPLACEMENT [1] (Int) (CBR) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+4], %l3 st %l3, [%i3+4] add %i3, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2939 nop RET2939: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P2940: !_REPLACEMENT [25] (Int) sethi %hi(0x2000), %l7 ld [%i3+96], %l3 st %l3, [%i3+96] add %i3, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] P2941: !_PREFETCH [12] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetcha [%i2 + 4] %asi, 1 P2942: !_MEMBAR (FP) membar #StoreLoad P2943: !_BLD [2] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f8 fmovd %f34, %f10 fmovd %f36, %f18 fmovs %f18, %f11 fmovd %f40, %f12 P2944: !_MEMBAR (FP) P2945: !_BLD [0] (FP) (Branch target of P3077) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 fmovs %f19, %f14 fmovd %f34, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f36, %f0 fmovd %f40, %f18 fmovs %f18, %f1 ba P2946 nop TARGET3077: ba RET3077 nop P2946: !_MEMBAR (FP) P2947: !_BLD [28] (FP) (Secondary ctx) (Branch target of P2850) wr %g0, 0xf1, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f2 ba P2948 nop TARGET2850: ba RET2850 nop P2948: !_MEMBAR (FP) (Secondary ctx) P2949: !_LD [21] (FP) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ld [%i2 + 0], %f3 ! 1 addresses covered P2950: !_ST [10] (maybe <- 0x4280006c) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i1 + 64 ] P2951: !_MEMBAR (FP) membar #StoreLoad P2952: !_BLD [0] (FP) (Branch target of P2790) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f4 fmovd %f34, %f6 fmovd %f36, %f18 fmovs %f18, %f7 fmovd %f40, %f8 ba P2953 nop TARGET2790: ba RET2790 nop P2953: !_MEMBAR (FP) P2954: !_BST [14] (maybe <- 0x4280006d) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 64 ] %asi P2955: !_MEMBAR (FP) membar #StoreLoad P2956: !_BLD [21] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f9 fmovs %f19, %f10 fmovd %f40, %f18 fmovs %f18, %f11 P2957: !_MEMBAR (FP) P2958: !_BLD [7] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i0 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f12 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET2958 nop RET2958: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2959: !_MEMBAR (FP) P2960: !_BST [20] (maybe <- 0x4280006e) (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 256 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2960 nop RET2960: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2961: !_MEMBAR (FP) membar #StoreLoad P2962: !_LD [15] (FP) (Secondary ctx) wr %g0, 0x81, %asi lda [%i3 + 128] %asi, %f13 ! 1 addresses covered P2963: !_MEMBAR (FP) membar #StoreLoad P2964: !_BLD [33] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f14 P2965: !_MEMBAR (FP) P2966: !_BLD [28] (FP) (CBR) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2966 nop RET2966: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2967: !_MEMBAR (FP) (Secondary ctx) P2968: !_PREFETCH [8] (Int) prefetch [%i1 + 0], 1 P2969: !_MEMBAR (FP) (Secondary ctx) (Branch target of P2723) ba P2970 nop TARGET2723: ba RET2723 nop P2970: !_BST [18] (maybe <- 0x4280006f) (FP) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 128 ] %asi P2971: !_MEMBAR (FP) (Secondary ctx) P2972: !_BSTC [14] (maybe <- 0x42800070) (FP) (CBR) wr %g0, 0xe0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2972 nop RET2972: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2973: !_MEMBAR (FP) membar #StoreLoad P2974: !_BLD [4] (FP) (Branch target of P3326) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f0 membar #Sync ! 5 addresses covered fmovs %f4, %f3 fmovd %f8, %f4 ba P2975 nop TARGET3326: ba RET3326 nop P2975: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2975 nop RET2975: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P2976: !_REPLACEMENT [30] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l6 ld [%i3+128], %o5 st %o5, [%i3+128] add %i3, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] P2977: !_REPLACEMENT [3] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(0x2000), %l3 ld [%i3+16], %l7 st %l7, [%i3+16] add %i3, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] P2978: !_ST [24] (maybe <- 0x42800071) (FP) (CBR) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 64 ] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2978 nop RET2978: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P2979: !_ST [26] (maybe <- 0x3000008) (Int) (Nucleus ctx) wr %g0, 0x4, %asi stwa %l4, [%i2 + 128] %asi add %l4, 1, %l4 P2980: !_MEMBAR (FP) P2981: !_BST [14] (maybe <- 0x42800072) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 64 ] %asi P2982: !_MEMBAR (FP) (Branch target of P3195) membar #StoreLoad ba P2983 nop TARGET3195: ba RET3195 nop P2983: !_PREFETCH [16] (Int) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 16], 1 P2984: !_REPLACEMENT [19] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l6 ld [%i3+0], %o5 st %o5, [%i3+0] add %i3, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] P2985: !_MEMBAR (FP) (Branch target of P2859) ba P2986 nop TARGET2859: ba RET2859 nop P2986: !_BST [10] (maybe <- 0x42800073) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i1 + 64 ] %asi P2987: !_MEMBAR (FP) membar #StoreLoad P2988: !_ST [5] (maybe <- 0x42800074) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i0 + 64 ] P2989: !_REPLACEMENT [14] (Int) sethi %hi(0x2000), %l7 ld [%i3+64], %l3 st %l3, [%i3+64] add %i3, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] P2990: !_MEMBAR (FP) P2991: !_BST [12] (maybe <- 0x42800075) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P2992: !_MEMBAR (FP) membar #StoreLoad P2993: !_PREFETCH [24] (Int) (Branch target of P3626) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 64], 1 ba P2994 nop TARGET3626: ba RET3626 nop P2994: !_MEMBAR (FP) (Branch target of P3380) membar #StoreLoad ba P2995 nop TARGET3380: ba RET3380 nop P2995: !_BLD [18] (FP) (Branch target of P2701) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 ba P2996 nop TARGET2701: ba RET2701 nop P2996: !_MEMBAR (FP) P2997: !_BST [6] (maybe <- 0x42800078) (FP) (Branch target of P2791) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 64 ] %asi ba P2998 nop TARGET2791: ba RET2791 nop P2998: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET2998 nop RET2998: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P2999: !_BSTC [23] (maybe <- 0x4280007a) (FP) (Branch target of P2707) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi ba P3000 nop TARGET2707: ba RET2707 nop P3000: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3000 nop RET3000: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3001: !_PREFETCH [19] (Int) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 0], 1 P3002: !_LD [14] (FP) (CBR) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ld [%i2 + 64], %f6 ! 1 addresses covered ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3002 nop RET3002: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P3003: !_REPLACEMENT [29] (Int) (CBR) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l6 ld [%i3+64], %o5 st %o5, [%i3+64] add %i3, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3003 nop RET3003: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P3004: !_MEMBAR (FP) P3005: !_BST [32] (maybe <- 0x4280007d) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 256 ] %asi P3006: !_MEMBAR (FP) membar #StoreLoad P3007: !_PREFETCH [7] (Int) (LE) wr %g0, 0x88, %asi prefetcha [%i0 + 128] %asi, 1 P3008: !_MEMBAR (FP) (CBR) (Secondary ctx) (Branch target of P2692) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3008 nop RET3008: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P3009 nop TARGET2692: ba RET2692 nop P3009: !_BLD [10] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i1 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 P3010: !_MEMBAR (FP) (Secondary ctx) P3011: !_BLD [22] (FP) (Branch target of P3152) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f8 fmovd %f40, %f10 ba P3012 nop TARGET3152: ba RET3152 nop P3012: !_MEMBAR (FP) P3013: !_BSTC [26] (maybe <- 0x4280007e) (FP) (Secondary ctx) wr %g0, 0xe1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 128 ] %asi P3014: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P3015: !_BLD [13] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 fmovs %f19, %f12 fmovd %f40, %f18 fmovs %f18, %f13 P3016: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3016 nop RET3016: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P3017: !_LD [0] (FP) ld [%i0 + 0], %f14 ! 1 addresses covered P3018: !_ST [19] (maybe <- 0x3000009) (Int) (CBR) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stwa %l4, [%i3 + 0] %asi add %l4, 1, %l4 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3018 nop RET3018: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P3019: !_MEMBAR (FP) membar #StoreLoad P3020: !_BLD [21] (FP) (Branch target of P3129) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovs %f19, %f0 fmovd %f40, %f18 fmovs %f18, %f1 ba P3021 nop TARGET3129: ba RET3129 nop P3021: !_MEMBAR (FP) P3022: !_ST [31] (maybe <- 0x42800080) (FP) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 192 ] P3023: !_REPLACEMENT [23] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+32], %l7 st %l7, [%i2+32] add %i2, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] P3024: !_MEMBAR (FP) (Branch target of P3235) membar #StoreLoad ba P3025 nop TARGET3235: ba RET3235 nop P3025: !_BLD [12] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f2 fmovd %f40, %f4 P3026: !_MEMBAR (FP) (Branch target of P3490) ba P3027 nop TARGET3490: ba RET3490 nop P3027: !_REPLACEMENT [20] (Int) sethi %hi(0x2000), %o5 ld [%i2+256], %l6 st %l6, [%i2+256] add %i2, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] P3028: !_REPLACEMENT [20] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(0x2000), %l7 ld [%i2+256], %l3 st %l3, [%i2+256] add %i2, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] P3029: !_MEMBAR (FP) P3030: !_BST [6] (maybe <- 0x42800081) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 64 ] %asi P3031: !_MEMBAR (FP) (Branch target of P2858) membar #StoreLoad ba P3032 nop TARGET2858: ba RET2858 nop P3032: !_REPLACEMENT [12] (Int) (Branch target of P3061) sethi %hi(0x2000), %l3 ld [%i2+4], %l7 st %l7, [%i2+4] add %i2, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] ba P3033 nop TARGET3061: ba RET3061 nop P3033: !_MEMBAR (FP) membar #StoreLoad P3034: !_BLD [3] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 fmovs %f19, %f6 fmovd %f34, %f18 fmovs %f18, %f7 fmovd %f36, %f8 fmovd %f40, %f18 fmovs %f18, %f9 P3035: !_MEMBAR (FP) P3036: !_PREFETCH [2] (Int) prefetch [%i0 + 8], 1 P3037: !_LD [26] (Int) (Branch target of P3366) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduw [%i2 + 128], %l3 ! move %l3(lower) -> %o2(lower) or %l3, %o2, %o2 ba P3038 nop TARGET3366: ba RET3366 nop P3038: !_MEMBAR (FP) (CBR) (Secondary ctx) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3038 nop RET3038: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3039: !_BLD [25] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i2 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f10 fmovd %f40, %f18 fmovs %f18, %f11 P3040: !_MEMBAR (FP) (Secondary ctx) (Branch target of P2672) ba P3041 nop TARGET2672: ba RET2672 nop P3041: !_LD [24] (Int) lduw [%i2 + 64], %o3 ! move %o3(lower) -> %o3(upper) sllx %o3, 32, %o3 P3042: !_REPLACEMENT [26] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+128], %l7 st %l7, [%i3+128] add %i3, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] P3043: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P3044: !_BLD [9] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f12 fmovd %f40, %f18 fmovs %f18, %f13 P3045: !_MEMBAR (FP) (Secondary ctx) P3046: !_REPLACEMENT [8] (Int) (CBR) sethi %hi(0x2000), %o5 ld [%i3+0], %l6 st %l6, [%i3+0] add %i3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3046 nop RET3046: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3047: !_MEMBAR (FP) P3048: !_BSTC [26] (maybe <- 0x42800083) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 128 ] %asi P3049: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3049 nop RET3049: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3050: !_BLD [3] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f14 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f34, %f0 fmovd %f36, %f18 fmovs %f18, %f1 fmovd %f40, %f2 P3051: !_MEMBAR (FP) P3052: !_PREFETCH [12] (Int) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 4], 1 P3053: !_MEMBAR (FP) (Branch target of P3545) ba P3054 nop TARGET3545: ba RET3545 nop P3054: !_BSTC [22] (maybe <- 0x42800085) (FP) (Branch target of P3049) wr %g0, 0xe0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi ba P3055 nop TARGET3049: ba RET3049 nop P3055: !_MEMBAR (FP) (Branch target of P3238) membar #StoreLoad ba P3056 nop TARGET3238: ba RET3238 nop P3056: !_LD [31] (Int) (Nucleus ctx) (Branch target of P3000) wr %g0, 0x4, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduwa [%i2 + 192] %asi, %o5 ! move %o5(lower) -> %o3(lower) or %o5, %o3, %o3 ba P3057 nop TARGET3000: ba RET3000 nop P3057: !_PREFETCH [7] (Int) (Nucleus ctx) (Branch target of P3475) wr %g0, 0x4, %asi prefetcha [%i0 + 128] %asi, 1 ba P3058 nop TARGET3475: ba RET3475 nop P3058: !_REPLACEMENT [1] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+4], %l7 st %l7, [%i3+4] add %i3, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] P3059: !_MEMBAR (FP) membar #StoreLoad P3060: !_BLD [16] (FP) (Branch target of P2805) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f36, %f18 fmovs %f18, %f3 ba P3061 nop TARGET2805: ba RET2805 nop P3061: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3061 nop RET3061: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3062: !_BLD [29] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f4 P3063: !_MEMBAR (FP) P3064: !_PREFETCH [11] (Int) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 0], 1 P3065: !_REPLACEMENT [12] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+4], %l7 st %l7, [%i3+4] add %i3, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] P3066: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3066 nop RET3066: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3067: !_BLD [25] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 fmovd %f40, %f6 P3068: !_MEMBAR (FP) (Branch target of P3298) ba P3069 nop TARGET3298: ba RET3298 nop P3069: !_REPLACEMENT [28] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(0x2000), %l3 ld [%i3+0], %l7 st %l7, [%i3+0] add %i3, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] P3070: !_ST [25] (maybe <- 0x42800088) (FP) (Secondary ctx) wr %g0, 0x81, %asi ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i2 + 96 ] %asi P3071: !_REPLACEMENT [14] (Int) (CBR) sethi %hi(0x2000), %l7 ld [%i3+64], %l3 st %l3, [%i3+64] add %i3, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3071 nop RET3071: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3072: !_MEMBAR (FP) (Branch target of P3324) ba P3073 nop TARGET3324: ba RET3324 nop P3073: !_BST [8] (maybe <- 0x42800089) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i1 + 0 ] %asi P3074: !_MEMBAR (FP) membar #StoreLoad P3075: !_REPLACEMENT [15] (Int) sethi %hi(0x2000), %l6 ld [%i3+128], %o5 st %o5, [%i3+128] add %i3, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] P3076: !_REPLACEMENT [7] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(0x2000), %l3 ld [%i3+128], %l7 st %l7, [%i3+128] add %i3, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] P3077: !_MEMBAR (FP) (CBR) (Branch target of P3488) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3077 nop RET3077: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 ba P3078 nop TARGET3488: ba RET3488 nop P3078: !_BSTC [11] (maybe <- 0x4280008b) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P3079: !_MEMBAR (FP) (Branch target of P3071) membar #StoreLoad ba P3080 nop TARGET3071: ba RET3071 nop P3080: !_LD [31] (Int) (CBR) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduwa [%i2 + 192] %asi, %o4 ! move %o4(lower) -> %o4(upper) sllx %o4, 32, %o4 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3080 nop RET3080: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3081: !_LD [18] (FP) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ld [%i3 + 128], %f7 ! 1 addresses covered P3082: !_LD [16] (FP) (Secondary ctx) (Branch target of P3427) wr %g0, 0x81, %asi lda [%i3 + 16] %asi, %f8 ! 1 addresses covered ba P3083 nop TARGET3427: ba RET3427 nop P3083: !_MEMBAR (FP) P3084: !_BST [6] (maybe <- 0x4280008e) (FP) (Branch target of P3446) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 64 ] %asi ba P3085 nop TARGET3446: ba RET3446 nop P3085: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3085 nop RET3085: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3086: !_BLD [24] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f9 fmovd %f40, %f10 P3087: !_MEMBAR (FP) P3088: !_IDC_FLIP [24] (Int) IDC_FLIP(3088, 20427, 6, 0x45800040, 0x40, %i2, 0x40, %l6, %l7, %o5, %l3) P3089: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3089 nop RET3089: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3090: !_BLD [15] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 P3091: !_MEMBAR (FP) P3092: !_BLD [16] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f36, %f12 P3093: !_MEMBAR (FP) P3094: !_REPLACEMENT [9] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+32], %l3 st %l3, [%i3+32] add %i3, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] P3095: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3095 nop RET3095: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3096: !_BST [20] (maybe <- 0x42800090) (FP) (Branch target of P3138) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 256 ] %asi ba P3097 nop TARGET3138: ba RET3138 nop P3097: !_MEMBAR (FP) (CBR) (Branch target of P3038) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3097 nop RET3097: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P3098 nop TARGET3038: ba RET3038 nop P3098: !_ST [16] (maybe <- 0x42800091) (FP) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i3 + 16 ] %asi P3099: !_LD [17] (Int) (CBR) lduw [%i3 + 96], %l7 ! move %l7(lower) -> %o4(lower) or %l7, %o4, %o4 !---- flushing int results buffer---- mov %o0, %l5 mov %o1, %l5 mov %o2, %l5 mov %o3, %l5 mov %o4, %l5 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3099 nop RET3099: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3100: !_LD [23] (Int) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduw [%i2 + 32], %o0 ! move %o0(lower) -> %o0(upper) sllx %o0, 32, %o0 P3101: !_IDC_FLIP [21] (Int) (CBR) IDC_FLIP(3101, 1385, 6, 0x45800000, 0x0, %i2, 0x0, %l6, %l7, %o5, %l3) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3101 nop RET3101: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3102: !_MEMBAR (FP) P3103: !_BSTC [12] (maybe <- 0x42800092) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P3104: !_MEMBAR (FP) P3105: !_BSTC [29] (maybe <- 0x42800095) (FP) (CBR) wr %g0, 0xe0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3105 nop RET3105: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P3106: !_MEMBAR (FP) membar #StoreLoad P3107: !_ST [21] (maybe <- 0x42800096) (FP) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 0 ] P3108: !_IDC_FLIP [21] (Int) IDC_FLIP(3108, 3487, 6, 0x45800000, 0x0, %i3, 0x0, %l6, %l7, %o5, %l3) P3109: !_MEMBAR (FP) P3110: !_BSTC [3] (maybe <- 0x42800097) (FP) (CBR) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3110 nop RET3110: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P3111: !_MEMBAR (FP) membar #StoreLoad P3112: !_LD [7] (Int) (LE) (Branch target of P2978) wr %g0, 0x88, %asi lduwa [%i0 + 128] %asi, %l7 ! move %l7(lower) -> %o0(lower) or %l7, %o0, %o0 ba P3113 nop TARGET2978: ba RET2978 nop P3113: !_MEMBAR (FP) (Branch target of P3363) membar #StoreLoad ba P3114 nop TARGET3363: ba RET3363 nop P3114: !_BLD [18] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 P3115: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3115 nop RET3115: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3116: !_ST [14] (maybe <- 0x4280009c) (FP) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 64 ] P3117: !_LD [13] (FP) (Secondary ctx) wr %g0, 0x81, %asi lda [%i3 + 32] %asi, %f14 ! 1 addresses covered P3118: !_MEMBAR (FP) (Branch target of P3008) membar #StoreLoad ba P3119 nop TARGET3008: ba RET3008 nop P3119: !_BLD [3] (FP) (Branch target of P3205) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovs %f19, %f0 fmovd %f34, %f18 fmovs %f18, %f1 fmovd %f36, %f2 fmovd %f40, %f18 fmovs %f18, %f3 ba P3120 nop TARGET3205: ba RET3205 nop P3120: !_MEMBAR (FP) (Branch target of P3139) ba P3121 nop TARGET3139: ba RET3139 nop P3121: !_BST [1] (maybe <- 0x4280009d) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P3122: !_MEMBAR (FP) membar #StoreLoad P3123: !_BLD [30] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f4 P3124: !_MEMBAR (FP) (Branch target of P2724) ba P3125 nop TARGET2724: ba RET2724 nop P3125: !_BSTC [9] (maybe <- 0x428000a2) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i1 + 0 ] %asi P3126: !_MEMBAR (FP) membar #StoreLoad P3127: !_REPLACEMENT [29] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l6 ld [%i3+64], %o5 st %o5, [%i3+64] add %i3, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] P3128: !_REPLACEMENT [2] (Int) sethi %hi(0x2000), %l3 ld [%i3+8], %l7 st %l7, [%i3+8] add %i3, %l3, %l6 ld [%l6+8], %l7 st %l7, [%l6+8] add %l6, %l3, %l6 ld [%l6+8], %l7 st %l7, [%l6+8] add %l6, %l3, %l6 ld [%l6+8], %l7 st %l7, [%l6+8] add %l6, %l3, %l6 ld [%l6+8], %l7 st %l7, [%l6+8] add %l6, %l3, %l6 ld [%l6+8], %l7 st %l7, [%l6+8] add %l6, %l3, %l6 ld [%l6+8], %l7 st %l7, [%l6+8] add %l6, %l3, %l6 ld [%l6+8], %l7 st %l7, [%l6+8] P3129: !_MEMBAR (FP) (CBR) (Branch target of P3150) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3129 nop RET3129: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 ba P3130 nop TARGET3150: ba RET3150 nop P3130: !_BLD [27] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 fmovd %f40, %f6 P3131: !_MEMBAR (FP) (Branch target of P3522) ba P3132 nop TARGET3522: ba RET3522 nop P3132: !_BST [33] (maybe <- 0x428000a4) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 0 ] %asi P3133: !_MEMBAR (FP) membar #StoreLoad P3134: !_PREFETCH [31] (Int) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 192], 1 P3135: !_MEMBAR (FP) (Branch target of P3099) membar #StoreLoad ba P3136 nop TARGET3099: ba RET3099 nop P3136: !_BLD [31] (FP) (Branch target of P2758) wr %g0, 0xf0, %asi ldda [%i2 + 192] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 ba P3137 nop TARGET2758: ba RET2758 nop P3137: !_MEMBAR (FP) P3138: !_PREFETCH [22] (Int) (CBR) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetcha [%i3 + 4] %asi, 1 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3138 nop RET3138: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3139: !_REPLACEMENT [5] (Int) (CBR) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+64], %l7 st %l7, [%i2+64] add %i2, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3139 nop RET3139: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3140: !_MEMBAR (FP) membar #StoreLoad P3141: !_BLD [25] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f8 fmovd %f40, %f18 fmovs %f18, %f9 P3142: !_MEMBAR (FP) P3143: !_BSTC [22] (maybe <- 0x428000a5) (FP) (Secondary ctx) wr %g0, 0xe1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P3144: !_MEMBAR (FP) (Secondary ctx) P3145: !_BSTC [24] (maybe <- 0x428000a8) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 64 ] %asi P3146: !_MEMBAR (FP) membar #StoreLoad P3147: !_BLD [6] (FP) (Branch target of P2857) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f10 fmovd %f40, %f18 fmovs %f18, %f11 ba P3148 nop TARGET2857: ba RET2857 nop P3148: !_MEMBAR (FP) P3149: !_BST [32] (maybe <- 0x428000aa) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 256 ] %asi P3150: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3150 nop RET3150: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3151: !_REPLACEMENT [24] (Int) (CBR) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(0x2000), %l7 ld [%i2+64], %l3 st %l3, [%i2+64] add %i2, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3151 nop RET3151: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3152: !_ST [21] (maybe <- 0x300000a) (Int) (CBR) (Secondary ctx) (Branch target of P3502) wr %g0, 0x81, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 stwa %l4, [%i2 + 0] %asi add %l4, 1, %l4 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3152 nop RET3152: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P3153 nop TARGET3502: ba RET3502 nop P3153: !_REPLACEMENT [31] (Int) (CBR) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+192], %l3 st %l3, [%i3+192] add %i3, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3153 nop RET3153: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3154: !_REPLACEMENT [21] (Int) (CBR) sethi %hi(0x2000), %l7 ld [%i3+0], %l3 st %l3, [%i3+0] add %i3, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3154 nop RET3154: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3155: !_MEMBAR (FP) membar #StoreLoad P3156: !_BLD [11] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f12 fmovd %f40, %f14 P3157: !_MEMBAR (FP) P3158: !_LD [15] (Int) lduw [%i2 + 128], %o1 ! move %o1(lower) -> %o1(upper) sllx %o1, 32, %o1 P3159: !_ST [1] (maybe <- 0x428000ab) (FP) (Nucleus ctx) wr %g0, 0x4, %asi ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i0 + 4 ] %asi P3160: !_MEMBAR (FP) P3161: !_BST [23] (maybe <- 0x428000ac) (FP) (CBR) (Branch target of P3218) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3161 nop RET3161: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P3162 nop TARGET3218: ba RET3218 nop P3162: !_MEMBAR (FP) membar #StoreLoad P3163: !_ST [4] (maybe <- 0x300000b) (Int) stw %l4, [%i0 + 32 ] add %l4, 1, %l4 P3164: !_MEMBAR (FP) (Secondary ctx) P3165: !_BST [1] (maybe <- 0x428000af) (FP) (Secondary ctx) (Branch target of P2709) wr %g0, 0xf1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi ba P3166 nop TARGET2709: ba RET2709 nop P3166: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P3167: !_REPLACEMENT [21] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l6 ld [%i2+0], %o5 st %o5, [%i2+0] add %i2, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] P3168: !_LD [26] (Int) lduw [%i3 + 128], %l6 ! move %l6(lower) -> %o1(lower) or %l6, %o1, %o1 P3169: !_MEMBAR (FP) membar #StoreLoad P3170: !_BLD [4] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovs %f19, %f0 fmovd %f34, %f18 fmovs %f18, %f1 fmovd %f36, %f2 fmovd %f40, %f18 fmovs %f18, %f3 P3171: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3171 nop RET3171: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3172: !_PREFETCH [5] (Int) prefetch [%i0 + 64], 1 P3173: !_REPLACEMENT [12] (Int) (CBR) sethi %hi(0x2000), %o5 ld [%i2+4], %l6 st %l6, [%i2+4] add %i2, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3173 nop RET3173: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3174: !_REPLACEMENT [11] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(0x2000), %o5 ld [%i2+0], %l6 st %l6, [%i2+0] add %i2, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] P3175: !_PREFETCH [25] (Int) (Secondary ctx) (Branch target of P2873) wr %g0, 0x81, %asi prefetcha [%i3 + 96] %asi, 1 ba P3176 nop TARGET2873: ba RET2873 nop P3176: !_MEMBAR (FP) P3177: !_BST [17] (maybe <- 0x428000b4) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f40 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 64 ] %asi P3178: !_MEMBAR (FP) membar #StoreLoad P3179: !_BLD [10] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i1 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f4 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3179 nop RET3179: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3180: !_MEMBAR (FP) (CBR) (Branch target of P2690) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3180 nop RET3180: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P3181 nop TARGET2690: ba RET2690 nop P3181: !_BST [15] (maybe <- 0x428000b5) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 128 ] %asi P3182: !_MEMBAR (FP) membar #StoreLoad P3183: !_ST [26] (maybe <- 0x428000b6) (FP) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i3 + 128 ] %asi P3184: !_MEMBAR (FP) (Branch target of P3424) membar #StoreLoad ba P3185 nop TARGET3424: ba RET3424 nop P3185: !_BLD [13] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 fmovs %f19, %f6 fmovd %f40, %f18 fmovs %f18, %f7 P3186: !_MEMBAR (FP) P3187: !_BLD [24] (FP) (Branch target of P2650) wr %g0, 0xf0, %asi ldda [%i3 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f8 fmovd %f40, %f18 fmovs %f18, %f9 ba P3188 nop TARGET2650: ba RET2650 nop P3188: !_MEMBAR (FP) P3189: !_REPLACEMENT [27] (Int) (Nucleus ctx) (Branch target of P3355) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l6 ld [%i2+160], %o5 st %o5, [%i2+160] add %i2, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] ba P3190 nop TARGET3355: ba RET3355 nop P3190: !_MEMBAR (FP) P3191: !_BST [29] (maybe <- 0x428000b7) (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3191 nop RET3191: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3192: !_MEMBAR (FP) (CBR) (Branch target of P3200) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3192 nop RET3192: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P3193 nop TARGET3200: ba RET3200 nop P3193: !_REPLACEMENT [10] (Int) sethi %hi(0x2000), %l6 ld [%i2+64], %o5 st %o5, [%i2+64] add %i2, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] P3194: !_REPLACEMENT [7] (Int) sethi %hi(0x2000), %l3 ld [%i2+128], %l7 st %l7, [%i2+128] add %i2, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] P3195: !_PREFETCH [30] (Int) (CBR) prefetch [%i3 + 128], 1 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3195 nop RET3195: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3196: !_REPLACEMENT [33] (Int) sethi %hi(0x2000), %l3 ld [%i2+0], %l7 st %l7, [%i2+0] add %i2, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] P3197: !_REPLACEMENT [13] (Int) sethi %hi(0x2000), %o5 ld [%i2+32], %l6 st %l6, [%i2+32] add %i2, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] P3198: !_IDC_FLIP [13] (Int) (CBR) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 IDC_FLIP(3198, 3242, 6, 0x44000020, 0x20, %i2, 0x20, %l6, %l7, %o5, %l3) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3198 nop RET3198: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3199: !_ST [29] (maybe <- 0x428000b8) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 64 ] P3200: !_FLUSHI [28] (Int) (CBR) flush %g0 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3200 nop RET3200: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3201: !_PREFETCH [15] (Int) prefetch [%i2 + 128], 1 P3202: !_REPLACEMENT [10] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+64], %l3 st %l3, [%i3+64] add %i3, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] add %o5, %l7, %o5 ld [%o5+64], %l3 st %l3, [%o5+64] P3203: !_REPLACEMENT [27] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(0x2000), %l6 ld [%i3+160], %o5 st %o5, [%i3+160] add %i3, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] P3204: !_IDC_FLIP [12] (Int) IDC_FLIP(3204, 27693, 6, 0x44000004, 0x4, %i2, 0x4, %l6, %l7, %o5, %l3) P3205: !_LD [24] (Int) (CBR) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduw [%i2 + 64], %o2 ! move %o2(lower) -> %o2(upper) sllx %o2, 32, %o2 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3205 nop RET3205: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3206: !_MEMBAR (FP) membar #StoreLoad P3207: !_BLD [26] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f10 fmovd %f40, %f18 fmovs %f18, %f11 P3208: !_MEMBAR (FP) (Branch target of P2966) ba P3209 nop TARGET2966: ba RET2966 nop P3209: !_REPLACEMENT [3] (Int) sethi %hi(0x2000), %l3 ld [%i3+16], %l7 st %l7, [%i3+16] add %i3, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] P3210: !_REPLACEMENT [30] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(0x2000), %o5 ld [%i3+128], %l6 st %l6, [%i3+128] add %i3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] P3211: !_PREFETCH [12] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetcha [%i3 + 4] %asi, 1 P3212: !_LD [1] (Int) (CBR) lduw [%i0 + 4], %o5 ! move %o5(lower) -> %o2(lower) or %o5, %o2, %o2 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3212 nop RET3212: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P3213: !_REPLACEMENT [24] (Int) (Branch target of P3426) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l6 ld [%i2+64], %o5 st %o5, [%i2+64] add %i2, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] add %l7, %l6, %l7 ld [%l7+64], %o5 st %o5, [%l7+64] ba P3214 nop TARGET3426: ba RET3426 nop P3214: !_ST [23] (maybe <- 0x428000b9) (FP) (Branch target of P3596) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 32 ] ba P3215 nop TARGET3596: ba RET3596 nop P3215: !_LD [26] (FP) ld [%i3 + 128], %f12 ! 1 addresses covered P3216: !_ST [33] (maybe <- 0x300000c) (Int) (CBR) sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 stw %l4, [%i2 + 0 ] add %l4, 1, %l4 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3216 nop RET3216: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3217: !_REPLACEMENT [12] (Int) (CBR) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %o5 ld [%i3+4], %l6 st %l6, [%i3+4] add %i3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3217 nop RET3217: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3218: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3218 nop RET3218: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3219: !_BSTC [10] (maybe <- 0x428000ba) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i1 + 64 ] %asi P3220: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3220 nop RET3220: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3221: !_BST [29] (maybe <- 0x428000bb) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 64 ] %asi P3222: !_MEMBAR (FP) P3223: !_BST [5] (maybe <- 0x428000bc) (FP) (CBR) (Branch target of P3115) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3223 nop RET3223: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P3224 nop TARGET3115: ba RET3115 nop P3224: !_MEMBAR (FP) (Branch target of P3046) membar #StoreLoad ba P3225 nop TARGET3046: ba RET3046 nop P3225: !_BLD [14] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 P3226: !_MEMBAR (FP) P3227: !_REPLACEMENT [26] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %o5 ld [%i2+128], %l6 st %l6, [%i2+128] add %i2, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] P3228: !_REPLACEMENT [9] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(0x2000), %l7 ld [%i2+32], %l3 st %l3, [%i2+32] add %i2, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] P3229: !_MEMBAR (FP) P3230: !_BSTC [17] (maybe <- 0x428000be) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f40 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 64 ] %asi P3231: !_MEMBAR (FP) membar #StoreLoad P3232: !_BLD [32] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f14 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3232 nop RET3232: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P3233: !_MEMBAR (FP) P3234: !_BST [16] (maybe <- 0x428000bf) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f36 membar #Sync stda %f32, [%i3 + 0 ] %asi P3235: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3235 nop RET3235: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P3236: !_ST [20] (maybe <- 0x428000c0) (FP) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i3 + 256 ] %asi P3237: !_MEMBAR (FP) (Branch target of P3254) ba P3238 nop TARGET3254: ba RET3254 nop P3238: !_BST [1] (maybe <- 0x428000c1) (FP) (CBR) (Branch target of P3481) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3238 nop RET3238: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 ba P3239 nop TARGET3481: ba RET3481 nop P3239: !_MEMBAR (FP) membar #StoreLoad P3240: !_ST [33] (maybe <- 0x428000c6) (FP) sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 0 ] P3241: !_PREFETCH [22] (Int) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 4], 1 P3242: !_LD [14] (FP) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ld [%i2 + 64], %f15 ! 1 addresses covered !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- P3243: !_REPLACEMENT [32] (Int) (CBR) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %o5 ld [%i3+256], %l6 st %l6, [%i3+256] add %i3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] add %l3, %o5, %l3 ld [%l3+256], %l6 st %l6, [%l3+256] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3243 nop RET3243: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3244: !_PREFETCH [25] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetcha [%i2 + 96] %asi, 1 P3245: !_MEMBAR (FP) (Branch target of P3365) ba P3246 nop TARGET3365: ba RET3365 nop P3246: !_BST [12] (maybe <- 0x428000c7) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P3247: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3247 nop RET3247: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3248: !_REPLACEMENT [30] (Int) (Branch target of P3464) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %o5 ld [%i2+128], %l6 st %l6, [%i2+128] add %i2, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] ba P3249 nop TARGET3464: ba RET3464 nop P3249: !_LD [10] (Int) (Nucleus ctx) (Branch target of P2708) wr %g0, 0x4, %asi lduwa [%i1 + 64] %asi, %o3 ! move %o3(lower) -> %o3(upper) sllx %o3, 32, %o3 ba P3250 nop TARGET2708: ba RET2708 nop P3250: !_ST [17] (maybe <- 0x300000d) (Int) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stw %l4, [%i3 + 96 ] add %l4, 1, %l4 P3251: !_LD [4] (Int) (Secondary ctx) wr %g0, 0x81, %asi lduwa [%i0 + 32] %asi, %l3 ! move %l3(lower) -> %o3(lower) or %l3, %o3, %o3 P3252: !_LD [2] (FP) ld [%i0 + 8], %f0 ! 1 addresses covered P3253: !_PREFETCH [15] (Int) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 128], 1 P3254: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3254 nop RET3254: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3255: !_BLD [18] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 P3256: !_MEMBAR (FP) P3257: !_REPLACEMENT [16] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+16], %l3 st %l3, [%i3+16] add %i3, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] add %o5, %l7, %o5 ld [%o5+16], %l3 st %l3, [%o5+16] P3258: !_MEMBAR (FP) P3259: !_BSTC [25] (maybe <- 0x428000ca) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 64 ] %asi P3260: !_MEMBAR (FP) membar #StoreLoad P3261: !_LD [21] (Int) (LE) wr %g0, 0x88, %asi lduwa [%i2 + 0] %asi, %o4 ! move %o4(lower) -> %o4(upper) sllx %o4, 32, %o4 P3262: !_MEMBAR (FP) (Branch target of P3510) ba P3263 nop TARGET3510: ba RET3510 nop P3263: !_BST [14] (maybe <- 0x428000cc) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 64 ] %asi P3264: !_MEMBAR (FP) (Branch target of P2704) membar #StoreLoad ba P3265 nop TARGET2704: ba RET2704 nop P3265: !_REPLACEMENT [3] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l6 ld [%i2+16], %o5 st %o5, [%i2+16] add %i2, %l6, %l7 ld [%l7+16], %o5 st %o5, [%l7+16] add %l7, %l6, %l7 ld [%l7+16], %o5 st %o5, [%l7+16] add %l7, %l6, %l7 ld [%l7+16], %o5 st %o5, [%l7+16] add %l7, %l6, %l7 ld [%l7+16], %o5 st %o5, [%l7+16] add %l7, %l6, %l7 ld [%l7+16], %o5 st %o5, [%l7+16] add %l7, %l6, %l7 ld [%l7+16], %o5 st %o5, [%l7+16] add %l7, %l6, %l7 ld [%l7+16], %o5 st %o5, [%l7+16] P3266: !_ST [8] (maybe <- 0x428000cd) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i1 + 0 ] P3267: !_ST [1] (maybe <- 0x428000ce) (FP) (Secondary ctx) wr %g0, 0x81, %asi ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i0 + 4 ] %asi P3268: !_MEMBAR (FP) P3269: !_BST [7] (maybe <- 0x428000cf) (FP) (CBR) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i0 + 128 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3269 nop RET3269: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3270: !_MEMBAR (FP) membar #StoreLoad P3271: !_BLD [27] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f2 fmovd %f40, %f18 fmovs %f18, %f3 P3272: !_MEMBAR (FP) P3273: !_BLD [30] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f4 P3274: !_MEMBAR (FP) P3275: !_BSTC [21] (maybe <- 0x428000d0) (FP) (Secondary ctx) wr %g0, 0xe1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P3276: !_MEMBAR (FP) (CBR) (Secondary ctx) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3276 nop RET3276: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3277: !_LD [18] (FP) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ld [%i3 + 128], %f5 ! 1 addresses covered P3278: !_ST [15] (maybe <- 0x428000d3) (FP) (CBR) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 128 ] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3278 nop RET3278: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3279: !_PREFETCH [28] (Int) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 0], 1 P3280: !_PREFETCH [4] (Int) (LE) (Secondary ctx) (Branch target of P2751) wr %g0, 0x89, %asi prefetcha [%i0 + 32] %asi, 1 ba P3281 nop TARGET2751: ba RET2751 nop P3281: !_MEMBAR (FP) (Branch target of P2691) ba P3282 nop TARGET2691: ba RET2691 nop P3282: !_BSTC [18] (maybe <- 0x428000d4) (FP) (CBR) wr %g0, 0xe0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 128 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3282 nop RET3282: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3283: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3283 nop RET3283: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3284: !_PREFETCH [31] (Int) (Secondary ctx) wr %g0, 0x81, %asi prefetcha [%i3 + 192] %asi, 1 P3285: !_MEMBAR (FP) membar #StoreLoad P3286: !_BLD [24] (FP) (Branch target of P2663) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f6 fmovd %f40, %f18 fmovs %f18, %f7 ba P3287 nop TARGET2663: ba RET2663 nop P3287: !_MEMBAR (FP) P3288: !_BSTC [30] (maybe <- 0x428000d5) (FP) (Secondary ctx) wr %g0, 0xe1, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 128 ] %asi P3289: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P3290: !_BLD [6] (FP) (Secondary ctx) (Branch target of P2696) wr %g0, 0xf1, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f8 fmovd %f40, %f18 fmovs %f18, %f9 ba P3291 nop TARGET2696: ba RET2696 nop P3291: !_MEMBAR (FP) (Secondary ctx) P3292: !_BLD [20] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f10 P3293: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3293 nop RET3293: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3294: !_BLD [25] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 fmovd %f40, %f12 P3295: !_MEMBAR (FP) P3296: !_BLD [28] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 P3297: !_MEMBAR (FP) (Branch target of P3003) ba P3298 nop TARGET3003: ba RET3003 nop P3298: !_ST [21] (maybe <- 0x300000e) (Int) (CBR) (Nucleus ctx) (Branch target of P3560) wr %g0, 0x4, %asi stwa %l4, [%i2 + 0] %asi add %l4, 1, %l4 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3298 nop RET3298: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P3299 nop TARGET3560: ba RET3560 nop P3299: !_REPLACEMENT [13] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %o5 ld [%i2+32], %l6 st %l6, [%i2+32] add %i2, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] P3300: !_MEMBAR (FP) membar #StoreLoad P3301: !_BLD [29] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f14 P3302: !_MEMBAR (FP) P3303: !_BST [23] (maybe <- 0x428000d6) (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3303 nop RET3303: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3304: !_MEMBAR (FP) P3305: !_BST [5] (maybe <- 0x428000d9) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 64 ] %asi P3306: !_MEMBAR (FP) (Branch target of P3636) membar #StoreLoad ba P3307 nop TARGET3636: ba RET3636 nop P3307: !_ST [15] (maybe <- 0x428000db) (FP) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 128 ] P3308: !_MEMBAR (FP) (Secondary ctx) P3309: !_BST [16] (maybe <- 0x428000dc) (FP) (CBR) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f36 membar #Sync stda %f32, [%i3 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3309 nop RET3309: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3310: !_MEMBAR (FP) (CBR) (Secondary ctx) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3310 nop RET3310: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P3311: !_BLD [9] (FP) wr %g0, 0xf0, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f40, %f0 P3312: !_MEMBAR (FP) P3313: !_BST [19] (maybe <- 0x428000dd) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 0 ] %asi P3314: !_MEMBAR (FP) membar #StoreLoad P3315: !_BLD [2] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 fmovs %f19, %f2 fmovd %f34, %f18 fmovs %f18, %f3 fmovd %f36, %f4 fmovd %f40, %f18 fmovs %f18, %f5 P3316: !_MEMBAR (FP) P3317: !_ST [7] (maybe <- 0x428000de) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i0 + 128 ] P3318: !_MEMBAR (FP) P3319: !_BSTC [0] (maybe <- 0x428000df) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P3320: !_MEMBAR (FP) membar #StoreLoad P3321: !_REPLACEMENT [7] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+128], %l3 st %l3, [%i3+128] add %i3, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] P3322: !_MEMBAR (FP) P3323: !_BSTC [28] (maybe <- 0x428000e4) (FP) (Branch target of P2836) wr %g0, 0xe0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 0 ] %asi ba P3324 nop TARGET2836: ba RET2836 nop P3324: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3324 nop RET3324: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P3325: !_BLD [4] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f6 fmovd %f34, %f8 fmovd %f36, %f18 fmovs %f18, %f9 fmovd %f40, %f10 P3326: !_MEMBAR (FP) (CBR) (Branch target of P3455) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3326 nop RET3326: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P3327 nop TARGET3455: ba RET3455 nop P3327: !_BSTC [9] (maybe <- 0x428000e5) (FP) (Branch target of P3179) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i1 + 0 ] %asi ba P3328 nop TARGET3179: ba RET3179 nop P3328: !_MEMBAR (FP) membar #StoreLoad P3329: !_BLD [27] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 fmovd %f40, %f12 P3330: !_MEMBAR (FP) P3331: !_LD [17] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduwa [%i2 + 96] %asi, %l7 ! move %l7(lower) -> %o4(lower) or %l7, %o4, %o4 !---- flushing int results buffer---- mov %o0, %l5 mov %o1, %l5 mov %o2, %l5 mov %o3, %l5 mov %o4, %l5 P3332: !_MEMBAR (FP) P3333: !_BST [27] (maybe <- 0x428000e7) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 128 ] %asi P3334: !_MEMBAR (FP) membar #StoreLoad P3335: !_FLUSHI [24] (Int) flush %g0 P3336: !_REPLACEMENT [32] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+256], %l3 st %l3, [%i3+256] add %i3, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] add %o5, %l7, %o5 ld [%o5+256], %l3 st %l3, [%o5+256] P3337: !_PREFETCH [13] (Int) (CBR) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetcha [%i2 + 32] %asi, 1 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3337 nop RET3337: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3338: !_MEMBAR (FP) (Branch target of P3220) ba P3339 nop TARGET3220: ba RET3220 nop P3339: !_BST [23] (maybe <- 0x428000e9) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P3340: !_MEMBAR (FP) (Branch target of P3276) ba P3341 nop TARGET3276: ba RET3276 nop P3341: !_BST [23] (maybe <- 0x428000ec) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P3342: !_MEMBAR (FP) membar #StoreLoad P3343: !_REPLACEMENT [12] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+4], %l7 st %l7, [%i2+4] add %i2, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] add %l6, %l3, %l6 ld [%l6+4], %l7 st %l7, [%l6+4] P3344: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3344 nop RET3344: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3345: !_BLD [27] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 fmovd %f40, %f14 P3346: !_MEMBAR (FP) P3347: !_BLD [16] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f36, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- P3348: !_MEMBAR (FP) (Branch target of P3191) ba P3349 nop TARGET3191: ba RET3191 nop P3349: !_PREFETCH [31] (Int) (Branch target of P3407) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 192], 1 ba P3350 nop TARGET3407: ba RET3407 nop P3350: !_LD [25] (FP) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ld [%i3 + 96], %f0 ! 1 addresses covered P3351: !_MEMBAR (FP) (Branch target of P2972) membar #StoreLoad ba P3352 nop TARGET2972: ba RET2972 nop P3352: !_BLD [21] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 fmovs %f19, %f2 fmovd %f40, %f18 fmovs %f18, %f3 P3353: !_MEMBAR (FP) (Branch target of P3536) ba P3354 nop TARGET3536: ba RET3536 nop P3354: !_REPLACEMENT [7] (Int) (Branch target of P3529) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+128], %l7 st %l7, [%i2+128] add %i2, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] add %l6, %l3, %l6 ld [%l6+128], %l7 st %l7, [%l6+128] ba P3355 nop TARGET3529: ba RET3529 nop P3355: !_ST [22] (maybe <- 0x300000f) (Int) (CBR) stw %l4, [%i3 + 4 ] add %l4, 1, %l4 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3355 nop RET3355: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3356: !_PREFETCH [14] (Int) (CBR) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetcha [%i3 + 64] %asi, 1 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3356 nop RET3356: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3357: !_REPLACEMENT [27] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(0x2000), %l3 ld [%i2+160], %l7 st %l7, [%i2+160] add %i2, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] P3358: !_REPLACEMENT [23] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(0x2000), %o5 ld [%i2+32], %l6 st %l6, [%i2+32] add %i2, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] P3359: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3359 nop RET3359: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3360: !_BLD [25] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f4 fmovd %f40, %f18 fmovs %f18, %f5 P3361: !_MEMBAR (FP) P3362: !_LD [23] (Int) lduw [%i2 + 32], %o0 ! move %o0(lower) -> %o0(upper) sllx %o0, 32, %o0 P3363: !_LD [16] (Int) (LE) (CBR) (Nucleus ctx) (Branch target of P3552) wr %g0, 0xc, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lduwa [%i3 + 16] %asi, %l7 ! move %l7(lower) -> %o0(lower) or %l7, %o0, %o0 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3363 nop RET3363: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 ba P3364 nop TARGET3552: ba RET3552 nop P3364: !_PREFETCH [19] (Int) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 0], 1 P3365: !_ST [26] (maybe <- 0x3000010) (Int) (CBR) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stw %l4, [%i3 + 128 ] add %l4, 1, %l4 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3365 nop RET3365: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3366: !_REPLACEMENT [23] (Int) (CBR) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+32], %l7 st %l7, [%i2+32] add %i2, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] add %l6, %l3, %l6 ld [%l6+32], %l7 st %l7, [%l6+32] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3366 nop RET3366: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3367: !_REPLACEMENT [17] (Int) sethi %hi(0x2000), %l3 ld [%i2+96], %l7 st %l7, [%i2+96] add %i2, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] add %l6, %l3, %l6 ld [%l6+96], %l7 st %l7, [%l6+96] P3368: !_MEMBAR (FP) P3369: !_BST [12] (maybe <- 0x428000ef) (FP) (Branch target of P2906) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi ba P3370 nop TARGET2906: ba RET2906 nop P3370: !_MEMBAR (FP) P3371: !_BSTC [19] (maybe <- 0x428000f2) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 0 ] %asi P3372: !_MEMBAR (FP) membar #StoreLoad P3373: !_PREFETCH [16] (Int) (Secondary ctx) (Branch target of P2677) wr %g0, 0x81, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetcha [%i3 + 16] %asi, 1 ba P3374 nop TARGET2677: ba RET2677 nop P3374: !_PREFETCH [19] (Int) (Nucleus ctx) wr %g0, 0x4, %asi prefetcha [%i2 + 0] %asi, 1 P3375: !_MEMBAR (FP) P3376: !_BST [29] (maybe <- 0x428000f3) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 64 ] %asi P3377: !_MEMBAR (FP) (Branch target of P3110) membar #StoreLoad ba P3378 nop TARGET3110: ba RET3110 nop P3378: !_ST [3] (maybe <- 0x428000f4) (FP) (Secondary ctx) (Branch target of P3543) wr %g0, 0x81, %asi ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i0 + 16 ] %asi ba P3379 nop TARGET3543: ba RET3543 nop P3379: !_REPLACEMENT [9] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %o5 ld [%i3+32], %l6 st %l6, [%i3+32] add %i3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] P3380: !_REPLACEMENT [13] (Int) (CBR) sethi %hi(0x2000), %l7 ld [%i3+32], %l3 st %l3, [%i3+32] add %i3, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3380 nop RET3380: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3381: !_MEMBAR (FP) membar #StoreLoad P3382: !_BLD [11] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f6 fmovd %f40, %f8 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3382 nop RET3382: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3383: !_MEMBAR (FP) (Branch target of P2929) ba P3384 nop TARGET2929: ba RET2929 nop P3384: !_BLD [5] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f9 fmovd %f40, %f10 P3385: !_MEMBAR (FP) P3386: !_BLD [27] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 fmovd %f40, %f12 P3387: !_MEMBAR (FP) P3388: !_BLD [7] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 P3389: !_MEMBAR (FP) P3390: !_BLD [7] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f14 P3391: !_MEMBAR (FP) P3392: !_BLD [18] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- P3393: !_MEMBAR (FP) P3394: !_BLD [2] (FP) (Branch target of P3564) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f0 membar #Sync ! 5 addresses covered fmovs %f4, %f3 fmovd %f8, %f4 ba P3395 nop TARGET3564: ba RET3564 nop P3395: !_MEMBAR (FP) (Loop exit) !---- flushing int results buffer---- mov %o0, %l5 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovs %f4, %f30 !-- loop_exit_6_2: sub %l2, 1, %l2 cmp %l2, 0 bg loop_entry_6_2 nop P3396: !_MEMBAR (FP) (Loop entry) sethi %hi(0x1), %l2 or %l2, %lo(0x1), %l2 loop_entry_6_3: P3397: !_BSTC [32] (maybe <- 0x428000f5) (FP) (CBR) (Branch target of P3589) wr %g0, 0xe0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 256 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3397 nop RET3397: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 ba P3398 nop TARGET3589: ba RET3589 nop P3398: !_MEMBAR (FP) P3399: !_BST [17] (maybe <- 0x428000f6) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f40 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 64 ] %asi P3400: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3400 nop RET3400: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3401: !_BSTC [20] (maybe <- 0x428000f7) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 256 ] %asi P3402: !_MEMBAR (FP) membar #StoreLoad P3403: !_BLD [28] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f0 membar #Sync ! 1 addresses covered P3404: !_MEMBAR (FP) P3405: !_BLD [0] (FP) (CBR) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 fmovs %f19, %f2 fmovd %f34, %f18 fmovs %f18, %f3 fmovd %f36, %f4 fmovd %f40, %f18 fmovs %f18, %f5 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3405 nop RET3405: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3406: !_MEMBAR (FP) (Secondary ctx) (Branch target of P3171) ba P3407 nop TARGET3171: ba RET3171 nop P3407: !_BLD [29] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i2 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f6 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3407 nop RET3407: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P3408: !_MEMBAR (FP) P3409: !_ST [1] (maybe <- 0x3000011) (Int) stw %l4, [%i0 + 4 ] add %l4, 1, %l4 P3410: !_ST [1] (maybe <- 0x3000012) (Int) (Secondary ctx) wr %g0, 0x81, %asi stwa %l4, [%i0 + 4] %asi add %l4, 1, %l4 P3411: !_REPLACEMENT [26] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %o5 ld [%i3+128], %l6 st %l6, [%i3+128] add %i3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] add %l3, %o5, %l3 ld [%l3+128], %l6 st %l6, [%l3+128] P3412: !_MEMBAR (FP) (Branch target of P3417) membar #StoreLoad ba P3413 nop TARGET3417: ba RET3417 nop P3413: !_BLD [11] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 fmovs %f19, %f8 fmovd %f40, %f18 fmovs %f18, %f9 P3414: !_MEMBAR (FP) (Branch target of P3344) ba P3415 nop TARGET3344: ba RET3344 nop P3415: !_BST [15] (maybe <- 0x428000f8) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 128 ] %asi P3416: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3416 nop RET3416: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3417: !_BSTC [33] (maybe <- 0x428000f9) (FP) (CBR) (Branch target of P2788) wr %g0, 0xe0, %asi sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3417 nop RET3417: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P3418 nop TARGET2788: ba RET2788 nop P3418: !_MEMBAR (FP) (Branch target of P3089) ba P3419 nop TARGET3089: ba RET3089 nop P3419: !_BSTC [9] (maybe <- 0x428000fa) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i1 + 0 ] %asi P3420: !_MEMBAR (FP) membar #StoreLoad P3421: !_LD [9] (FP) (Secondary ctx) wr %g0, 0x81, %asi lda [%i1 + 32] %asi, %f10 ! 1 addresses covered P3422: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3422 nop RET3422: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3423: !_BST [16] (maybe <- 0x428000fc) (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f36 membar #Sync stda %f32, [%i2 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3423 nop RET3423: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3424: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3424 nop RET3424: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3425: !_ST [0] (maybe <- 0x428000fd) (FP) (Nucleus ctx) wr %g0, 0x4, %asi ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i0 + 0 ] %asi P3426: !_REPLACEMENT [31] (Int) (CBR) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+192], %l3 st %l3, [%i3+192] add %i3, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] add %o5, %l7, %o5 ld [%o5+192], %l3 st %l3, [%o5+192] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3426 nop RET3426: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3427: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3427 nop RET3427: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3428: !_BSTC [21] (maybe <- 0x428000fe) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P3429: !_MEMBAR (FP) (Branch target of P3016) membar #StoreLoad ba P3430 nop TARGET3016: ba RET3016 nop P3430: !_BLD [10] (FP) wr %g0, 0xf0, %asi ldda [%i1 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 P3431: !_MEMBAR (FP) (Branch target of P2958) ba P3432 nop TARGET2958: ba RET2958 nop P3432: !_BLD [13] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f12 fmovd %f40, %f14 P3433: !_MEMBAR (FP) (CBR) (Branch target of P3437) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3433 nop RET3433: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P3434 nop TARGET3437: ba RET3437 nop P3434: !_ST [25] (maybe <- 0x42800101) (FP) (Nucleus ctx) wr %g0, 0x4, %asi ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i2 + 96 ] %asi P3435: !_LD [21] (Int) lduw [%i2 + 0], %o0 ! move %o0(lower) -> %o0(upper) sllx %o0, 32, %o0 P3436: !_MEMBAR (FP) P3437: !_BST [22] (maybe <- 0x42800102) (FP) (CBR) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3437 nop RET3437: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3438: !_MEMBAR (FP) (Branch target of P3161) membar #StoreLoad ba P3439 nop TARGET3161: ba RET3161 nop P3439: !_BLD [19] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- P3440: !_MEMBAR (FP) (Branch target of P3066) ba P3441 nop TARGET3066: ba RET3066 nop P3441: !_PREFETCH [23] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetcha [%i3 + 32] %asi, 1 P3442: !_PREFETCH [16] (Int) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 16], 1 P3443: !_MEMBAR (FP) P3444: !_BST [23] (maybe <- 0x42800105) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P3445: !_MEMBAR (FP) P3446: !_BST [1] (maybe <- 0x42800108) (FP) (CBR) (Branch target of P3212) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3446 nop RET3446: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P3447 nop TARGET3212: ba RET3212 nop P3447: !_MEMBAR (FP) (Branch target of P3243) membar #StoreLoad ba P3448 nop TARGET3243: ba RET3243 nop P3448: !_REPLACEMENT [11] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %o5 ld [%i3+0], %l6 st %l6, [%i3+0] add %i3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] P3449: !_LD [3] (FP) (Branch target of P3217) ld [%i0 + 16], %f0 ! 1 addresses covered ba P3450 nop TARGET3217: ba RET3217 nop P3450: !_ST [28] (maybe <- 0x3000013) (Int) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 stw %l4, [%i2 + 0 ] add %l4, 1, %l4 P3451: !_LD [8] (Int) (LE) wr %g0, 0x88, %asi lduwa [%i1 + 0] %asi, %l7 ! move %l7(lower) -> %o0(lower) or %l7, %o0, %o0 P3452: !_ST [6] (maybe <- 0x4280010d) (FP) (Secondary ctx) (Branch target of P3416) wr %g0, 0x81, %asi ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i0 + 96 ] %asi ba P3453 nop TARGET3416: ba RET3416 nop P3453: !_REPLACEMENT [6] (Int) (CBR) sethi %hi(0x2000), %l7 ld [%i3+96], %l3 st %l3, [%i3+96] add %i3, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3453 nop RET3453: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3454: !_REPLACEMENT [1] (Int) (Branch target of P3587) sethi %hi(0x2000), %l7 ld [%i3+4], %l3 st %l3, [%i3+4] add %i3, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] ba P3455 nop TARGET3587: ba RET3587 nop P3455: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3455 nop RET3455: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3456: !_BSTC [4] (maybe <- 0x4280010e) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P3457: !_MEMBAR (FP) membar #StoreLoad P3458: !_BLD [9] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 fmovd %f40, %f2 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3458 nop RET3458: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3459: !_MEMBAR (FP) (Branch target of P2647) ba P3460 nop TARGET2647: ba RET2647 nop P3460: !_ST [17] (maybe <- 0x3000014) (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stwa %l4, [%i3 + 96] %asi add %l4, 1, %l4 P3461: !_ST [32] (maybe <- 0x42800113) (FP) (CBR) (Secondary ctx) wr %g0, 0x81, %asi ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i2 + 256 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3461 nop RET3461: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P3462: !_REPLACEMENT [17] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l6 ld [%i2+96], %o5 st %o5, [%i2+96] add %i2, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] add %l7, %l6, %l7 ld [%l7+96], %o5 st %o5, [%l7+96] P3463: !_MEMBAR (FP) (Branch target of P2641) ba P3464 nop TARGET2641: ba RET2641 nop P3464: !_BSTC [13] (maybe <- 0x42800114) (FP) (CBR) wr %g0, 0xe0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3464 nop RET3464: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3465: !_MEMBAR (FP) P3466: !_BSTC [11] (maybe <- 0x42800117) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P3467: !_MEMBAR (FP) P3468: !_BSTC [12] (maybe <- 0x4280011a) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P3469: !_MEMBAR (FP) (Branch target of P2667) membar #StoreLoad ba P3470 nop TARGET2667: ba RET2667 nop P3470: !_LD [30] (Int) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduw [%i2 + 128], %o1 ! move %o1(lower) -> %o1(upper) sllx %o1, 32, %o1 P3471: !_LD [26] (Int) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lduw [%i3 + 128], %l6 ! move %l6(lower) -> %o1(lower) or %l6, %o1, %o1 P3472: !_MEMBAR (FP) membar #StoreLoad P3473: !_BLD [23] (FP) (Branch target of P2927) wr %g0, 0xf0, %asi ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 fmovs %f19, %f4 fmovd %f40, %f18 fmovs %f18, %f5 ba P3474 nop TARGET2927: ba RET2927 nop P3474: !_MEMBAR (FP) P3475: !_BSTC [11] (maybe <- 0x4280011d) (FP) (CBR) wr %g0, 0xe0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3475 nop RET3475: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3476: !_MEMBAR (FP) (Branch target of P2718) ba P3477 nop TARGET2718: ba RET2718 nop P3477: !_BST [7] (maybe <- 0x42800120) (FP) (CBR) (Secondary ctx) (Branch target of P2686) wr %g0, 0xf1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i0 + 128 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3477 nop RET3477: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P3478 nop TARGET2686: ba RET2686 nop P3478: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P3479: !_BLD [13] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f6 fmovd %f40, %f8 P3480: !_MEMBAR (FP) (Secondary ctx) P3481: !_REPLACEMENT [13] (Int) (CBR) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+32], %l3 st %l3, [%i3+32] add %i3, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3481 nop RET3481: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3482: !_MEMBAR (FP) P3483: !_BST [22] (maybe <- 0x42800121) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P3484: !_MEMBAR (FP) membar #StoreLoad P3485: !_REPLACEMENT [7] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(0x2000), %l6 ld [%i3+128], %o5 st %o5, [%i3+128] add %i3, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] add %l7, %l6, %l7 ld [%l7+128], %o5 st %o5, [%l7+128] P3486: !_ST [24] (maybe <- 0x42800124) (FP) (CBR) (Branch target of P3247) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 64 ] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3486 nop RET3486: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 ba P3487 nop TARGET3247: ba RET3247 nop P3487: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P3488: !_BLD [25] (FP) (CBR) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i2 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f9 fmovd %f40, %f10 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3488 nop RET3488: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P3489: !_MEMBAR (FP) (Secondary ctx) P3490: !_REPLACEMENT [8] (Int) (CBR) sethi %hi(0x2000), %l6 ld [%i3+0], %o5 st %o5, [%i3+0] add %i3, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3490 nop RET3490: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P3491: !_LD [3] (FP) (Secondary ctx) wr %g0, 0x81, %asi lda [%i0 + 16] %asi, %f11 ! 1 addresses covered P3492: !_REPLACEMENT [28] (Int) sethi %hi(0x2000), %l6 ld [%i3+0], %o5 st %o5, [%i3+0] add %i3, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] P3493: !_REPLACEMENT [10] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(0x2000), %l3 ld [%i3+64], %l7 st %l7, [%i3+64] add %i3, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] P3494: !_PREFETCH [10] (Int) (Nucleus ctx) wr %g0, 0x4, %asi prefetcha [%i1 + 64] %asi, 1 P3495: !_MEMBAR (FP) (Secondary ctx) P3496: !_BSTC [21] (maybe <- 0x42800125) (FP) (Secondary ctx) wr %g0, 0xe1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P3497: !_MEMBAR (FP) (Secondary ctx) P3498: !_BST [15] (maybe <- 0x42800128) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 128 ] %asi P3499: !_MEMBAR (FP) membar #StoreLoad P3500: !_BLD [19] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f12 P3501: !_MEMBAR (FP) P3502: !_ST [30] (maybe <- 0x42800129) (FP) (CBR) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 128 ] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3502 nop RET3502: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P3503: !_ST [2] (maybe <- 0x3000015) (Int) stw %l4, [%i0 + 8 ] add %l4, 1, %l4 P3504: !_MEMBAR (FP) P3505: !_BST [12] (maybe <- 0x4280012a) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P3506: !_MEMBAR (FP) membar #StoreLoad P3507: !_MEMBAR (Int) (Branch target of P2792) ba P3508 nop TARGET2792: ba RET2792 nop P3508: !_BST [10] (maybe <- 0x4280012d) (FP) (Branch target of P3173) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i1 + 64 ] %asi ba P3509 nop TARGET3173: ba RET3173 nop P3509: !_MEMBAR (FP) membar #StoreLoad P3510: !_ST [4] (maybe <- 0x3000016) (Int) (CBR) stw %l4, [%i0 + 32 ] add %l4, 1, %l4 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3510 nop RET3510: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3511: !_MEMBAR (FP) P3512: !_BST [22] (maybe <- 0x4280012e) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P3513: !_MEMBAR (FP) P3514: !_BST [15] (maybe <- 0x42800131) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 128 ] %asi P3515: !_MEMBAR (FP) P3516: !_BST [32] (maybe <- 0x42800132) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 256 ] %asi P3517: !_MEMBAR (FP) (Branch target of P2658) membar #StoreLoad ba P3518 nop TARGET2658: ba RET2658 nop P3518: !_BLD [10] (FP) wr %g0, 0xf0, %asi ldda [%i1 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 P3519: !_MEMBAR (FP) P3520: !_LD [20] (Int) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lduw [%i3 + 256], %o2 ! move %o2(lower) -> %o2(upper) sllx %o2, 32, %o2 P3521: !_REPLACEMENT [27] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l6 ld [%i2+160], %o5 st %o5, [%i2+160] add %i2, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] P3522: !_REPLACEMENT [33] (Int) (CBR) (Branch target of P2729) sethi %hi(0x2000), %l3 ld [%i2+0], %l7 st %l7, [%i2+0] add %i2, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3522 nop RET3522: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 ba P3523 nop TARGET2729: ba RET2729 nop P3523: !_REPLACEMENT [19] (Int) (CBR) sethi %hi(0x2000), %l3 ld [%i2+0], %l7 st %l7, [%i2+0] add %i2, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3523 nop RET3523: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3524: !_MEMBAR (FP) P3525: !_BST [17] (maybe <- 0x42800133) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f40 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 64 ] %asi P3526: !_MEMBAR (FP) P3527: !_BSTC [25] (maybe <- 0x42800134) (FP) (Secondary ctx) wr %g0, 0xe1, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 64 ] %asi P3528: !_MEMBAR (FP) (Secondary ctx) (Branch target of P2776) membar #StoreLoad ba P3529 nop TARGET2776: ba RET2776 nop P3529: !_REPLACEMENT [25] (Int) (CBR) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+96], %l3 st %l3, [%i3+96] add %i3, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3529 nop RET3529: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3530: !_PREFETCH [6] (Int) (Secondary ctx) wr %g0, 0x81, %asi prefetcha [%i0 + 96] %asi, 1 P3531: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P3532: !_BLD [1] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f14 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f34, %f0 fmovd %f36, %f18 fmovs %f18, %f1 fmovd %f40, %f2 P3533: !_MEMBAR (FP) (CBR) (Secondary ctx) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3533 nop RET3533: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3534: !_ST [22] (maybe <- 0x3000017) (Int) stw %l4, [%i2 + 4 ] add %l4, 1, %l4 P3535: !_MEMBAR (FP) P3536: !_BST [28] (maybe <- 0x42800136) (FP) (CBR) (Branch target of P3310) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3536 nop RET3536: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P3537 nop TARGET3310: ba RET3310 nop P3537: !_MEMBAR (FP) membar #StoreLoad P3538: !_LD [28] (Int) lduw [%i2 + 0], %o5 ! move %o5(lower) -> %o2(lower) or %o5, %o2, %o2 P3539: !_MEMBAR (FP) P3540: !_BST [12] (maybe <- 0x42800137) (FP) (Branch target of P3486) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi ba P3541 nop TARGET3486: ba RET3486 nop P3541: !_MEMBAR (FP) (Branch target of P2870) membar #StoreLoad ba P3542 nop TARGET2870: ba RET2870 nop P3542: !_BLD [25] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 fmovd %f40, %f4 P3543: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3543 nop RET3543: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3544: !_LD [19] (FP) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ld [%i3 + 0], %f5 ! 1 addresses covered P3545: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3545 nop RET3545: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P3546: !_BST [7] (maybe <- 0x4280013a) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i0 + 128 ] %asi P3547: !_MEMBAR (FP) (CBR) (Branch target of P3633) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3547 nop RET3547: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P3548 nop TARGET3633: ba RET3633 nop P3548: !_BSTC [22] (maybe <- 0x4280013b) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P3549: !_MEMBAR (FP) membar #StoreLoad P3550: !_LD [31] (Int) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduw [%i2 + 192], %o3 ! move %o3(lower) -> %o3(upper) sllx %o3, 32, %o3 P3551: !_MEMBAR (FP) membar #StoreLoad P3552: !_BLD [16] (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f36, %f6 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3552 nop RET3552: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3553: !_MEMBAR (FP) P3554: !_BSTC [32] (maybe <- 0x4280013e) (FP) (Branch target of P3080) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 256 ] %asi ba P3555 nop TARGET3080: ba RET3080 nop P3555: !_MEMBAR (FP) (Branch target of P3622) membar #StoreLoad ba P3556 nop TARGET3622: ba RET3622 nop P3556: !_BLD [28] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 P3557: !_MEMBAR (FP) (Branch target of P2784) ba P3558 nop TARGET2784: ba RET2784 nop P3558: !_BST [23] (maybe <- 0x4280013f) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi P3559: !_MEMBAR (FP) membar #StoreLoad P3560: !_BLD [25] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i2 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f8 fmovd %f40, %f18 fmovs %f18, %f9 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3560 nop RET3560: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3561: !_MEMBAR (FP) P3562: !_LD [16] (Int) lduw [%i3 + 16], %o5 ! move %o5(lower) -> %o3(lower) or %o5, %o3, %o3 P3563: !_PREFETCH [26] (Int) (Nucleus ctx) (Branch target of P2745) wr %g0, 0x4, %asi prefetcha [%i2 + 128] %asi, 1 ba P3564 nop TARGET2745: ba RET2745 nop P3564: !_LD [14] (FP) (CBR) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ld [%i3 + 64], %f10 ! 1 addresses covered ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3564 nop RET3564: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P3565: !_ST [9] (maybe <- 0x42800142) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i1 + 32 ] P3566: !_REPLACEMENT [3] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+16], %l7 st %l7, [%i2+16] add %i2, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] P3567: !_PREFETCH [4] (Int) prefetch [%i0 + 32], 1 P3568: !_MEMBAR (FP) P3569: !_BSTC [15] (maybe <- 0x42800143) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 128 ] %asi P3570: !_MEMBAR (FP) membar #StoreLoad P3571: !_REPLACEMENT [19] (Int) sethi %hi(0x2000), %l7 ld [%i2+0], %l3 st %l3, [%i2+0] add %i2, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] P3572: !_LD [8] (Int) (LE) wr %g0, 0x88, %asi lduwa [%i1 + 0] %asi, %o4 ! move %o4(lower) -> %o4(upper) sllx %o4, 32, %o4 P3573: !_REPLACEMENT [21] (Int) sethi %hi(0x2000), %o5 ld [%i2+0], %l6 st %l6, [%i2+0] add %i2, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] P3574: !_MEMBAR (FP) membar #StoreLoad P3575: !_BLD [28] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 P3576: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3576 nop RET3576: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3577: !_BLD [27] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 128] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f12 fmovd %f40, %f18 fmovs %f18, %f13 P3578: !_MEMBAR (FP) P3579: !_FLUSHI [11] (Int) flush %g0 P3580: !_MEMBAR (FP) P3581: !_BST [22] (maybe <- 0x42800144) (FP) (CBR) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3581 nop RET3581: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3582: !_MEMBAR (FP) membar #StoreLoad P3583: !_BLD [30] (FP) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i3 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f14 P3584: !_MEMBAR (FP) (Secondary ctx) P3585: !_BLD [31] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 192] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- P3586: !_MEMBAR (FP) P3587: !_BST [16] (maybe <- 0x42800147) (FP) (CBR) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f36 membar #Sync stda %f32, [%i3 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3587 nop RET3587: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3588: !_MEMBAR (FP) membar #StoreLoad P3589: !_LD [5] (Int) (CBR) lduw [%i0 + 64], %l3 ! move %l3(lower) -> %o4(lower) or %l3, %o4, %o4 !---- flushing int results buffer---- mov %o0, %l5 mov %o1, %l5 mov %o2, %l5 mov %o3, %l5 mov %o4, %l5 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3589 nop RET3589: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3590: !_PREFETCH [23] (Int) (Secondary ctx) wr %g0, 0x81, %asi prefetcha [%i2 + 32] %asi, 1 P3591: !_REPLACEMENT [0] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l7 ld [%i2+0], %l3 st %l3, [%i2+0] add %i2, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] P3592: !_LD [18] (Int) lduw [%i3 + 128], %o0 ! move %o0(lower) -> %o0(upper) sllx %o0, 32, %o0 P3593: !_ST [0] (maybe <- 0x3000018) (Int) stw %l4, [%i0 + 0 ] add %l4, 1, %l4 P3594: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P3595: !_BLD [23] (FP) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f0 membar #Sync ! 3 addresses covered fmovd %f8, %f2 P3596: !_MEMBAR (FP) (CBR) (Secondary ctx) (Branch target of P3085) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3596 nop RET3596: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P3597 nop TARGET3085: ba RET3085 nop P3597: !_BST [4] (maybe <- 0x42800148) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P3598: !_MEMBAR (FP) membar #StoreLoad P3599: !_ST [28] (maybe <- 0x4280014d) (FP) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i2 + 0 ] %asi P3600: !_MEMBAR (FP) membar #StoreLoad P3601: !_BLD [23] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 fmovs %f19, %f4 fmovd %f40, %f18 fmovs %f18, %f5 P3602: !_MEMBAR (FP) P3603: !_BST [26] (maybe <- 0x4280014e) (FP) (CBR) (Secondary ctx) wr %g0, 0xf1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 128 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3603 nop RET3603: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P3604: !_MEMBAR (FP) (CBR) (Secondary ctx) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3604 nop RET3604: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3605: !_PREFETCH [24] (Int) prefetch [%i3 + 64], 1 P3606: !_LD [6] (Int) lduw [%i0 + 96], %o5 ! move %o5(lower) -> %o0(lower) or %o5, %o0, %o0 P3607: !_ST [27] (maybe <- 0x3000019) (Int) stw %l4, [%i3 + 160 ] add %l4, 1, %l4 P3608: !_MEMBAR (FP) P3609: !_BSTC [23] (maybe <- 0x42800150) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P3610: !_MEMBAR (FP) membar #StoreLoad P3611: !_ST [19] (maybe <- 0x42800153) (FP) (Branch target of P3216) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i3 + 0 ] ba P3612 nop TARGET3216: ba RET3216 nop P3612: !_MEMBAR (FP) membar #StoreLoad P3613: !_BLD [9] (FP) wr %g0, 0xf0, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f6 fmovd %f40, %f18 fmovs %f18, %f7 P3614: !_MEMBAR (FP) P3615: !_ST [27] (maybe <- 0x42800154) (FP) (Secondary ctx) (Branch target of P3604) wr %g0, 0x81, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i2 + 160 ] %asi ba P3616 nop TARGET3604: ba RET3604 nop P3616: !_REPLACEMENT [5] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+64], %l7 st %l7, [%i3+64] add %i3, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] add %l6, %l3, %l6 ld [%l6+64], %l7 st %l7, [%l6+64] P3617: !_REPLACEMENT [1] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(0x2000), %o5 ld [%i3+4], %l6 st %l6, [%i3+4] add %i3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] P3618: !_ST [28] (maybe <- 0x300001a) (Int) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 stw %l4, [%i2 + 0 ] add %l4, 1, %l4 P3619: !_ST [4] (maybe <- 0x42800155) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i0 + 32 ] P3620: !_ST [26] (maybe <- 0x300001b) (Int) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stw %l4, [%i3 + 128 ] add %l4, 1, %l4 P3621: !_MEMBAR (FP) (Secondary ctx) P3622: !_BSTC [2] (maybe <- 0x42800156) (FP) (CBR) (Secondary ctx) (Branch target of P2813) wr %g0, 0xe1, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3622 nop RET3622: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P3623 nop TARGET2813: ba RET2813 nop P3623: !_MEMBAR (FP) (Secondary ctx) membar #StoreLoad P3624: !_REPLACEMENT [1] (Int) (Secondary ctx) (Branch target of P3581) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %o5 ld [%i2+4], %l6 st %l6, [%i2+4] add %i2, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] ba P3625 nop TARGET3581: ba RET3581 nop P3625: !_REPLACEMENT [17] (Int) sethi %hi(0x2000), %l7 ld [%i2+96], %l3 st %l3, [%i2+96] add %i2, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] add %o5, %l7, %o5 ld [%o5+96], %l3 st %l3, [%o5+96] P3626: !_MEMBAR (FP) (CBR) (Secondary ctx) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3626 nop RET3626: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3627: !_BLD [16] (FP) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f36, %f8 P3628: !_MEMBAR (FP) (Secondary ctx) P3629: !_BLD [7] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f9 P3630: !_MEMBAR (FP) P3631: !_BST [1] (maybe <- 0x4280015b) (FP) (CBR) (Branch target of P3198) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3631 nop RET3631: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P3632 nop TARGET3198: ba RET3198 nop P3632: !_MEMBAR (FP) membar #StoreLoad P3633: !_REPLACEMENT [8] (Int) (CBR) sethi %hi(0x2000), %l7 ld [%i2+0], %l3 st %l3, [%i2+0] add %i2, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] add %o5, %l7, %o5 ld [%o5+0], %l3 st %l3, [%o5+0] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3633 nop RET3633: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3634: !_REPLACEMENT [15] (Int) (CBR) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(0x2000), %l7 ld [%i2+128], %l3 st %l3, [%i2+128] add %i2, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3634 nop RET3634: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3635: !_REPLACEMENT [12] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(0x2000), %l7 ld [%i2+4], %l3 st %l3, [%i2+4] add %i2, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] P3636: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3636 nop RET3636: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3637: !_BLD [9] (FP) wr %g0, 0xf0, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f10 fmovd %f40, %f18 fmovs %f18, %f11 P3638: !_MEMBAR (FP) (Loop exit) (Branch target of P2765) !---- flushing int results buffer---- mov %o0, %l5 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 !-- loop_exit_6_3: sub %l2, 1, %l2 cmp %l2, 0 bg loop_entry_6_3 nop ba P3639 nop TARGET2765: ba RET2765 nop P3639: !_MEMBAR (Int) membar #StoreLoad END_NODES6: ! Test instruction sequence for CPU 6 ends sethi %hi(0xdead0e0f), %o5 or %o5, %lo(0xdead0e0f), %o5 ! move %o5(lower) -> %o0(upper) sllx %o5, 32, %o0 sethi %hi(0xdead0e0f), %o5 or %o5, %lo(0xdead0e0f), %o5 stw %o5, [%i5] ld [%i5], %f0 !---- flushing int results buffer---- mov %o0, %l5 !---- flushing fp results buffer to %f30 ---- fmovs %f0, %f30 !-- restore retl nop !----------------- ! register usage: ! %i0 %i1 : base registers for first 2 regions ! %i2 %i3 : cache registers for 8 regions ! %i4 fixed pointer to per-cpu results area ! %l1 moving pointer to per-cpu FP results area ! %o7 moving pointer to per-cpu integer results area ! %i5 pointer to per-cpu private area ! %l0 holds lfsr, used as source of random bits ! %l2 loop count register ! %f16 running counter for unique fp store values ! %f17 holds increment value for fp counter ! %l4 running counter for unique integer store values (increment value is always 1) ! %l5 move-to register for load values (simulation only) ! %f30 move-to register for FP values (simulation only) ! %i4 holds the instructions count which is used for interrupt ordering ! %i4 holds the thread_id (OBP only) ! %l5 holds the moving pointer for interrupt bonus data (OBP only). Conflicts with RTL/simulation usage ! %l3 %l6 %l7 %o5 : 4 temporary registers ! %o0 %o1 %o2 %o3 %o4 : 5 integer results buffer registers ! %f0-f15 FP results buffer registers ! %f32-f47 FP block load/store registers func7: ! instruction sequence begins save %sp, -192, %sp ! Force %i0-%i3 to be 64-byte aligned add %i0, 63, %i0 andn %i0, 63, %i0 add %i1, 63, %i1 andn %i1, 63, %i1 add %i2, 63, %i2 andn %i2, 63, %i2 add %i3, 63, %i3 andn %i3, 63, %i3 add %i4, 63, %i4 andn %i4, 63, %i4 add %i5, 63, %i5 andn %i5, 63, %i5 ! Initialize pointer to FP load results area mov %i4, %l1 ! Initialize pointer to integer load results area sethi %hi(0x80000), %o7 or %o7, %lo(0x80000), %o7 add %o7, %l1, %o7 ! Reinitialize i4 to 0. i4 will be used to keep the count of analyzable node info mov 0x0, %i4 ! Initialize %f0-%f62 to 0xdeadbee0deadbee1 sethi %hi(0xdeadbee0), %l7 or %l7, %lo(0xdeadbee0), %l7 stw %l7, [%i5] sethi %hi(0xdeadbee1), %l7 or %l7, %lo(0xdeadbee1), %l7 stw %l7, [%i5+4] ldd [%i5], %f0 fmovd %f0, %f2 fmovd %f0, %f4 fmovd %f0, %f6 fmovd %f0, %f8 fmovd %f0, %f10 fmovd %f0, %f12 fmovd %f0, %f14 fmovd %f0, %f16 fmovd %f0, %f18 fmovd %f0, %f20 fmovd %f0, %f22 fmovd %f0, %f24 fmovd %f0, %f26 fmovd %f0, %f28 fmovd %f0, %f30 fmovd %f0, %f32 fmovd %f0, %f34 fmovd %f0, %f36 fmovd %f0, %f38 fmovd %f0, %f40 fmovd %f0, %f42 fmovd %f0, %f44 fmovd %f0, %f46 fmovd %f0, %f48 fmovd %f0, %f50 fmovd %f0, %f52 fmovd %f0, %f54 fmovd %f0, %f56 fmovd %f0, %f58 fmovd %f0, %f60 fmovd %f0, %f62 ! Signature for extract_loads script to start extracting load values for this stream sethi %hi(0x07deade1), %l7 or %l7, %lo(0x07deade1), %l7 stw %l7, [%i5] ld [%i5], %f16 ! Initialize running integer counter in register %l4 sethi %hi(0x3800001), %l4 or %l4, %lo(0x3800001), %l4 ! Initialize running FP counter in register %f16 sethi %hi(0x43000001), %l7 or %l7, %lo(0x43000001), %l7 stw %l7, [%i5] ld [%i5], %f16 ! Initialize FP counter increment value in register %f17 (constant) sethi %hi(0x37800000), %l7 or %l7, %lo(0x37800000), %l7 stw %l7, [%i5] ld [%i5], %f17 ! Initialize LFSR to 0x3c21^4 sethi %hi(0x3c21), %l0 or %l0, %lo(0x3c21), %l0 mulx %l0, %l0, %l0 mulx %l0, %l0, %l0 BEGIN_NODES7: ! Test instruction sequence for ISTREAM 7 begins P3640: !_REPLACEMENT [27] (Int) (Loop entry) sethi %hi(0x5), %l2 or %l2, %lo(0x5), %l2 loop_entry_7_0: sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %o5 ld [%i2+160], %l6 st %l6, [%i2+160] add %i2, %o5, %l3 ld [%l3+160], %l6 st %l6, [%l3+160] add %l3, %o5, %l3 ld [%l3+160], %l6 st %l6, [%l3+160] add %l3, %o5, %l3 ld [%l3+160], %l6 st %l6, [%l3+160] add %l3, %o5, %l3 ld [%l3+160], %l6 st %l6, [%l3+160] add %l3, %o5, %l3 ld [%l3+160], %l6 st %l6, [%l3+160] add %l3, %o5, %l3 ld [%l3+160], %l6 st %l6, [%l3+160] add %l3, %o5, %l3 ld [%l3+160], %l6 st %l6, [%l3+160] P3641: !_LD [16] (FP) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ld [%i3 + 16], %f0 ! 1 addresses covered P3642: !_ST [9] (maybe <- 0x43000001) (FP) (CBR) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i1 + 32 ] ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3642 nop RET3642: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3643: !_ST [25] (maybe <- 0x43000002) (FP) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 sta %f20, [%i2 + 96 ] %asi P3644: !_PREFETCH [22] (Int) prefetch [%i2 + 4], 1 P3645: !_LD [24] (Int) lduw [%i2 + 64], %o0 ! move %o0(lower) -> %o0(upper) sllx %o0, 32, %o0 P3646: !_PREFETCH [2] (Int) (LE) (CBR) (Secondary ctx) wr %g0, 0x89, %asi prefetcha [%i0 + 8] %asi, 1 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3646 nop RET3646: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3647: !_MEMBAR (FP) membar #StoreLoad P3648: !_BLD [30] (FP) (Branch target of P3794) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 ba P3649 nop TARGET3794: ba RET3794 nop P3649: !_MEMBAR (FP) (Branch target of P3707) ba P3650 nop TARGET3707: ba RET3707 nop P3650: !_PREFETCH [12] (Int) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 4], 1 P3651: !_MEMBAR (FP) P3652: !_BST [31] (maybe <- 0x43000003) (FP) (Branch target of P3660) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 192 ] %asi ba P3653 nop TARGET3660: ba RET3660 nop P3653: !_MEMBAR (FP) (Branch target of P3776) membar #StoreLoad ba P3654 nop TARGET3776: ba RET3776 nop P3654: !_REPLACEMENT [4] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %o5 ld [%i3+32], %l6 st %l6, [%i3+32] add %i3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] P3655: !_MEMBAR (FP) membar #StoreLoad P3656: !_BLD [2] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f2 fmovd %f34, %f4 fmovd %f36, %f18 fmovs %f18, %f5 fmovd %f40, %f6 P3657: !_MEMBAR (FP) (Branch target of P3676) ba P3658 nop TARGET3676: ba RET3676 nop P3658: !_BST [4] (maybe <- 0x43000004) (FP) (Branch target of P3710) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi ba P3659 nop TARGET3710: ba RET3710 nop P3659: !_MEMBAR (FP) P3660: !_BST [7] (maybe <- 0x43000009) (FP) (CBR) (Branch target of P3787) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i0 + 128 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3660 nop RET3660: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 ba P3661 nop TARGET3787: ba RET3787 nop P3661: !_MEMBAR (FP) membar #StoreLoad P3662: !_PREFETCH [22] (Int) (Branch target of P3739) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 4], 1 ba P3663 nop TARGET3739: ba RET3739 nop P3663: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3663 nop RET3663: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3664: !_BLD [15] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 P3665: !_MEMBAR (FP) P3666: !_BSTC [30] (maybe <- 0x4300000a) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 128 ] %asi P3667: !_MEMBAR (FP) membar #StoreLoad P3668: !_BLD [31] (FP) (Branch target of P3646) wr %g0, 0xf0, %asi ldda [%i2 + 192] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f8 ba P3669 nop TARGET3646: ba RET3646 nop P3669: !_MEMBAR (FP) P3670: !_ST [4] (maybe <- 0x3800001) (Int) (Branch target of P3681) stw %l4, [%i0 + 32 ] add %l4, 1, %l4 ba P3671 nop TARGET3681: ba RET3681 nop P3671: !_LD [9] (FP) (CBR) (Secondary ctx) wr %g0, 0x81, %asi lda [%i1 + 32] %asi, %f9 ! 1 addresses covered ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3671 nop RET3671: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P3672: !_ST [10] (maybe <- 0x3800002) (Int) stw %l4, [%i1 + 64 ] add %l4, 1, %l4 P3673: !_REPLACEMENT [31] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+192], %l7 st %l7, [%i3+192] add %i3, %l3, %l6 ld [%l6+192], %l7 st %l7, [%l6+192] add %l6, %l3, %l6 ld [%l6+192], %l7 st %l7, [%l6+192] add %l6, %l3, %l6 ld [%l6+192], %l7 st %l7, [%l6+192] add %l6, %l3, %l6 ld [%l6+192], %l7 st %l7, [%l6+192] add %l6, %l3, %l6 ld [%l6+192], %l7 st %l7, [%l6+192] add %l6, %l3, %l6 ld [%l6+192], %l7 st %l7, [%l6+192] add %l6, %l3, %l6 ld [%l6+192], %l7 st %l7, [%l6+192] P3674: !_REPLACEMENT [28] (Int) sethi %hi(0x2000), %o5 ld [%i3+0], %l6 st %l6, [%i3+0] add %i3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] P3675: !_MEMBAR (FP) membar #StoreLoad P3676: !_BLD [18] (FP) (CBR) (Branch target of P3671) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f10 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3676 nop RET3676: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 ba P3677 nop TARGET3671: ba RET3671 nop P3677: !_MEMBAR (FP) P3678: !_LD [25] (FP) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lda [%i3 + 96] %asi, %f11 ! 1 addresses covered P3679: !_REPLACEMENT [14] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %o5 ld [%i2+64], %l6 st %l6, [%i2+64] add %i2, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] P3680: !_MEMBAR (FP) membar #StoreLoad P3681: !_BLD [3] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f12 fmovd %f34, %f14 fmovd %f36, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f40, %f0 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3681 nop RET3681: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3682: !_MEMBAR (FP) (Branch target of P3722) ba P3683 nop TARGET3722: ba RET3722 nop P3683: !_REPLACEMENT [4] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(0x2000), %o5 ld [%i2+32], %l6 st %l6, [%i2+32] add %i2, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] add %l3, %o5, %l3 ld [%l3+32], %l6 st %l6, [%l3+32] P3684: !_LD [16] (Int) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lduw [%i3 + 16], %o5 ! move %o5(lower) -> %o0(lower) or %o5, %o0, %o0 P3685: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3685 nop RET3685: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P3686: !_BLD [2] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 fmovs %f19, %f2 fmovd %f34, %f18 fmovs %f18, %f3 fmovd %f36, %f4 fmovd %f40, %f18 fmovs %f18, %f5 P3687: !_MEMBAR (FP) P3688: !_BLD [20] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f6 P3689: !_MEMBAR (FP) P3690: !_BSTC [26] (maybe <- 0x4300000b) (FP) (Secondary ctx) wr %g0, 0xe1, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 128 ] %asi P3691: !_MEMBAR (FP) (Secondary ctx) P3692: !_BST [25] (maybe <- 0x4300000d) (FP) (Branch target of P3696) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 64 ] %asi ba P3693 nop TARGET3696: ba RET3696 nop P3693: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3693 nop RET3693: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3694: !_BLD [28] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 P3695: !_MEMBAR (FP) P3696: !_BLD [4] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f8 fmovd %f34, %f10 fmovd %f36, %f18 fmovs %f18, %f11 fmovd %f40, %f12 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3696 nop RET3696: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P3697: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3697 nop RET3697: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3698: !_PREFETCH [9] (Int) (Branch target of P3757) prefetch [%i1 + 32], 1 ba P3699 nop TARGET3757: ba RET3757 nop P3699: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3699 nop RET3699: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3700: !_BLD [14] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 P3701: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3701 nop RET3701: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3702: !_BST [30] (maybe <- 0x4300000f) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 128 ] %asi P3703: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3703 nop RET3703: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3704: !_BLD [18] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f14 P3705: !_MEMBAR (FP) P3706: !_ST [24] (maybe <- 0x3800003) (Int) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stw %l4, [%i3 + 64 ] add %l4, 1, %l4 P3707: !_PREFETCH [28] (Int) (CBR) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 prefetch [%i2 + 0], 1 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3707 nop RET3707: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3708: !_MEMBAR (FP) membar #StoreLoad P3709: !_BLD [16] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f36, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- P3710: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3710 nop RET3710: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P3711: !_BST [30] (maybe <- 0x43000010) (FP) (Branch target of P3765) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 128 ] %asi ba P3712 nop TARGET3765: ba RET3765 nop P3712: !_MEMBAR (FP) membar #StoreLoad P3713: !_BLD [0] (FP) (Branch target of P3761) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f0 membar #Sync ! 5 addresses covered fmovs %f4, %f3 fmovd %f8, %f4 ba P3714 nop TARGET3761: ba RET3761 nop P3714: !_MEMBAR (FP) P3715: !_REPLACEMENT [33] (Int) (CBR) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+0], %l7 st %l7, [%i2+0] add %i2, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] add %l6, %l3, %l6 ld [%l6+0], %l7 st %l7, [%l6+0] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3715 nop RET3715: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3716: !_MEMBAR (FP) (Branch target of P3801) membar #StoreLoad ba P3717 nop TARGET3801: ba RET3801 nop P3717: !_BLD [31] (FP) (Branch target of P3760) wr %g0, 0xf0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 192] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 ba P3718 nop TARGET3760: ba RET3760 nop P3718: !_MEMBAR (FP) P3719: !_PREFETCH [6] (Int) (CBR) prefetch [%i0 + 96], 1 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3719 nop RET3719: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P3720: !_MEMBAR (FP) membar #StoreLoad P3721: !_BLD [4] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f6 fmovd %f34, %f8 fmovd %f36, %f18 fmovs %f18, %f9 fmovd %f40, %f10 P3722: !_MEMBAR (FP) (CBR) (Branch target of P3835) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3722 nop RET3722: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P3723 nop TARGET3835: ba RET3835 nop P3723: !_BLD [8] (FP) wr %g0, 0xf0, %asi ldda [%i1 + 0] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f11 fmovd %f40, %f12 P3724: !_MEMBAR (FP) (Branch target of P3744) ba P3725 nop TARGET3744: ba RET3744 nop P3725: !_BLD [32] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 256] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 P3726: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3726 nop RET3726: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3727: !_BSTC [7] (maybe <- 0x43000011) (FP) (Branch target of P3697) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i0 + 128 ] %asi ba P3728 nop TARGET3697: ba RET3697 nop P3728: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3728 nop RET3728: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3729: !_BLD [28] (FP) wr %g0, 0xf0, %asi ldda [%i3 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f14 P3730: !_MEMBAR (FP) P3731: !_BSTC [3] (maybe <- 0x43000012) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P3732: !_MEMBAR (FP) (Branch target of P3771) membar #StoreLoad ba P3733 nop TARGET3771: ba RET3771 nop P3733: !_BLD [6] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- fmovd %f40, %f0 P3734: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3734 nop RET3734: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3735: !_REPLACEMENT [29] (Int) sethi %hi(0x2000), %o5 ld [%i2+64], %l6 st %l6, [%i2+64] add %i2, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] add %l3, %o5, %l3 ld [%l3+64], %l6 st %l6, [%l3+64] P3736: !_REPLACEMENT [30] (Int) sethi %hi(0x2000), %l7 ld [%i2+128], %l3 st %l3, [%i2+128] add %i2, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] add %o5, %l7, %o5 ld [%o5+128], %l3 st %l3, [%o5+128] P3737: !_MEMBAR (FP) (Branch target of P3841) membar #StoreLoad ba P3738 nop TARGET3841: ba RET3841 nop P3738: !_BLD [19] (FP) (Branch target of P3752) wr %g0, 0xf0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f1 ba P3739 nop TARGET3752: ba RET3752 nop P3739: !_MEMBAR (FP) (CBR) (Branch target of P3726) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3739 nop RET3739: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P3740 nop TARGET3726: ba RET3726 nop P3740: !_LD [26] (FP) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lda [%i3 + 128] %asi, %f2 ! 1 addresses covered P3741: !_ST [19] (maybe <- 0x43000017) (FP) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 0 ] P3742: !_MEMBAR (FP) (CBR) (Secondary ctx) (Branch target of P3743) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3742 nop RET3742: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P3743 nop TARGET3743: ba RET3743 nop P3743: !_BLD [24] (FP) (CBR) (Secondary ctx) wr %g0, 0xf1, %asi ldda [%i3 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f18 fmovs %f18, %f3 fmovd %f40, %f4 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3743 nop RET3743: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3744: !_MEMBAR (FP) (CBR) (Secondary ctx) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3744 nop RET3744: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3745: !_ST [5] (maybe <- 0x43000018) (FP) (Branch target of P3719) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i0 + 64 ] ba P3746 nop TARGET3719: ba RET3719 nop P3746: !_MEMBAR (FP) (Branch target of P3813) membar #StoreLoad ba P3747 nop TARGET3813: ba RET3813 nop P3747: !_BLD [3] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f18 fmovs %f18, %f5 fmovs %f19, %f6 fmovd %f34, %f18 fmovs %f18, %f7 fmovd %f36, %f8 fmovd %f40, %f18 fmovs %f18, %f9 P3748: !_MEMBAR (FP) P3749: !_ST [21] (maybe <- 0x3800004) (Int) stw %l4, [%i3 + 0 ] add %l4, 1, %l4 P3750: !_MEMBAR (FP) membar #StoreLoad P3751: !_BLD [0] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f10 fmovd %f34, %f12 fmovd %f36, %f18 fmovs %f18, %f13 fmovd %f40, %f14 P3752: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3752 nop RET3752: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3753: !_BSTC [18] (maybe <- 0x43000019) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 128 ] %asi P3754: !_MEMBAR (FP) membar #StoreLoad P3755: !_BLD [15] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- P3756: !_MEMBAR (FP) P3757: !_BST [17] (maybe <- 0x4300001a) (FP) (CBR) (Branch target of P3642) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f40 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 64 ] %asi ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3757 nop RET3757: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 ba P3758 nop TARGET3642: ba RET3642 nop P3758: !_MEMBAR (FP) membar #StoreLoad P3759: !_PREFETCH [14] (Int) (Branch target of P3685) prefetch [%i3 + 64], 1 ba P3760 nop TARGET3685: ba RET3685 nop P3760: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3760 nop RET3760: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3761: !_BST [4] (maybe <- 0x4300001b) (FP) (CBR) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3761 nop RET3761: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3762: !_MEMBAR (FP) membar #StoreLoad P3763: !_REPLACEMENT [22] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %o5 ld [%i2+4], %l6 st %l6, [%i2+4] add %i2, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] add %l3, %o5, %l3 ld [%l3+4], %l6 st %l6, [%l3+4] P3764: !_MEMBAR (FP) membar #StoreLoad P3765: !_BLD [3] (FP) (CBR) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f0 membar #Sync ! 5 addresses covered fmovs %f4, %f3 fmovd %f8, %f4 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3765 nop RET3765: ! lfsr step begin srlx %l0, 1, %l7 xnor %l7, %l0, %l7 sllx %l7, 63, %l7 or %l7, %l0, %l0 srlx %l0, 1, %l0 P3766: !_MEMBAR (FP) P3767: !_ST [11] (maybe <- 0x3800005) (Int) (Secondary ctx) wr %g0, 0x81, %asi stwa %l4, [%i3 + 0] %asi add %l4, 1, %l4 P3768: !_MEMBAR (FP) P3769: !_BSTC [20] (maybe <- 0x43000020) (FP) (Branch target of P3693) wr %g0, 0xe0, %asi sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 256 ] %asi ba P3770 nop TARGET3693: ba RET3693 nop P3770: !_MEMBAR (FP) membar #StoreLoad P3771: !_BLD [17] (FP) (CBR) (Secondary ctx) wr %g0, 0xf1, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 64] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f40, %f18 fmovs %f18, %f5 ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3771 nop RET3771: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3772: !_MEMBAR (FP) (Secondary ctx) (Branch target of P3831) ba P3773 nop TARGET3831: ba RET3831 nop P3773: !_REPLACEMENT [22] (Int) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+4], %l3 st %l3, [%i3+4] add %i3, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] add %o5, %l7, %o5 ld [%o5+4], %l3 st %l3, [%o5+4] P3774: !_REPLACEMENT [27] (Int) sethi %hi(0x2000), %l6 ld [%i3+160], %o5 st %o5, [%i3+160] add %i3, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] add %l7, %l6, %l7 ld [%l7+160], %o5 st %o5, [%l7+160] P3775: !_ST [28] (maybe <- 0x43000021) (FP) sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 0 ] P3776: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3776 nop RET3776: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3777: !_BLD [5] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f32 membar #Sync ! 2 addresses covered fmovd %f32, %f6 fmovd %f40, %f18 fmovs %f18, %f7 P3778: !_MEMBAR (FP) P3779: !_BST [29] (maybe <- 0x43000022) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 64 ] %asi P3780: !_MEMBAR (FP) P3781: !_BST [9] (maybe <- 0x43000023) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i1 + 0 ] %asi P3782: !_MEMBAR (FP) membar #StoreLoad P3783: !_LD [32] (FP) ld [%i2 + 256], %f8 ! 1 addresses covered P3784: !_LD [16] (FP) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ld [%i3 + 16], %f9 ! 1 addresses covered P3785: !_MEMBAR (FP) (Secondary ctx) P3786: !_BSTC [24] (maybe <- 0x43000025) (FP) (Secondary ctx) wr %g0, 0xe1, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i2 + 64 ] %asi P3787: !_MEMBAR (FP) (CBR) (Secondary ctx) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3787 nop RET3787: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3788: !_BST [16] (maybe <- 0x43000027) (FP) (Branch target of P3703) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f36 membar #Sync stda %f32, [%i3 + 0 ] %asi ba P3789 nop TARGET3703: ba RET3703 nop P3789: !_MEMBAR (FP) membar #StoreLoad P3790: !_ST [12] (maybe <- 0x3800006) (Int) (CBR) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 stwa %l4, [%i3 + 4] %asi add %l4, 1, %l4 ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3790 nop RET3790: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P3791: !_ST [19] (maybe <- 0x43000028) (FP) (Branch target of P3663) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i2 + 0 ] ba P3792 nop TARGET3663: ba RET3663 nop P3792: !_REPLACEMENT [27] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l3 ld [%i3+160], %l7 st %l7, [%i3+160] add %i3, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] add %l6, %l3, %l6 ld [%l6+160], %l7 st %l7, [%l6+160] P3793: !_LD [28] (FP) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lda [%i2 + 0] %asi, %f10 ! 1 addresses covered P3794: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3794 nop RET3794: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3795: !_BSTC [7] (maybe <- 0x43000029) (FP) (Branch target of P3699) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i0 + 128 ] %asi ba P3796 nop TARGET3699: ba RET3699 nop P3796: !_MEMBAR (FP) (Branch target of P3734) membar #StoreLoad ba P3797 nop TARGET3734: ba RET3734 nop P3797: !_BLD [16] (FP) (Branch target of P3728) wr %g0, 0xf0, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ldda [%i3 + 0] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f36, %f18 fmovs %f18, %f11 ba P3798 nop TARGET3728: ba RET3728 nop P3798: !_MEMBAR (FP) P3799: !_ST [24] (maybe <- 0x3800007) (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 stwa %l4, [%i2 + 64] %asi add %l4, 1, %l4 P3800: !_REPLACEMENT [13] (Int) (Secondary ctx) wr %g0, 0x81, %asi sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 sethi %hi(0x2000), %l7 ld [%i3+32], %l3 st %l3, [%i3+32] add %i3, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] add %o5, %l7, %o5 ld [%o5+32], %l3 st %l3, [%o5+32] P3801: !_ST [5] (maybe <- 0x4300002a) (FP) (CBR) ! preparing store val #0, next val will be in f20 fmovs %f16, %f20 fadds %f16, %f17, %f16 st %f20, [%i0 + 64 ] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3801 nop RET3801: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P3802: !_MEMBAR (FP) membar #StoreLoad P3803: !_BLD [7] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 128] %asi, %f32 membar #Sync ! 1 addresses covered fmovd %f32, %f12 P3804: !_MEMBAR (FP) P3805: !_BLD [23] (FP) wr %g0, 0xf0, %asi ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f13 fmovs %f19, %f14 fmovd %f40, %f18 fmovs %f18, %f15 !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- P3806: !_MEMBAR (FP) P3807: !_LD [17] (Int) (Nucleus ctx) wr %g0, 0x4, %asi sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 lduwa [%i2 + 96] %asi, %o1 ! move %o1(lower) -> %o1(upper) sllx %o1, 32, %o1 P3808: !_REPLACEMENT [19] (Int) (Branch target of P3715) sethi %hi(0x2000), %o5 ld [%i3+0], %l6 st %l6, [%i3+0] add %i3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] add %l3, %o5, %l3 ld [%l3+0], %l6 st %l6, [%l3+0] ba P3809 nop TARGET3715: ba RET3715 nop P3809: !_LD [22] (Int) sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 lduw [%i3 + 4], %o5 ! move %o5(lower) -> %o1(lower) or %o5, %o1, %o1 P3810: !_IDC_FLIP [15] (Int) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 IDC_FLIP(3810, 15317, 7, 0x44000080, 0x80, %i2, 0x80, %l6, %l7, %o5, %l3) P3811: !_ST [24] (maybe <- 0x3800008) (Int) (Secondary ctx) wr %g0, 0x81, %asi stwa %l4, [%i3 + 64] %asi add %l4, 1, %l4 P3812: !_MEMBAR (FP) (Secondary ctx) P3813: !_BSTC [28] (maybe <- 0x4300002b) (FP) (CBR) (Secondary ctx) (Branch target of P3815) wr %g0, 0xe1, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i3 + 0 ] %asi ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3813 nop RET3813: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 ba P3814 nop TARGET3815: ba RET3815 nop P3814: !_MEMBAR (FP) (Secondary ctx) (Branch target of P3742) membar #StoreLoad ba P3815 nop TARGET3742: ba RET3742 nop P3815: !_REPLACEMENT [16] (Int) (CBR) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l3 ld [%i2+16], %l7 st %l7, [%i2+16] add %i2, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] add %l6, %l3, %l6 ld [%l6+16], %l7 st %l7, [%l6+16] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3815 nop RET3815: ! lfsr step begin srlx %l0, 1, %o5 xnor %o5, %l0, %o5 sllx %o5, 63, %o5 or %o5, %l0, %l0 srlx %l0, 1, %l0 P3816: !_IDC_FLIP [2] (Int) IDC_FLIP(3816, 29419, 7, 0x43000008, 0x8, %i0, 0x8, %l6, %l7, %o5, %l3) P3817: !_MEMBAR (FP) P3818: !_BST [4] (maybe <- 0x4300002c) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P3819: !_MEMBAR (FP) membar #StoreLoad P3820: !_PREFETCH [20] (Int) sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 256], 1 P3821: !_MEMBAR (FP) membar #StoreLoad P3822: !_BLD [5] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 64] %asi, %f0 membar #Sync ! 2 addresses covered fmovs %f8, %f1 P3823: !_MEMBAR (FP) P3824: !_LD [9] (Int) lduw [%i1 + 32], %o2 ! move %o2(lower) -> %o2(upper) sllx %o2, 32, %o2 P3825: !_MEMBAR (FP) P3826: !_BSTC [29] (maybe <- 0x43000031) (FP) wr %g0, 0xe0, %asi sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f32 membar #Sync stda %f32, [%i2 + 64 ] %asi P3827: !_MEMBAR (FP) membar #StoreLoad P3828: !_BLD [4] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f2 fmovd %f34, %f4 fmovd %f36, %f18 fmovs %f18, %f5 fmovd %f40, %f6 P3829: !_MEMBAR (FP) P3830: !_BST [1] (maybe <- 0x43000032) (FP) wr %g0, 0xf0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P3831: !_MEMBAR (FP) (CBR) membar #StoreLoad ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3831 nop RET3831: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P3832: !_PREFETCH [11] (Int) sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 prefetch [%i3 + 0], 1 P3833: !_MEMBAR (FP) membar #StoreLoad P3834: !_BLD [23] (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 ldda [%i2 + 0] %asi, %f32 membar #Sync ! 3 addresses covered fmovd %f32, %f18 fmovs %f18, %f7 fmovs %f19, %f8 fmovd %f40, %f18 fmovs %f18, %f9 P3835: !_MEMBAR (FP) (CBR) ! cbranch andcc %l0, 1, %g0 be,pt %xcc, TARGET3835 nop RET3835: ! lfsr step begin srlx %l0, 1, %l6 xnor %l6, %l0, %l6 sllx %l6, 63, %l6 or %l6, %l0, %l0 srlx %l0, 1, %l0 P3836: !_BSTC [4] (maybe <- 0x43000037) (FP) wr %g0, 0xe0, %asi ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f34 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #3, next val will be in f36 fmovd %f20, %f34 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #4, next val will be in f40 fmovd %f20, %f36 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i0 + 0 ] %asi P3837: !_MEMBAR (FP) (Branch target of P3701) membar #StoreLoad ba P3838 nop TARGET3701: ba RET3701 nop P3838: !_BLD [3] (FP) wr %g0, 0xf0, %asi ldda [%i0 + 0] %asi, %f32 membar #Sync ! 5 addresses covered fmovd %f32, %f10 fmovd %f34, %f12 fmovd %f36, %f18 fmovs %f18, %f13 fmovd %f40, %f14 P3839: !_MEMBAR (FP) (Branch target of P3790) ba P3840 nop TARGET3790: ba RET3790 nop P3840: !_LD [17] (FP) sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ld [%i3 + 96], %f15 ! 1 addresses covered !---- flushing fp results buffer to %f30 ---- fmovd %f0, %f30 fmovd %f2, %f30 fmovd %f4, %f30 fmovd %f6, %f30 fmovd %f8, %f30 fmovd %f10, %f30 fmovd %f12, %f30 fmovd %f14, %f30 !-- P3841: !_REPLACEMENT [21] (Int) (CBR) sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 add %i0, %i2, %i2 sethi %hi(0x2000), %l6 ld [%i2+0], %o5 st %o5, [%i2+0] add %i2, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] add %l7, %l6, %l7 ld [%l7+0], %o5 st %o5, [%l7+0] ! cbranch andcc %l0, 1, %g0 be,pn %xcc, TARGET3841 nop RET3841: ! lfsr step begin srlx %l0, 1, %l3 xnor %l3, %l0, %l3 sllx %l3, 63, %l3 or %l3, %l0, %l0 srlx %l0, 1, %l0 P3842: !_IDC_FLIP [17] (Int) IDC_FLIP(3842, 27331, 7, 0x44800060, 0x60, %i3, 0x60, %l6, %l7, %o5, %l3) P3843: !_MEMBAR (FP) P3844: !_BST [21] (maybe <- 0x4300003c) (FP) wr %g0, 0xf0, %asi sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3 add %i0, %i3, %i3 ! preparing store val #0, next val will be in f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 ! preparing store val #1, next val will be in f33 fmovs %f16, %f21 fadds %f16, %f17, %f16 ! preparing store val #2, next val will be in f40 fmovd %f20, %f32 fmovs %f16, %f20 fadds %f16, %f17, %f16 fmovd %f20, %f40 membar #Sync stda %f32, [%i3 + 0 ] %asi P3845: !_MEMBAR (FP) membar #StoreLoad P3846: !_LD [3] (Int) (Loop exit) lduw [%i0 + 16], %l6 ! move %l6(lower) -> %o2(lower) or %l6, %o2, %o2 !---- flushing int results buffer---- mov %o0, %l5 mov %o1, %l5 mov %o2, %l5 loop_exit_7_0: sub %l2, 1, %l2 cmp %l2, 0 bg loop_entry_7_0 nop P3847: !_MEMBAR (Int) membar #StoreLoad END_NODES7: ! Test instruction sequence for CPU 7 ends sethi %hi(0xdead0e0f), %o5 or %o5, %lo(0xdead0e0f), %o5 ! move %o5(lower) -> %o0(upper) sllx %o5, 32, %o0 sethi %hi(0xdead0e0f), %o5 or %o5, %lo(0xdead0e0f), %o5 stw %o5, [%i5] ld [%i5], %f0 !---- flushing int results buffer---- mov %o0, %l5 !---- flushing fp results buffer to %f30 ---- fmovs %f0, %f30 !-- restore retl nop tsotool_text_end: !#0 N1 P1 REPLACEMENT 8 Int BE Pri Loop_entry !#0 N2 P2 LD 33 -1 Int BE Pri !#0 N3 P3 ST 17 0x1 Int BE Pri !#0 N4 P4 MEMBAR !#0 N5 P5 BLD 21 -1 FP BE Pri !#0 N6 P5 BLD 22 -1 FP BE Pri !#A N5 N6 !#0 N7 P5 BLD 23 -1 FP BE Pri !#0 N8 P6 MEMBAR !#0 N9 P7 LD 2 -1 Int BE Pri !#0 N10 P8 MEMBAR !#0 N11 P9 BLD 21 -1 FP BE Pri !#0 N12 P9 BLD 22 -1 FP BE Pri !#A N11 N12 !#0 N13 P9 BLD 23 -1 FP BE Pri !#0 N14 P10 MEMBAR !#0 N15 P11 BST 21 0x3f800001 FP BE Pri !#0 N16 P11 BST 22 0x3f800002 FP BE Pri !#A N15 N16 !#0 N17 P11 BST 23 0x3f800003 FP BE Pri !#0 N18 P12 MEMBAR !#0 N19 P13 BST 0 0x3f800004 FP BE Sec !#0 N20 P13 BST 1 0x3f800005 FP BE Sec !#A N19 N20 !#0 N21 P13 BST 2 0x3f800006 FP BE Sec !#0 N22 P13 BST 3 0x3f800007 FP BE Sec !#0 N23 P13 BST 4 0x3f800008 FP BE Sec !#0 N24 P14 MEMBAR !#0 N25 P15 BSTC 31 0x3f800009 FP BE Pri !#0 N26 P16 MEMBAR !#0 N27 P17 BSTC 5 0x3f80000a FP BE Pri !#0 N28 P17 BSTC 6 0x3f80000b FP BE Pri !#0 N29 P18 MEMBAR !#0 N30 P19 REPLACEMENT 29 Int BE Pri !#0 N31 P20 REPLACEMENT 16 Int BE Pri !#0 N32 P21 MEMBAR !#0 N33 P22 BST 30 0x3f80000c FP BE Pri !#0 N34 P23 MEMBAR !#0 N35 P24 REPLACEMENT 25 Int BE Pri !#0 N36 P25 IDC_FLIP 33 Int BE Pri !#0 N37 P26 LD 22 -1 FP BE Pri !#0 N38 P27 ST 17 0x3f80000d FP BE Pri !#0 N39 P28 MEMBAR !#0 N40 P29 BLD 0 -1 FP BE Pri !#0 N41 P29 BLD 1 -1 FP BE Pri !#A N40 N41 !#0 N42 P29 BLD 2 -1 FP BE Pri !#0 N43 P29 BLD 3 -1 FP BE Pri !#0 N44 P29 BLD 4 -1 FP BE Pri !#0 N45 P30 MEMBAR !#0 N46 P31 REPLACEMENT 2 Int BE Pri !#0 N47 P32 MEMBAR !#0 N48 P33 BST 18 0x3f80000e FP BE Pri !#0 N49 P34 MEMBAR !#0 N50 P35 BST 7 0x3f80000f FP BE Pri !#0 N51 P36 MEMBAR !#0 N52 P37 BLD 20 -1 FP BE Pri !#0 N53 P38 MEMBAR !#0 N54 P39 ST 23 0x2 Int BE Pri !#0 N55 P40 IDC_FLIP 8 Int BE Pri !#0 N56 P41 MEMBAR !#0 N57 P42 BSTC 0 0x3f800010 FP BE Pri !#0 N58 P42 BSTC 1 0x3f800011 FP BE Pri !#A N57 N58 !#0 N59 P42 BSTC 2 0x3f800012 FP BE Pri !#0 N60 P42 BSTC 3 0x3f800013 FP BE Pri !#0 N61 P42 BSTC 4 0x3f800014 FP BE Pri !#0 N62 P43 MEMBAR !#0 N63 P44 BLD 29 -1 FP BE Pri !#0 N64 P45 MEMBAR !#0 N65 P46 BLD 26 -1 FP BE Pri !#0 N66 P46 BLD 27 -1 FP BE Pri !#0 N67 P47 MEMBAR !#0 N68 P48 REPLACEMENT 30 Int BE Pri !#0 N69 P49 MEMBAR !#0 N70 P50 BST 24 0x3f800015 FP BE Pri !#0 N71 P50 BST 25 0x3f800016 FP BE Pri !#0 N72 P51 MEMBAR !#0 N73 P52 BSTC 0 0x3f800017 FP BE Pri !#0 N74 P52 BSTC 1 0x3f800018 FP BE Pri !#A N73 N74 !#0 N75 P52 BSTC 2 0x3f800019 FP BE Pri !#0 N76 P52 BSTC 3 0x3f80001a FP BE Pri !#0 N77 P52 BSTC 4 0x3f80001b FP BE Pri !#0 N78 P53 MEMBAR !#0 N79 P54 LD 24 -1 FP BE Pri !#0 N80 P55 MEMBAR !#0 N81 P56 BLD 26 -1 FP BE Pri !#0 N82 P56 BLD 27 -1 FP BE Pri !#0 N83 P57 MEMBAR !#0 N84 P58 REPLACEMENT 28 Int BE Pri !#0 N85 P59 MEMBAR !#0 N86 P60 BLD 21 -1 FP BE Sec !#0 N87 P60 BLD 22 -1 FP BE Sec !#A N86 N87 !#0 N88 P60 BLD 23 -1 FP BE Sec !#0 N89 P61 MEMBAR !#0 N90 P62 BST 0 0x3f80001c FP BE Pri !#0 N91 P62 BST 1 0x3f80001d FP BE Pri !#A N90 N91 !#0 N92 P62 BST 2 0x3f80001e FP BE Pri !#0 N93 P62 BST 3 0x3f80001f FP BE Pri !#0 N94 P62 BST 4 0x3f800020 FP BE Pri !#0 N95 P63 MEMBAR !#0 N96 P64 LD 31 -1 Int BE Pri !#0 N97 P65 MEMBAR !#0 N98 P66 BLD 0 -1 FP BE Pri !#0 N99 P66 BLD 1 -1 FP BE Pri !#A N98 N99 !#0 N100 P66 BLD 2 -1 FP BE Pri !#0 N101 P66 BLD 3 -1 FP BE Pri !#0 N102 P66 BLD 4 -1 FP BE Pri !#0 N103 P67 MEMBAR !#0 N104 P68 LD 27 -1 Int BE Pri !#0 N105 P69 MEMBAR !#0 N106 P70 BST 11 0x3f800021 FP BE Pri !#0 N107 P70 BST 12 0x3f800022 FP BE Pri !#A N106 N107 !#0 N108 P70 BST 13 0x3f800023 FP BE Pri !#0 N109 P71 MEMBAR !#0 N110 P72 BST 8 0x3f800024 FP BE Pri !#0 N111 P72 BST 9 0x3f800025 FP BE Pri !#0 N112 P73 MEMBAR !#0 N113 P74 BLD 10 -1 FP BE Pri !#0 N114 P75 MEMBAR !#0 N115 P76 REPLACEMENT 15 Int BE Pri !#0 N116 P77 MEMBAR !#0 N117 P78 BLD 30 -1 FP BE Pri !#0 N118 P79 MEMBAR !#0 N119 P80 LD 32 -1 Int BE Pri !#0 N120 P81 MEMBAR !#0 N121 P82 BLD 0 -1 FP BE Pri !#0 N122 P82 BLD 1 -1 FP BE Pri !#A N121 N122 !#0 N123 P82 BLD 2 -1 FP BE Pri !#0 N124 P82 BLD 3 -1 FP BE Pri !#0 N125 P82 BLD 4 -1 FP BE Pri !#0 N126 P83 MEMBAR !#0 N127 P84 BLD 7 -1 FP BE Pri !#0 N128 P85 MEMBAR !#0 N129 P86 REPLACEMENT 18 Int BE Pri !#0 N130 P87 LD 6 -1 FP BE Pri !#0 N131 P88 MEMBAR !#0 N132 P89 BLD 21 -1 FP BE Pri !#0 N133 P89 BLD 22 -1 FP BE Pri !#A N132 N133 !#0 N134 P89 BLD 23 -1 FP BE Pri !#0 N135 P90 MEMBAR !#0 N136 P91 BSTC 0 0x3f800026 FP BE Pri !#0 N137 P91 BSTC 1 0x3f800027 FP BE Pri !#A N136 N137 !#0 N138 P91 BSTC 2 0x3f800028 FP BE Pri !#0 N139 P91 BSTC 3 0x3f800029 FP BE Pri !#0 N140 P91 BSTC 4 0x3f80002a FP BE Pri !#0 N141 P92 MEMBAR !#0 N142 P93 BSTC 0 0x3f80002b FP BE Sec !#0 N143 P93 BSTC 1 0x3f80002c FP BE Sec !#A N142 N143 !#0 N144 P93 BSTC 2 0x3f80002d FP BE Sec !#0 N145 P93 BSTC 3 0x3f80002e FP BE Sec !#0 N146 P93 BSTC 4 0x3f80002f FP BE Sec !#0 N147 P94 MEMBAR !#0 N148 P95 PREFETCH 14 Int LE Pri !#0 N149 P96 LD 18 -1 FP BE Pri !#0 N150 P97 LD 27 -1 FP BE Pri !#0 N151 P98 ST 32 0x3 Int BE Pri !#0 N152 P99 IDC_FLIP 31 Int BE Pri !#0 N153 P100 MEMBAR !#0 N154 P101 BLD 26 -1 FP BE Pri !#0 N155 P101 BLD 27 -1 FP BE Pri !#0 N156 P102 MEMBAR !#0 N157 P103 IDC_FLIP 7 Int BE Pri !#0 N158 P104 IDC_FLIP 17 Int BE Pri !#0 N159 P105 MEMBAR !#0 N160 P106 BSTC 29 0x3f800030 FP BE Sec !#0 N161 P107 MEMBAR !#0 N162 P108 REPLACEMENT 29 Int BE Pri !#0 N163 P109 PREFETCH 33 Int BE Pri !#0 N164 P110 REPLACEMENT 29 Int BE Pri !#0 N165 P111 MEMBAR !#0 N166 P112 BST 21 0x3f800031 FP BE Pri !#0 N167 P112 BST 22 0x3f800032 FP BE Pri !#A N166 N167 !#0 N168 P112 BST 23 0x3f800033 FP BE Pri !#0 N169 P113 MEMBAR !#0 N170 P114 REPLACEMENT 12 Int BE Pri !#0 N171 P115 MEMBAR !#0 N172 P116 BST 0 0x3f800034 FP BE Pri !#0 N173 P116 BST 1 0x3f800035 FP BE Pri !#A N172 N173 !#0 N174 P116 BST 2 0x3f800036 FP BE Pri !#0 N175 P116 BST 3 0x3f800037 FP BE Pri !#0 N176 P116 BST 4 0x3f800038 FP BE Pri !#0 N177 P117 MEMBAR !#0 N178 P118 REPLACEMENT 9 Int BE Pri !#0 N179 P119 ST 8 0x3f800039 FP BE Sec !#0 N180 P120 PREFETCH 12 Int BE Pri !#0 N181 P121 MEMBAR !#0 N182 P122 BLD 32 -1 FP BE Pri !#0 N183 P123 MEMBAR !#0 N184 P124 IDC_FLIP 11 Int BE Pri !#0 N185 P125 LD 2 -1 FP BE Pri !#0 N186 P126 ST 24 0x4 Int BE Pri !#0 N187 P127 LD 27 -1 Int BE Pri !#0 N188 P128 MEMBAR !#0 N189 P129 BLD 24 -1 FP BE Pri !#0 N190 P129 BLD 25 -1 FP BE Pri !#0 N191 P130 MEMBAR !#0 N192 P131 BST 11 0x3f80003a FP BE Pri !#0 N193 P131 BST 12 0x3f80003b FP BE Pri !#A N192 N193 !#0 N194 P131 BST 13 0x3f80003c FP BE Pri !#0 N195 P132 MEMBAR !#0 N196 P133 REPLACEMENT 11 Int BE Pri !#0 N197 P134 ST 12 0x5 Int BE Pri !#0 N198 P135 PREFETCH 4 Int LE Pri !#0 N199 P136 MEMBAR !#0 N200 P137 BSTC 20 0x3f80003d FP BE Pri !#0 N201 P138 MEMBAR !#0 N202 P139 LD 20 -1 Int BE Nuc !#0 N203 P140 MEMBAR !#0 N204 P141 BSTC 7 0x3f80003e FP BE Pri !#0 N205 P142 MEMBAR !#0 N206 P143 BSTC 19 0x3f80003f FP BE Pri !#0 N207 P144 MEMBAR !#0 N208 P145 BLD 8 -1 FP BE Pri !#0 N209 P145 BLD 9 -1 FP BE Pri !#0 N210 P146 MEMBAR !#0 N211 P147 BSTC 11 0x3f800040 FP BE Pri !#0 N212 P147 BSTC 12 0x3f800041 FP BE Pri !#A N211 N212 !#0 N213 P147 BSTC 13 0x3f800042 FP BE Pri !#0 N214 P148 MEMBAR !#0 N215 P149 PREFETCH 26 Int BE Pri !#0 N216 P150 MEMBAR !#0 N217 P151 BLD 16 -1 FP BE Pri !#0 N218 P152 MEMBAR !#0 N219 P153 REPLACEMENT 17 Int BE Sec !#0 N220 P154 LD 12 -1 FP BE Sec !#0 N221 P155 MEMBAR !#0 N222 P156 BST 8 0x3f800043 FP BE Sec !#0 N223 P156 BST 9 0x3f800044 FP BE Sec !#0 N224 P157 MEMBAR !#0 N225 P158 BST 29 0x3f800045 FP BE Pri !#0 N226 P159 MEMBAR !#0 N227 P160 BSTC 0 0x3f800046 FP BE Pri !#0 N228 P160 BSTC 1 0x3f800047 FP BE Pri !#A N227 N228 !#0 N229 P160 BSTC 2 0x3f800048 FP BE Pri !#0 N230 P160 BSTC 3 0x3f800049 FP BE Pri !#0 N231 P160 BSTC 4 0x3f80004a FP BE Pri !#0 N232 P161 MEMBAR !#0 N233 P162 PREFETCH 7 Int BE Pri !#0 N234 P163 MEMBAR !#0 N235 P164 BLD 15 -1 FP BE Sec !#0 N236 P165 MEMBAR !#0 N237 P166 BLD 33 -1 FP BE Pri !#0 N238 P167 MEMBAR !#0 N239 P168 ST 27 0x6 Int BE Pri !#0 N240 P169 PREFETCH 21 Int BE Pri !#0 N241 P170 LD 14 -1 Int BE Pri !#0 N242 P171 MEMBAR !#0 N243 P172 BST 5 0x3f80004b FP BE Pri !#0 N244 P172 BST 6 0x3f80004c FP BE Pri !#0 N245 P173 MEMBAR !#0 N246 P174 ST 33 0x7 Int LE Nuc !#0 N247 P175 MEMBAR !#0 N248 P176 BLD 21 -1 FP BE Pri !#0 N249 P176 BLD 22 -1 FP BE Pri !#A N248 N249 !#0 N250 P176 BLD 23 -1 FP BE Pri !#0 N251 P177 MEMBAR !#0 N252 P178 BLD 0 -1 FP BE Pri !#0 N253 P178 BLD 1 -1 FP BE Pri !#A N252 N253 !#0 N254 P178 BLD 2 -1 FP BE Pri !#0 N255 P178 BLD 3 -1 FP BE Pri !#0 N256 P178 BLD 4 -1 FP BE Pri !#0 N257 P179 MEMBAR !#0 N258 P180 BLD 21 -1 FP BE Sec !#0 N259 P180 BLD 22 -1 FP BE Sec !#A N258 N259 !#0 N260 P180 BLD 23 -1 FP BE Sec !#0 N261 P181 MEMBAR !#0 N262 P182 LD 17 -1 FP BE Pri !#0 N263 P183 LD 18 -1 FP BE Nuc !#0 N264 P184 MEMBAR !#0 N265 P185 BLD 20 -1 FP BE Pri !#0 N266 P186 MEMBAR !#0 N267 P187 REPLACEMENT 5 Int BE Pri !#0 N268 P188 MEMBAR !#0 N269 P189 BLD 11 -1 FP BE Pri !#0 N270 P189 BLD 12 -1 FP BE Pri !#A N269 N270 !#0 N271 P189 BLD 13 -1 FP BE Pri !#0 N272 P190 MEMBAR !#0 N273 P191 REPLACEMENT 28 Int BE Sec !#0 N274 P192 PREFETCH 4 Int BE Nuc !#0 N275 P193 PREFETCH 21 Int BE Sec !#0 N276 P194 ST 24 0x3f80004d FP BE Pri !#0 N277 P195 ST 5 0x8 Int LE Pri !#0 N278 P196 FLUSHI 0 Int BE Pri !#0 N279 P197 ST 4 0x9 Int BE Pri !#0 N280 P198 REPLACEMENT 32 Int BE Pri !#0 N281 P199 MEMBAR !#0 N282 P200 BSTC 21 0x3f80004e FP BE Pri !#0 N283 P200 BSTC 22 0x3f80004f FP BE Pri !#A N282 N283 !#0 N284 P200 BSTC 23 0x3f800050 FP BE Pri !#0 N285 P201 MEMBAR !#0 N286 P202 BST 10 0x3f800051 FP BE Pri !#0 N287 P203 MEMBAR !#0 N288 P204 ST 28 0x3f800052 FP BE Pri !#0 N289 P205 MEMBAR !#0 N290 P206 BLD 0 -1 FP BE Pri !#0 N291 P206 BLD 1 -1 FP BE Pri !#A N290 N291 !#0 N292 P206 BLD 2 -1 FP BE Pri !#0 N293 P206 BLD 3 -1 FP BE Pri !#0 N294 P206 BLD 4 -1 FP BE Pri !#0 N295 P207 MEMBAR !#0 N296 P208 ST 7 0xa Int BE Pri !#0 N297 P209 MEMBAR !#0 N298 P210 BST 15 0x3f800053 FP BE Pri !#0 N299 P211 MEMBAR !#0 N300 P212 REPLACEMENT 1 Int BE Pri !#0 N301 P213 MEMBAR !#0 N302 P214 BLD 14 -1 FP BE Pri !#0 N303 P215 MEMBAR !#0 N304 P216 BSTC 33 0x3f800054 FP BE Pri !#0 N305 P217 MEMBAR !#0 N306 P218 BSTC 0 0x3f800055 FP BE Pri !#0 N307 P218 BSTC 1 0x3f800056 FP BE Pri !#A N306 N307 !#0 N308 P218 BSTC 2 0x3f800057 FP BE Pri !#0 N309 P218 BSTC 3 0x3f800058 FP BE Pri !#0 N310 P218 BSTC 4 0x3f800059 FP BE Pri !#0 N311 P219 MEMBAR !#0 N312 P220 ST 19 0x3f80005a FP BE Pri !#0 N313 P221 MEMBAR !#0 N314 P222 BST 10 0x3f80005b FP BE Pri !#0 N315 P223 MEMBAR !#0 N316 P224 REPLACEMENT 21 Int BE Pri !#0 N317 P225 MEMBAR !#0 N318 P226 BLD 5 -1 FP BE Pri !#0 N319 P226 BLD 6 -1 FP BE Pri !#0 N320 P227 MEMBAR !#0 N321 P228 BLD 26 -1 FP BE Pri !#0 N322 P228 BLD 27 -1 FP BE Pri !#0 N323 P229 MEMBAR !#0 N324 P230 LD 22 -1 Int BE Sec !#0 N325 P231 MEMBAR !#0 N326 P232 BLD 33 -1 FP BE Pri !#0 N327 P233 MEMBAR !#0 N328 P234 BST 7 0x3f80005c FP BE Pri !#0 N329 P235 MEMBAR !#0 N330 P236 LD 28 -1 Int BE Pri Loop_exit !#0 N331 P1 REPLACEMENT 8 Int BE Pri Loop_entry !#0 N332 P2 LD 33 -1 Int BE Pri !#0 N333 P3 ST 17 0xb Int BE Pri !#0 N334 P4 MEMBAR !#0 N335 P5 BLD 21 -1 FP BE Pri !#0 N336 P5 BLD 22 -1 FP BE Pri !#A N335 N336 !#0 N337 P5 BLD 23 -1 FP BE Pri !#0 N338 P6 MEMBAR !#0 N339 P7 LD 2 -1 Int BE Pri !#0 N340 P8 MEMBAR !#0 N341 P9 BLD 21 -1 FP BE Pri !#0 N342 P9 BLD 22 -1 FP BE Pri !#A N341 N342 !#0 N343 P9 BLD 23 -1 FP BE Pri !#0 N344 P10 MEMBAR !#0 N345 P11 BST 21 0x3f80005d FP BE Pri !#0 N346 P11 BST 22 0x3f80005e FP BE Pri !#A N345 N346 !#0 N347 P11 BST 23 0x3f80005f FP BE Pri !#0 N348 P12 MEMBAR !#0 N349 P13 BST 0 0x3f800060 FP BE Sec !#0 N350 P13 BST 1 0x3f800061 FP BE Sec !#A N349 N350 !#0 N351 P13 BST 2 0x3f800062 FP BE Sec !#0 N352 P13 BST 3 0x3f800063 FP BE Sec !#0 N353 P13 BST 4 0x3f800064 FP BE Sec !#0 N354 P14 MEMBAR !#0 N355 P15 BSTC 31 0x3f800065 FP BE Pri !#0 N356 P16 MEMBAR !#0 N357 P17 BSTC 5 0x3f800066 FP BE Pri !#0 N358 P17 BSTC 6 0x3f800067 FP BE Pri !#0 N359 P18 MEMBAR !#0 N360 P19 REPLACEMENT 29 Int BE Pri !#0 N361 P20 REPLACEMENT 16 Int BE Pri !#0 N362 P21 MEMBAR !#0 N363 P22 BST 30 0x3f800068 FP BE Pri !#0 N364 P23 MEMBAR !#0 N365 P24 REPLACEMENT 25 Int BE Pri !#0 N366 P25 IDC_FLIP 33 Int BE Pri !#0 N367 P26 LD 22 -1 FP BE Pri !#0 N368 P27 ST 17 0x3f800069 FP BE Pri !#0 N369 P28 MEMBAR !#0 N370 P29 BLD 0 -1 FP BE Pri !#0 N371 P29 BLD 1 -1 FP BE Pri !#A N370 N371 !#0 N372 P29 BLD 2 -1 FP BE Pri !#0 N373 P29 BLD 3 -1 FP BE Pri !#0 N374 P29 BLD 4 -1 FP BE Pri !#0 N375 P30 MEMBAR !#0 N376 P31 REPLACEMENT 2 Int BE Pri !#0 N377 P32 MEMBAR !#0 N378 P33 BST 18 0x3f80006a FP BE Pri !#0 N379 P34 MEMBAR !#0 N380 P35 BST 7 0x3f80006b FP BE Pri !#0 N381 P36 MEMBAR !#0 N382 P37 BLD 20 -1 FP BE Pri !#0 N383 P38 MEMBAR !#0 N384 P39 ST 23 0xc Int BE Pri !#0 N385 P40 IDC_FLIP 8 Int BE Pri !#0 N386 P41 MEMBAR !#0 N387 P42 BSTC 0 0x3f80006c FP BE Pri !#0 N388 P42 BSTC 1 0x3f80006d FP BE Pri !#A N387 N388 !#0 N389 P42 BSTC 2 0x3f80006e FP BE Pri !#0 N390 P42 BSTC 3 0x3f80006f FP BE Pri !#0 N391 P42 BSTC 4 0x3f800070 FP BE Pri !#0 N392 P43 MEMBAR !#0 N393 P44 BLD 29 -1 FP BE Pri !#0 N394 P45 MEMBAR !#0 N395 P46 BLD 26 -1 FP BE Pri !#0 N396 P46 BLD 27 -1 FP BE Pri !#0 N397 P47 MEMBAR !#0 N398 P48 REPLACEMENT 30 Int BE Pri !#0 N399 P49 MEMBAR !#0 N400 P50 BST 24 0x3f800071 FP BE Pri !#0 N401 P50 BST 25 0x3f800072 FP BE Pri !#0 N402 P51 MEMBAR !#0 N403 P52 BSTC 0 0x3f800073 FP BE Pri !#0 N404 P52 BSTC 1 0x3f800074 FP BE Pri !#A N403 N404 !#0 N405 P52 BSTC 2 0x3f800075 FP BE Pri !#0 N406 P52 BSTC 3 0x3f800076 FP BE Pri !#0 N407 P52 BSTC 4 0x3f800077 FP BE Pri !#0 N408 P53 MEMBAR !#0 N409 P54 LD 24 -1 FP BE Pri !#0 N410 P55 MEMBAR !#0 N411 P56 BLD 26 -1 FP BE Pri !#0 N412 P56 BLD 27 -1 FP BE Pri !#0 N413 P57 MEMBAR !#0 N414 P58 REPLACEMENT 28 Int BE Pri !#0 N415 P59 MEMBAR !#0 N416 P60 BLD 21 -1 FP BE Sec !#0 N417 P60 BLD 22 -1 FP BE Sec !#A N416 N417 !#0 N418 P60 BLD 23 -1 FP BE Sec !#0 N419 P61 MEMBAR !#0 N420 P62 BST 0 0x3f800078 FP BE Pri !#0 N421 P62 BST 1 0x3f800079 FP BE Pri !#A N420 N421 !#0 N422 P62 BST 2 0x3f80007a FP BE Pri !#0 N423 P62 BST 3 0x3f80007b FP BE Pri !#0 N424 P62 BST 4 0x3f80007c FP BE Pri !#0 N425 P63 MEMBAR !#0 N426 P64 LD 31 -1 Int BE Pri !#0 N427 P65 MEMBAR !#0 N428 P66 BLD 0 -1 FP BE Pri !#0 N429 P66 BLD 1 -1 FP BE Pri !#A N428 N429 !#0 N430 P66 BLD 2 -1 FP BE Pri !#0 N431 P66 BLD 3 -1 FP BE Pri !#0 N432 P66 BLD 4 -1 FP BE Pri !#0 N433 P67 MEMBAR !#0 N434 P68 LD 27 -1 Int BE Pri !#0 N435 P69 MEMBAR !#0 N436 P70 BST 11 0x3f80007d FP BE Pri !#0 N437 P70 BST 12 0x3f80007e FP BE Pri !#A N436 N437 !#0 N438 P70 BST 13 0x3f80007f FP BE Pri !#0 N439 P71 MEMBAR !#0 N440 P72 BST 8 0x3f800080 FP BE Pri !#0 N441 P72 BST 9 0x3f800081 FP BE Pri !#0 N442 P73 MEMBAR !#0 N443 P74 BLD 10 -1 FP BE Pri !#0 N444 P75 MEMBAR !#0 N445 P76 REPLACEMENT 15 Int BE Pri !#0 N446 P77 MEMBAR !#0 N447 P78 BLD 30 -1 FP BE Pri !#0 N448 P79 MEMBAR !#0 N449 P80 LD 32 -1 Int BE Pri !#0 N450 P81 MEMBAR !#0 N451 P82 BLD 0 -1 FP BE Pri !#0 N452 P82 BLD 1 -1 FP BE Pri !#A N451 N452 !#0 N453 P82 BLD 2 -1 FP BE Pri !#0 N454 P82 BLD 3 -1 FP BE Pri !#0 N455 P82 BLD 4 -1 FP BE Pri !#0 N456 P83 MEMBAR !#0 N457 P84 BLD 7 -1 FP BE Pri !#0 N458 P85 MEMBAR !#0 N459 P86 REPLACEMENT 18 Int BE Pri !#0 N460 P87 LD 6 -1 FP BE Pri !#0 N461 P88 MEMBAR !#0 N462 P89 BLD 21 -1 FP BE Pri !#0 N463 P89 BLD 22 -1 FP BE Pri !#A N462 N463 !#0 N464 P89 BLD 23 -1 FP BE Pri !#0 N465 P90 MEMBAR !#0 N466 P91 BSTC 0 0x3f800082 FP BE Pri !#0 N467 P91 BSTC 1 0x3f800083 FP BE Pri !#A N466 N467 !#0 N468 P91 BSTC 2 0x3f800084 FP BE Pri !#0 N469 P91 BSTC 3 0x3f800085 FP BE Pri !#0 N470 P91 BSTC 4 0x3f800086 FP BE Pri !#0 N471 P92 MEMBAR !#0 N472 P93 BSTC 0 0x3f800087 FP BE Sec !#0 N473 P93 BSTC 1 0x3f800088 FP BE Sec !#A N472 N473 !#0 N474 P93 BSTC 2 0x3f800089 FP BE Sec !#0 N475 P93 BSTC 3 0x3f80008a FP BE Sec !#0 N476 P93 BSTC 4 0x3f80008b FP BE Sec !#0 N477 P94 MEMBAR !#0 N478 P95 PREFETCH 14 Int LE Pri !#0 N479 P96 LD 18 -1 FP BE Pri !#0 N480 P97 LD 27 -1 FP BE Pri !#0 N481 P98 ST 32 0xd Int BE Pri !#0 N482 P99 IDC_FLIP 31 Int BE Pri !#0 N483 P100 MEMBAR !#0 N484 P101 BLD 26 -1 FP BE Pri !#0 N485 P101 BLD 27 -1 FP BE Pri !#0 N486 P102 MEMBAR !#0 N487 P103 IDC_FLIP 7 Int BE Pri !#0 N488 P104 IDC_FLIP 17 Int BE Pri !#0 N489 P105 MEMBAR !#0 N490 P106 BSTC 29 0x3f80008c FP BE Sec !#0 N491 P107 MEMBAR !#0 N492 P108 REPLACEMENT 29 Int BE Pri !#0 N493 P109 PREFETCH 33 Int BE Pri !#0 N494 P110 REPLACEMENT 29 Int BE Pri !#0 N495 P111 MEMBAR !#0 N496 P112 BST 21 0x3f80008d FP BE Pri !#0 N497 P112 BST 22 0x3f80008e FP BE Pri !#A N496 N497 !#0 N498 P112 BST 23 0x3f80008f FP BE Pri !#0 N499 P113 MEMBAR !#0 N500 P114 REPLACEMENT 12 Int BE Pri !#0 N501 P115 MEMBAR !#0 N502 P116 BST 0 0x3f800090 FP BE Pri !#0 N503 P116 BST 1 0x3f800091 FP BE Pri !#A N502 N503 !#0 N504 P116 BST 2 0x3f800092 FP BE Pri !#0 N505 P116 BST 3 0x3f800093 FP BE Pri !#0 N506 P116 BST 4 0x3f800094 FP BE Pri !#0 N507 P117 MEMBAR !#0 N508 P118 REPLACEMENT 9 Int BE Pri !#0 N509 P119 ST 8 0x3f800095 FP BE Sec !#0 N510 P120 PREFETCH 12 Int BE Pri !#0 N511 P121 MEMBAR !#0 N512 P122 BLD 32 -1 FP BE Pri !#0 N513 P123 MEMBAR !#0 N514 P124 IDC_FLIP 11 Int BE Pri !#0 N515 P125 LD 2 -1 FP BE Pri !#0 N516 P126 ST 24 0xe Int BE Pri !#0 N517 P127 LD 27 -1 Int BE Pri !#0 N518 P128 MEMBAR !#0 N519 P129 BLD 24 -1 FP BE Pri !#0 N520 P129 BLD 25 -1 FP BE Pri !#0 N521 P130 MEMBAR !#0 N522 P131 BST 11 0x3f800096 FP BE Pri !#0 N523 P131 BST 12 0x3f800097 FP BE Pri !#A N522 N523 !#0 N524 P131 BST 13 0x3f800098 FP BE Pri !#0 N525 P132 MEMBAR !#0 N526 P133 REPLACEMENT 11 Int BE Pri !#0 N527 P134 ST 12 0xf Int BE Pri !#0 N528 P135 PREFETCH 4 Int LE Pri !#0 N529 P136 MEMBAR !#0 N530 P137 BSTC 20 0x3f800099 FP BE Pri !#0 N531 P138 MEMBAR !#0 N532 P139 LD 20 -1 Int BE Nuc !#0 N533 P140 MEMBAR !#0 N534 P141 BSTC 7 0x3f80009a FP BE Pri !#0 N535 P142 MEMBAR !#0 N536 P143 BSTC 19 0x3f80009b FP BE Pri !#0 N537 P144 MEMBAR !#0 N538 P145 BLD 8 -1 FP BE Pri !#0 N539 P145 BLD 9 -1 FP BE Pri !#0 N540 P146 MEMBAR !#0 N541 P147 BSTC 11 0x3f80009c FP BE Pri !#0 N542 P147 BSTC 12 0x3f80009d FP BE Pri !#A N541 N542 !#0 N543 P147 BSTC 13 0x3f80009e FP BE Pri !#0 N544 P148 MEMBAR !#0 N545 P149 PREFETCH 26 Int BE Pri !#0 N546 P150 MEMBAR !#0 N547 P151 BLD 16 -1 FP BE Pri !#0 N548 P152 MEMBAR !#0 N549 P153 REPLACEMENT 17 Int BE Sec !#0 N550 P154 LD 12 -1 FP BE Sec !#0 N551 P155 MEMBAR !#0 N552 P156 BST 8 0x3f80009f FP BE Sec !#0 N553 P156 BST 9 0x3f8000a0 FP BE Sec !#0 N554 P157 MEMBAR !#0 N555 P158 BST 29 0x3f8000a1 FP BE Pri !#0 N556 P159 MEMBAR !#0 N557 P160 BSTC 0 0x3f8000a2 FP BE Pri !#0 N558 P160 BSTC 1 0x3f8000a3 FP BE Pri !#A N557 N558 !#0 N559 P160 BSTC 2 0x3f8000a4 FP BE Pri !#0 N560 P160 BSTC 3 0x3f8000a5 FP BE Pri !#0 N561 P160 BSTC 4 0x3f8000a6 FP BE Pri !#0 N562 P161 MEMBAR !#0 N563 P162 PREFETCH 7 Int BE Pri !#0 N564 P163 MEMBAR !#0 N565 P164 BLD 15 -1 FP BE Sec !#0 N566 P165 MEMBAR !#0 N567 P166 BLD 33 -1 FP BE Pri !#0 N568 P167 MEMBAR !#0 N569 P168 ST 27 0x10 Int BE Pri !#0 N570 P169 PREFETCH 21 Int BE Pri !#0 N571 P170 LD 14 -1 Int BE Pri !#0 N572 P171 MEMBAR !#0 N573 P172 BST 5 0x3f8000a7 FP BE Pri !#0 N574 P172 BST 6 0x3f8000a8 FP BE Pri !#0 N575 P173 MEMBAR !#0 N576 P174 ST 33 0x11 Int LE Nuc !#0 N577 P175 MEMBAR !#0 N578 P176 BLD 21 -1 FP BE Pri !#0 N579 P176 BLD 22 -1 FP BE Pri !#A N578 N579 !#0 N580 P176 BLD 23 -1 FP BE Pri !#0 N581 P177 MEMBAR !#0 N582 P178 BLD 0 -1 FP BE Pri !#0 N583 P178 BLD 1 -1 FP BE Pri !#A N582 N583 !#0 N584 P178 BLD 2 -1 FP BE Pri !#0 N585 P178 BLD 3 -1 FP BE Pri !#0 N586 P178 BLD 4 -1 FP BE Pri !#0 N587 P179 MEMBAR !#0 N588 P180 BLD 21 -1 FP BE Sec !#0 N589 P180 BLD 22 -1 FP BE Sec !#A N588 N589 !#0 N590 P180 BLD 23 -1 FP BE Sec !#0 N591 P181 MEMBAR !#0 N592 P182 LD 17 -1 FP BE Pri !#0 N593 P183 LD 18 -1 FP BE Nuc !#0 N594 P184 MEMBAR !#0 N595 P185 BLD 20 -1 FP BE Pri !#0 N596 P186 MEMBAR !#0 N597 P187 REPLACEMENT 5 Int BE Pri !#0 N598 P188 MEMBAR !#0 N599 P189 BLD 11 -1 FP BE Pri !#0 N600 P189 BLD 12 -1 FP BE Pri !#A N599 N600 !#0 N601 P189 BLD 13 -1 FP BE Pri !#0 N602 P190 MEMBAR !#0 N603 P191 REPLACEMENT 28 Int BE Sec !#0 N604 P192 PREFETCH 4 Int BE Nuc !#0 N605 P193 PREFETCH 21 Int BE Sec !#0 N606 P194 ST 24 0x3f8000a9 FP BE Pri !#0 N607 P195 ST 5 0x12 Int LE Pri !#0 N608 P196 FLUSHI 0 Int BE Pri !#0 N609 P197 ST 4 0x13 Int BE Pri !#0 N610 P198 REPLACEMENT 32 Int BE Pri !#0 N611 P199 MEMBAR !#0 N612 P200 BSTC 21 0x3f8000aa FP BE Pri !#0 N613 P200 BSTC 22 0x3f8000ab FP BE Pri !#A N612 N613 !#0 N614 P200 BSTC 23 0x3f8000ac FP BE Pri !#0 N615 P201 MEMBAR !#0 N616 P202 BST 10 0x3f8000ad FP BE Pri !#0 N617 P203 MEMBAR !#0 N618 P204 ST 28 0x3f8000ae FP BE Pri !#0 N619 P205 MEMBAR !#0 N620 P206 BLD 0 -1 FP BE Pri !#0 N621 P206 BLD 1 -1 FP BE Pri !#A N620 N621 !#0 N622 P206 BLD 2 -1 FP BE Pri !#0 N623 P206 BLD 3 -1 FP BE Pri !#0 N624 P206 BLD 4 -1 FP BE Pri !#0 N625 P207 MEMBAR !#0 N626 P208 ST 7 0x14 Int BE Pri !#0 N627 P209 MEMBAR !#0 N628 P210 BST 15 0x3f8000af FP BE Pri !#0 N629 P211 MEMBAR !#0 N630 P212 REPLACEMENT 1 Int BE Pri !#0 N631 P213 MEMBAR !#0 N632 P214 BLD 14 -1 FP BE Pri !#0 N633 P215 MEMBAR !#0 N634 P216 BSTC 33 0x3f8000b0 FP BE Pri !#0 N635 P217 MEMBAR !#0 N636 P218 BSTC 0 0x3f8000b1 FP BE Pri !#0 N637 P218 BSTC 1 0x3f8000b2 FP BE Pri !#A N636 N637 !#0 N638 P218 BSTC 2 0x3f8000b3 FP BE Pri !#0 N639 P218 BSTC 3 0x3f8000b4 FP BE Pri !#0 N640 P218 BSTC 4 0x3f8000b5 FP BE Pri !#0 N641 P219 MEMBAR !#0 N642 P220 ST 19 0x3f8000b6 FP BE Pri !#0 N643 P221 MEMBAR !#0 N644 P222 BST 10 0x3f8000b7 FP BE Pri !#0 N645 P223 MEMBAR !#0 N646 P224 REPLACEMENT 21 Int BE Pri !#0 N647 P225 MEMBAR !#0 N648 P226 BLD 5 -1 FP BE Pri !#0 N649 P226 BLD 6 -1 FP BE Pri !#0 N650 P227 MEMBAR !#0 N651 P228 BLD 26 -1 FP BE Pri !#0 N652 P228 BLD 27 -1 FP BE Pri !#0 N653 P229 MEMBAR !#0 N654 P230 LD 22 -1 Int BE Sec !#0 N655 P231 MEMBAR !#0 N656 P232 BLD 33 -1 FP BE Pri !#0 N657 P233 MEMBAR !#0 N658 P234 BST 7 0x3f8000b8 FP BE Pri !#0 N659 P235 MEMBAR !#0 N660 P236 LD 28 -1 Int BE Pri Loop_exit !#0 N661 P1 REPLACEMENT 8 Int BE Pri Loop_entry !#0 N662 P2 LD 33 -1 Int BE Pri !#0 N663 P3 ST 17 0x15 Int BE Pri !#0 N664 P4 MEMBAR !#0 N665 P5 BLD 21 -1 FP BE Pri !#0 N666 P5 BLD 22 -1 FP BE Pri !#A N665 N666 !#0 N667 P5 BLD 23 -1 FP BE Pri !#0 N668 P6 MEMBAR !#0 N669 P7 LD 2 -1 Int BE Pri !#0 N670 P8 MEMBAR !#0 N671 P9 BLD 21 -1 FP BE Pri !#0 N672 P9 BLD 22 -1 FP BE Pri !#A N671 N672 !#0 N673 P9 BLD 23 -1 FP BE Pri !#0 N674 P10 MEMBAR !#0 N675 P11 BST 21 0x3f8000b9 FP BE Pri !#0 N676 P11 BST 22 0x3f8000ba FP BE Pri !#A N675 N676 !#0 N677 P11 BST 23 0x3f8000bb FP BE Pri !#0 N678 P12 MEMBAR !#0 N679 P13 BST 0 0x3f8000bc FP BE Sec !#0 N680 P13 BST 1 0x3f8000bd FP BE Sec !#A N679 N680 !#0 N681 P13 BST 2 0x3f8000be FP BE Sec !#0 N682 P13 BST 3 0x3f8000bf FP BE Sec !#0 N683 P13 BST 4 0x3f8000c0 FP BE Sec !#0 N684 P14 MEMBAR !#0 N685 P15 BSTC 31 0x3f8000c1 FP BE Pri !#0 N686 P16 MEMBAR !#0 N687 P17 BSTC 5 0x3f8000c2 FP BE Pri !#0 N688 P17 BSTC 6 0x3f8000c3 FP BE Pri !#0 N689 P18 MEMBAR !#0 N690 P19 REPLACEMENT 29 Int BE Pri !#0 N691 P20 REPLACEMENT 16 Int BE Pri !#0 N692 P21 MEMBAR !#0 N693 P22 BST 30 0x3f8000c4 FP BE Pri !#0 N694 P23 MEMBAR !#0 N695 P24 REPLACEMENT 25 Int BE Pri !#0 N696 P25 IDC_FLIP 33 Int BE Pri !#0 N697 P26 LD 22 -1 FP BE Pri !#0 N698 P27 ST 17 0x3f8000c5 FP BE Pri !#0 N699 P28 MEMBAR !#0 N700 P29 BLD 0 -1 FP BE Pri !#0 N701 P29 BLD 1 -1 FP BE Pri !#A N700 N701 !#0 N702 P29 BLD 2 -1 FP BE Pri !#0 N703 P29 BLD 3 -1 FP BE Pri !#0 N704 P29 BLD 4 -1 FP BE Pri !#0 N705 P30 MEMBAR !#0 N706 P31 REPLACEMENT 2 Int BE Pri !#0 N707 P32 MEMBAR !#0 N708 P33 BST 18 0x3f8000c6 FP BE Pri !#0 N709 P34 MEMBAR !#0 N710 P35 BST 7 0x3f8000c7 FP BE Pri !#0 N711 P36 MEMBAR !#0 N712 P37 BLD 20 -1 FP BE Pri !#0 N713 P38 MEMBAR !#0 N714 P39 ST 23 0x16 Int BE Pri !#0 N715 P40 IDC_FLIP 8 Int BE Pri !#0 N716 P41 MEMBAR !#0 N717 P42 BSTC 0 0x3f8000c8 FP BE Pri !#0 N718 P42 BSTC 1 0x3f8000c9 FP BE Pri !#A N717 N718 !#0 N719 P42 BSTC 2 0x3f8000ca FP BE Pri !#0 N720 P42 BSTC 3 0x3f8000cb FP BE Pri !#0 N721 P42 BSTC 4 0x3f8000cc FP BE Pri !#0 N722 P43 MEMBAR !#0 N723 P44 BLD 29 -1 FP BE Pri !#0 N724 P45 MEMBAR !#0 N725 P46 BLD 26 -1 FP BE Pri !#0 N726 P46 BLD 27 -1 FP BE Pri !#0 N727 P47 MEMBAR !#0 N728 P48 REPLACEMENT 30 Int BE Pri !#0 N729 P49 MEMBAR !#0 N730 P50 BST 24 0x3f8000cd FP BE Pri !#0 N731 P50 BST 25 0x3f8000ce FP BE Pri !#0 N732 P51 MEMBAR !#0 N733 P52 BSTC 0 0x3f8000cf FP BE Pri !#0 N734 P52 BSTC 1 0x3f8000d0 FP BE Pri !#A N733 N734 !#0 N735 P52 BSTC 2 0x3f8000d1 FP BE Pri !#0 N736 P52 BSTC 3 0x3f8000d2 FP BE Pri !#0 N737 P52 BSTC 4 0x3f8000d3 FP BE Pri !#0 N738 P53 MEMBAR !#0 N739 P54 LD 24 -1 FP BE Pri !#0 N740 P55 MEMBAR !#0 N741 P56 BLD 26 -1 FP BE Pri !#0 N742 P56 BLD 27 -1 FP BE Pri !#0 N743 P57 MEMBAR !#0 N744 P58 REPLACEMENT 28 Int BE Pri !#0 N745 P59 MEMBAR !#0 N746 P60 BLD 21 -1 FP BE Sec !#0 N747 P60 BLD 22 -1 FP BE Sec !#A N746 N747 !#0 N748 P60 BLD 23 -1 FP BE Sec !#0 N749 P61 MEMBAR !#0 N750 P62 BST 0 0x3f8000d4 FP BE Pri !#0 N751 P62 BST 1 0x3f8000d5 FP BE Pri !#A N750 N751 !#0 N752 P62 BST 2 0x3f8000d6 FP BE Pri !#0 N753 P62 BST 3 0x3f8000d7 FP BE Pri !#0 N754 P62 BST 4 0x3f8000d8 FP BE Pri !#0 N755 P63 MEMBAR !#0 N756 P64 LD 31 -1 Int BE Pri !#0 N757 P65 MEMBAR !#0 N758 P66 BLD 0 -1 FP BE Pri !#0 N759 P66 BLD 1 -1 FP BE Pri !#A N758 N759 !#0 N760 P66 BLD 2 -1 FP BE Pri !#0 N761 P66 BLD 3 -1 FP BE Pri !#0 N762 P66 BLD 4 -1 FP BE Pri !#0 N763 P67 MEMBAR !#0 N764 P68 LD 27 -1 Int BE Pri !#0 N765 P69 MEMBAR !#0 N766 P70 BST 11 0x3f8000d9 FP BE Pri !#0 N767 P70 BST 12 0x3f8000da FP BE Pri !#A N766 N767 !#0 N768 P70 BST 13 0x3f8000db FP BE Pri !#0 N769 P71 MEMBAR !#0 N770 P72 BST 8 0x3f8000dc FP BE Pri !#0 N771 P72 BST 9 0x3f8000dd FP BE Pri !#0 N772 P73 MEMBAR !#0 N773 P74 BLD 10 -1 FP BE Pri !#0 N774 P75 MEMBAR !#0 N775 P76 REPLACEMENT 15 Int BE Pri !#0 N776 P77 MEMBAR !#0 N777 P78 BLD 30 -1 FP BE Pri !#0 N778 P79 MEMBAR !#0 N779 P80 LD 32 -1 Int BE Pri !#0 N780 P81 MEMBAR !#0 N781 P82 BLD 0 -1 FP BE Pri !#0 N782 P82 BLD 1 -1 FP BE Pri !#A N781 N782 !#0 N783 P82 BLD 2 -1 FP BE Pri !#0 N784 P82 BLD 3 -1 FP BE Pri !#0 N785 P82 BLD 4 -1 FP BE Pri !#0 N786 P83 MEMBAR !#0 N787 P84 BLD 7 -1 FP BE Pri !#0 N788 P85 MEMBAR !#0 N789 P86 REPLACEMENT 18 Int BE Pri !#0 N790 P87 LD 6 -1 FP BE Pri !#0 N791 P88 MEMBAR !#0 N792 P89 BLD 21 -1 FP BE Pri !#0 N793 P89 BLD 22 -1 FP BE Pri !#A N792 N793 !#0 N794 P89 BLD 23 -1 FP BE Pri !#0 N795 P90 MEMBAR !#0 N796 P91 BSTC 0 0x3f8000de FP BE Pri !#0 N797 P91 BSTC 1 0x3f8000df FP BE Pri !#A N796 N797 !#0 N798 P91 BSTC 2 0x3f8000e0 FP BE Pri !#0 N799 P91 BSTC 3 0x3f8000e1 FP BE Pri !#0 N800 P91 BSTC 4 0x3f8000e2 FP BE Pri !#0 N801 P92 MEMBAR !#0 N802 P93 BSTC 0 0x3f8000e3 FP BE Sec !#0 N803 P93 BSTC 1 0x3f8000e4 FP BE Sec !#A N802 N803 !#0 N804 P93 BSTC 2 0x3f8000e5 FP BE Sec !#0 N805 P93 BSTC 3 0x3f8000e6 FP BE Sec !#0 N806 P93 BSTC 4 0x3f8000e7 FP BE Sec !#0 N807 P94 MEMBAR !#0 N808 P95 PREFETCH 14 Int LE Pri !#0 N809 P96 LD 18 -1 FP BE Pri !#0 N810 P97 LD 27 -1 FP BE Pri !#0 N811 P98 ST 32 0x17 Int BE Pri !#0 N812 P99 IDC_FLIP 31 Int BE Pri !#0 N813 P100 MEMBAR !#0 N814 P101 BLD 26 -1 FP BE Pri !#0 N815 P101 BLD 27 -1 FP BE Pri !#0 N816 P102 MEMBAR !#0 N817 P103 IDC_FLIP 7 Int BE Pri !#0 N818 P104 IDC_FLIP 17 Int BE Pri !#0 N819 P105 MEMBAR !#0 N820 P106 BSTC 29 0x3f8000e8 FP BE Sec !#0 N821 P107 MEMBAR !#0 N822 P108 REPLACEMENT 29 Int BE Pri !#0 N823 P109 PREFETCH 33 Int BE Pri !#0 N824 P110 REPLACEMENT 29 Int BE Pri !#0 N825 P111 MEMBAR !#0 N826 P112 BST 21 0x3f8000e9 FP BE Pri !#0 N827 P112 BST 22 0x3f8000ea FP BE Pri !#A N826 N827 !#0 N828 P112 BST 23 0x3f8000eb FP BE Pri !#0 N829 P113 MEMBAR !#0 N830 P114 REPLACEMENT 12 Int BE Pri !#0 N831 P115 MEMBAR !#0 N832 P116 BST 0 0x3f8000ec FP BE Pri !#0 N833 P116 BST 1 0x3f8000ed FP BE Pri !#A N832 N833 !#0 N834 P116 BST 2 0x3f8000ee FP BE Pri !#0 N835 P116 BST 3 0x3f8000ef FP BE Pri !#0 N836 P116 BST 4 0x3f8000f0 FP BE Pri !#0 N837 P117 MEMBAR !#0 N838 P118 REPLACEMENT 9 Int BE Pri !#0 N839 P119 ST 8 0x3f8000f1 FP BE Sec !#0 N840 P120 PREFETCH 12 Int BE Pri !#0 N841 P121 MEMBAR !#0 N842 P122 BLD 32 -1 FP BE Pri !#0 N843 P123 MEMBAR !#0 N844 P124 IDC_FLIP 11 Int BE Pri !#0 N845 P125 LD 2 -1 FP BE Pri !#0 N846 P126 ST 24 0x18 Int BE Pri !#0 N847 P127 LD 27 -1 Int BE Pri !#0 N848 P128 MEMBAR !#0 N849 P129 BLD 24 -1 FP BE Pri !#0 N850 P129 BLD 25 -1 FP BE Pri !#0 N851 P130 MEMBAR !#0 N852 P131 BST 11 0x3f8000f2 FP BE Pri !#0 N853 P131 BST 12 0x3f8000f3 FP BE Pri !#A N852 N853 !#0 N854 P131 BST 13 0x3f8000f4 FP BE Pri !#0 N855 P132 MEMBAR !#0 N856 P133 REPLACEMENT 11 Int BE Pri !#0 N857 P134 ST 12 0x19 Int BE Pri !#0 N858 P135 PREFETCH 4 Int LE Pri !#0 N859 P136 MEMBAR !#0 N860 P137 BSTC 20 0x3f8000f5 FP BE Pri !#0 N861 P138 MEMBAR !#0 N862 P139 LD 20 -1 Int BE Nuc !#0 N863 P140 MEMBAR !#0 N864 P141 BSTC 7 0x3f8000f6 FP BE Pri !#0 N865 P142 MEMBAR !#0 N866 P143 BSTC 19 0x3f8000f7 FP BE Pri !#0 N867 P144 MEMBAR !#0 N868 P145 BLD 8 -1 FP BE Pri !#0 N869 P145 BLD 9 -1 FP BE Pri !#0 N870 P146 MEMBAR !#0 N871 P147 BSTC 11 0x3f8000f8 FP BE Pri !#0 N872 P147 BSTC 12 0x3f8000f9 FP BE Pri !#A N871 N872 !#0 N873 P147 BSTC 13 0x3f8000fa FP BE Pri !#0 N874 P148 MEMBAR !#0 N875 P149 PREFETCH 26 Int BE Pri !#0 N876 P150 MEMBAR !#0 N877 P151 BLD 16 -1 FP BE Pri !#0 N878 P152 MEMBAR !#0 N879 P153 REPLACEMENT 17 Int BE Sec !#0 N880 P154 LD 12 -1 FP BE Sec !#0 N881 P155 MEMBAR !#0 N882 P156 BST 8 0x3f8000fb FP BE Sec !#0 N883 P156 BST 9 0x3f8000fc FP BE Sec !#0 N884 P157 MEMBAR !#0 N885 P158 BST 29 0x3f8000fd FP BE Pri !#0 N886 P159 MEMBAR !#0 N887 P160 BSTC 0 0x3f8000fe FP BE Pri !#0 N888 P160 BSTC 1 0x3f8000ff FP BE Pri !#A N887 N888 !#0 N889 P160 BSTC 2 0x3f800100 FP BE Pri !#0 N890 P160 BSTC 3 0x3f800101 FP BE Pri !#0 N891 P160 BSTC 4 0x3f800102 FP BE Pri !#0 N892 P161 MEMBAR !#0 N893 P162 PREFETCH 7 Int BE Pri !#0 N894 P163 MEMBAR !#0 N895 P164 BLD 15 -1 FP BE Sec !#0 N896 P165 MEMBAR !#0 N897 P166 BLD 33 -1 FP BE Pri !#0 N898 P167 MEMBAR !#0 N899 P168 ST 27 0x1a Int BE Pri !#0 N900 P169 PREFETCH 21 Int BE Pri !#0 N901 P170 LD 14 -1 Int BE Pri !#0 N902 P171 MEMBAR !#0 N903 P172 BST 5 0x3f800103 FP BE Pri !#0 N904 P172 BST 6 0x3f800104 FP BE Pri !#0 N905 P173 MEMBAR !#0 N906 P174 ST 33 0x1b Int LE Nuc !#0 N907 P175 MEMBAR !#0 N908 P176 BLD 21 -1 FP BE Pri !#0 N909 P176 BLD 22 -1 FP BE Pri !#A N908 N909 !#0 N910 P176 BLD 23 -1 FP BE Pri !#0 N911 P177 MEMBAR !#0 N912 P178 BLD 0 -1 FP BE Pri !#0 N913 P178 BLD 1 -1 FP BE Pri !#A N912 N913 !#0 N914 P178 BLD 2 -1 FP BE Pri !#0 N915 P178 BLD 3 -1 FP BE Pri !#0 N916 P178 BLD 4 -1 FP BE Pri !#0 N917 P179 MEMBAR !#0 N918 P180 BLD 21 -1 FP BE Sec !#0 N919 P180 BLD 22 -1 FP BE Sec !#A N918 N919 !#0 N920 P180 BLD 23 -1 FP BE Sec !#0 N921 P181 MEMBAR !#0 N922 P182 LD 17 -1 FP BE Pri !#0 N923 P183 LD 18 -1 FP BE Nuc !#0 N924 P184 MEMBAR !#0 N925 P185 BLD 20 -1 FP BE Pri !#0 N926 P186 MEMBAR !#0 N927 P187 REPLACEMENT 5 Int BE Pri !#0 N928 P188 MEMBAR !#0 N929 P189 BLD 11 -1 FP BE Pri !#0 N930 P189 BLD 12 -1 FP BE Pri !#A N929 N930 !#0 N931 P189 BLD 13 -1 FP BE Pri !#0 N932 P190 MEMBAR !#0 N933 P191 REPLACEMENT 28 Int BE Sec !#0 N934 P192 PREFETCH 4 Int BE Nuc !#0 N935 P193 PREFETCH 21 Int BE Sec !#0 N936 P194 ST 24 0x3f800105 FP BE Pri !#0 N937 P195 ST 5 0x1c Int LE Pri !#0 N938 P196 FLUSHI 0 Int BE Pri !#0 N939 P197 ST 4 0x1d Int BE Pri !#0 N940 P198 REPLACEMENT 32 Int BE Pri !#0 N941 P199 MEMBAR !#0 N942 P200 BSTC 21 0x3f800106 FP BE Pri !#0 N943 P200 BSTC 22 0x3f800107 FP BE Pri !#A N942 N943 !#0 N944 P200 BSTC 23 0x3f800108 FP BE Pri !#0 N945 P201 MEMBAR !#0 N946 P202 BST 10 0x3f800109 FP BE Pri !#0 N947 P203 MEMBAR !#0 N948 P204 ST 28 0x3f80010a FP BE Pri !#0 N949 P205 MEMBAR !#0 N950 P206 BLD 0 -1 FP BE Pri !#0 N951 P206 BLD 1 -1 FP BE Pri !#A N950 N951 !#0 N952 P206 BLD 2 -1 FP BE Pri !#0 N953 P206 BLD 3 -1 FP BE Pri !#0 N954 P206 BLD 4 -1 FP BE Pri !#0 N955 P207 MEMBAR !#0 N956 P208 ST 7 0x1e Int BE Pri !#0 N957 P209 MEMBAR !#0 N958 P210 BST 15 0x3f80010b FP BE Pri !#0 N959 P211 MEMBAR !#0 N960 P212 REPLACEMENT 1 Int BE Pri !#0 N961 P213 MEMBAR !#0 N962 P214 BLD 14 -1 FP BE Pri !#0 N963 P215 MEMBAR !#0 N964 P216 BSTC 33 0x3f80010c FP BE Pri !#0 N965 P217 MEMBAR !#0 N966 P218 BSTC 0 0x3f80010d FP BE Pri !#0 N967 P218 BSTC 1 0x3f80010e FP BE Pri !#A N966 N967 !#0 N968 P218 BSTC 2 0x3f80010f FP BE Pri !#0 N969 P218 BSTC 3 0x3f800110 FP BE Pri !#0 N970 P218 BSTC 4 0x3f800111 FP BE Pri !#0 N971 P219 MEMBAR !#0 N972 P220 ST 19 0x3f800112 FP BE Pri !#0 N973 P221 MEMBAR !#0 N974 P222 BST 10 0x3f800113 FP BE Pri !#0 N975 P223 MEMBAR !#0 N976 P224 REPLACEMENT 21 Int BE Pri !#0 N977 P225 MEMBAR !#0 N978 P226 BLD 5 -1 FP BE Pri !#0 N979 P226 BLD 6 -1 FP BE Pri !#0 N980 P227 MEMBAR !#0 N981 P228 BLD 26 -1 FP BE Pri !#0 N982 P228 BLD 27 -1 FP BE Pri !#0 N983 P229 MEMBAR !#0 N984 P230 LD 22 -1 Int BE Sec !#0 N985 P231 MEMBAR !#0 N986 P232 BLD 33 -1 FP BE Pri !#0 N987 P233 MEMBAR !#0 N988 P234 BST 7 0x3f800114 FP BE Pri !#0 N989 P235 MEMBAR !#0 N990 P236 LD 28 -1 Int BE Pri Loop_exit !#0 N991 P1 REPLACEMENT 8 Int BE Pri Loop_entry !#0 N992 P2 LD 33 -1 Int BE Pri !#0 N993 P3 ST 17 0x1f Int BE Pri !#0 N994 P4 MEMBAR !#0 N995 P5 BLD 21 -1 FP BE Pri !#0 N996 P5 BLD 22 -1 FP BE Pri !#A N995 N996 !#0 N997 P5 BLD 23 -1 FP BE Pri !#0 N998 P6 MEMBAR !#0 N999 P7 LD 2 -1 Int BE Pri !#0 N1000 P8 MEMBAR !#0 N1001 P9 BLD 21 -1 FP BE Pri !#0 N1002 P9 BLD 22 -1 FP BE Pri !#A N1001 N1002 !#0 N1003 P9 BLD 23 -1 FP BE Pri !#0 N1004 P10 MEMBAR !#0 N1005 P11 BST 21 0x3f800115 FP BE Pri !#0 N1006 P11 BST 22 0x3f800116 FP BE Pri !#A N1005 N1006 !#0 N1007 P11 BST 23 0x3f800117 FP BE Pri !#0 N1008 P12 MEMBAR !#0 N1009 P13 BST 0 0x3f800118 FP BE Sec !#0 N1010 P13 BST 1 0x3f800119 FP BE Sec !#A N1009 N1010 !#0 N1011 P13 BST 2 0x3f80011a FP BE Sec !#0 N1012 P13 BST 3 0x3f80011b FP BE Sec !#0 N1013 P13 BST 4 0x3f80011c FP BE Sec !#0 N1014 P14 MEMBAR !#0 N1015 P15 BSTC 31 0x3f80011d FP BE Pri !#0 N1016 P16 MEMBAR !#0 N1017 P17 BSTC 5 0x3f80011e FP BE Pri !#0 N1018 P17 BSTC 6 0x3f80011f FP BE Pri !#0 N1019 P18 MEMBAR !#0 N1020 P19 REPLACEMENT 29 Int BE Pri !#0 N1021 P20 REPLACEMENT 16 Int BE Pri !#0 N1022 P21 MEMBAR !#0 N1023 P22 BST 30 0x3f800120 FP BE Pri !#0 N1024 P23 MEMBAR !#0 N1025 P24 REPLACEMENT 25 Int BE Pri !#0 N1026 P25 IDC_FLIP 33 Int BE Pri !#0 N1027 P26 LD 22 -1 FP BE Pri !#0 N1028 P27 ST 17 0x3f800121 FP BE Pri !#0 N1029 P28 MEMBAR !#0 N1030 P29 BLD 0 -1 FP BE Pri !#0 N1031 P29 BLD 1 -1 FP BE Pri !#A N1030 N1031 !#0 N1032 P29 BLD 2 -1 FP BE Pri !#0 N1033 P29 BLD 3 -1 FP BE Pri !#0 N1034 P29 BLD 4 -1 FP BE Pri !#0 N1035 P30 MEMBAR !#0 N1036 P31 REPLACEMENT 2 Int BE Pri !#0 N1037 P32 MEMBAR !#0 N1038 P33 BST 18 0x3f800122 FP BE Pri !#0 N1039 P34 MEMBAR !#0 N1040 P35 BST 7 0x3f800123 FP BE Pri !#0 N1041 P36 MEMBAR !#0 N1042 P37 BLD 20 -1 FP BE Pri !#0 N1043 P38 MEMBAR !#0 N1044 P39 ST 23 0x20 Int BE Pri !#0 N1045 P40 IDC_FLIP 8 Int BE Pri !#0 N1046 P41 MEMBAR !#0 N1047 P42 BSTC 0 0x3f800124 FP BE Pri !#0 N1048 P42 BSTC 1 0x3f800125 FP BE Pri !#A N1047 N1048 !#0 N1049 P42 BSTC 2 0x3f800126 FP BE Pri !#0 N1050 P42 BSTC 3 0x3f800127 FP BE Pri !#0 N1051 P42 BSTC 4 0x3f800128 FP BE Pri !#0 N1052 P43 MEMBAR !#0 N1053 P44 BLD 29 -1 FP BE Pri !#0 N1054 P45 MEMBAR !#0 N1055 P46 BLD 26 -1 FP BE Pri !#0 N1056 P46 BLD 27 -1 FP BE Pri !#0 N1057 P47 MEMBAR !#0 N1058 P48 REPLACEMENT 30 Int BE Pri !#0 N1059 P49 MEMBAR !#0 N1060 P50 BST 24 0x3f800129 FP BE Pri !#0 N1061 P50 BST 25 0x3f80012a FP BE Pri !#0 N1062 P51 MEMBAR !#0 N1063 P52 BSTC 0 0x3f80012b FP BE Pri !#0 N1064 P52 BSTC 1 0x3f80012c FP BE Pri !#A N1063 N1064 !#0 N1065 P52 BSTC 2 0x3f80012d FP BE Pri !#0 N1066 P52 BSTC 3 0x3f80012e FP BE Pri !#0 N1067 P52 BSTC 4 0x3f80012f FP BE Pri !#0 N1068 P53 MEMBAR !#0 N1069 P54 LD 24 -1 FP BE Pri !#0 N1070 P55 MEMBAR !#0 N1071 P56 BLD 26 -1 FP BE Pri !#0 N1072 P56 BLD 27 -1 FP BE Pri !#0 N1073 P57 MEMBAR !#0 N1074 P58 REPLACEMENT 28 Int BE Pri !#0 N1075 P59 MEMBAR !#0 N1076 P60 BLD 21 -1 FP BE Sec !#0 N1077 P60 BLD 22 -1 FP BE Sec !#A N1076 N1077 !#0 N1078 P60 BLD 23 -1 FP BE Sec !#0 N1079 P61 MEMBAR !#0 N1080 P62 BST 0 0x3f800130 FP BE Pri !#0 N1081 P62 BST 1 0x3f800131 FP BE Pri !#A N1080 N1081 !#0 N1082 P62 BST 2 0x3f800132 FP BE Pri !#0 N1083 P62 BST 3 0x3f800133 FP BE Pri !#0 N1084 P62 BST 4 0x3f800134 FP BE Pri !#0 N1085 P63 MEMBAR !#0 N1086 P64 LD 31 -1 Int BE Pri !#0 N1087 P65 MEMBAR !#0 N1088 P66 BLD 0 -1 FP BE Pri !#0 N1089 P66 BLD 1 -1 FP BE Pri !#A N1088 N1089 !#0 N1090 P66 BLD 2 -1 FP BE Pri !#0 N1091 P66 BLD 3 -1 FP BE Pri !#0 N1092 P66 BLD 4 -1 FP BE Pri !#0 N1093 P67 MEMBAR !#0 N1094 P68 LD 27 -1 Int BE Pri !#0 N1095 P69 MEMBAR !#0 N1096 P70 BST 11 0x3f800135 FP BE Pri !#0 N1097 P70 BST 12 0x3f800136 FP BE Pri !#A N1096 N1097 !#0 N1098 P70 BST 13 0x3f800137 FP BE Pri !#0 N1099 P71 MEMBAR !#0 N1100 P72 BST 8 0x3f800138 FP BE Pri !#0 N1101 P72 BST 9 0x3f800139 FP BE Pri !#0 N1102 P73 MEMBAR !#0 N1103 P74 BLD 10 -1 FP BE Pri !#0 N1104 P75 MEMBAR !#0 N1105 P76 REPLACEMENT 15 Int BE Pri !#0 N1106 P77 MEMBAR !#0 N1107 P78 BLD 30 -1 FP BE Pri !#0 N1108 P79 MEMBAR !#0 N1109 P80 LD 32 -1 Int BE Pri !#0 N1110 P81 MEMBAR !#0 N1111 P82 BLD 0 -1 FP BE Pri !#0 N1112 P82 BLD 1 -1 FP BE Pri !#A N1111 N1112 !#0 N1113 P82 BLD 2 -1 FP BE Pri !#0 N1114 P82 BLD 3 -1 FP BE Pri !#0 N1115 P82 BLD 4 -1 FP BE Pri !#0 N1116 P83 MEMBAR !#0 N1117 P84 BLD 7 -1 FP BE Pri !#0 N1118 P85 MEMBAR !#0 N1119 P86 REPLACEMENT 18 Int BE Pri !#0 N1120 P87 LD 6 -1 FP BE Pri !#0 N1121 P88 MEMBAR !#0 N1122 P89 BLD 21 -1 FP BE Pri !#0 N1123 P89 BLD 22 -1 FP BE Pri !#A N1122 N1123 !#0 N1124 P89 BLD 23 -1 FP BE Pri !#0 N1125 P90 MEMBAR !#0 N1126 P91 BSTC 0 0x3f80013a FP BE Pri !#0 N1127 P91 BSTC 1 0x3f80013b FP BE Pri !#A N1126 N1127 !#0 N1128 P91 BSTC 2 0x3f80013c FP BE Pri !#0 N1129 P91 BSTC 3 0x3f80013d FP BE Pri !#0 N1130 P91 BSTC 4 0x3f80013e FP BE Pri !#0 N1131 P92 MEMBAR !#0 N1132 P93 BSTC 0 0x3f80013f FP BE Sec !#0 N1133 P93 BSTC 1 0x3f800140 FP BE Sec !#A N1132 N1133 !#0 N1134 P93 BSTC 2 0x3f800141 FP BE Sec !#0 N1135 P93 BSTC 3 0x3f800142 FP BE Sec !#0 N1136 P93 BSTC 4 0x3f800143 FP BE Sec !#0 N1137 P94 MEMBAR !#0 N1138 P95 PREFETCH 14 Int LE Pri !#0 N1139 P96 LD 18 -1 FP BE Pri !#0 N1140 P97 LD 27 -1 FP BE Pri !#0 N1141 P98 ST 32 0x21 Int BE Pri !#0 N1142 P99 IDC_FLIP 31 Int BE Pri !#0 N1143 P100 MEMBAR !#0 N1144 P101 BLD 26 -1 FP BE Pri !#0 N1145 P101 BLD 27 -1 FP BE Pri !#0 N1146 P102 MEMBAR !#0 N1147 P103 IDC_FLIP 7 Int BE Pri !#0 N1148 P104 IDC_FLIP 17 Int BE Pri !#0 N1149 P105 MEMBAR !#0 N1150 P106 BSTC 29 0x3f800144 FP BE Sec !#0 N1151 P107 MEMBAR !#0 N1152 P108 REPLACEMENT 29 Int BE Pri !#0 N1153 P109 PREFETCH 33 Int BE Pri !#0 N1154 P110 REPLACEMENT 29 Int BE Pri !#0 N1155 P111 MEMBAR !#0 N1156 P112 BST 21 0x3f800145 FP BE Pri !#0 N1157 P112 BST 22 0x3f800146 FP BE Pri !#A N1156 N1157 !#0 N1158 P112 BST 23 0x3f800147 FP BE Pri !#0 N1159 P113 MEMBAR !#0 N1160 P114 REPLACEMENT 12 Int BE Pri !#0 N1161 P115 MEMBAR !#0 N1162 P116 BST 0 0x3f800148 FP BE Pri !#0 N1163 P116 BST 1 0x3f800149 FP BE Pri !#A N1162 N1163 !#0 N1164 P116 BST 2 0x3f80014a FP BE Pri !#0 N1165 P116 BST 3 0x3f80014b FP BE Pri !#0 N1166 P116 BST 4 0x3f80014c FP BE Pri !#0 N1167 P117 MEMBAR !#0 N1168 P118 REPLACEMENT 9 Int BE Pri !#0 N1169 P119 ST 8 0x3f80014d FP BE Sec !#0 N1170 P120 PREFETCH 12 Int BE Pri !#0 N1171 P121 MEMBAR !#0 N1172 P122 BLD 32 -1 FP BE Pri !#0 N1173 P123 MEMBAR !#0 N1174 P124 IDC_FLIP 11 Int BE Pri !#0 N1175 P125 LD 2 -1 FP BE Pri !#0 N1176 P126 ST 24 0x22 Int BE Pri !#0 N1177 P127 LD 27 -1 Int BE Pri !#0 N1178 P128 MEMBAR !#0 N1179 P129 BLD 24 -1 FP BE Pri !#0 N1180 P129 BLD 25 -1 FP BE Pri !#0 N1181 P130 MEMBAR !#0 N1182 P131 BST 11 0x3f80014e FP BE Pri !#0 N1183 P131 BST 12 0x3f80014f FP BE Pri !#A N1182 N1183 !#0 N1184 P131 BST 13 0x3f800150 FP BE Pri !#0 N1185 P132 MEMBAR !#0 N1186 P133 REPLACEMENT 11 Int BE Pri !#0 N1187 P134 ST 12 0x23 Int BE Pri !#0 N1188 P135 PREFETCH 4 Int LE Pri !#0 N1189 P136 MEMBAR !#0 N1190 P137 BSTC 20 0x3f800151 FP BE Pri !#0 N1191 P138 MEMBAR !#0 N1192 P139 LD 20 -1 Int BE Nuc !#0 N1193 P140 MEMBAR !#0 N1194 P141 BSTC 7 0x3f800152 FP BE Pri !#0 N1195 P142 MEMBAR !#0 N1196 P143 BSTC 19 0x3f800153 FP BE Pri !#0 N1197 P144 MEMBAR !#0 N1198 P145 BLD 8 -1 FP BE Pri !#0 N1199 P145 BLD 9 -1 FP BE Pri !#0 N1200 P146 MEMBAR !#0 N1201 P147 BSTC 11 0x3f800154 FP BE Pri !#0 N1202 P147 BSTC 12 0x3f800155 FP BE Pri !#A N1201 N1202 !#0 N1203 P147 BSTC 13 0x3f800156 FP BE Pri !#0 N1204 P148 MEMBAR !#0 N1205 P149 PREFETCH 26 Int BE Pri !#0 N1206 P150 MEMBAR !#0 N1207 P151 BLD 16 -1 FP BE Pri !#0 N1208 P152 MEMBAR !#0 N1209 P153 REPLACEMENT 17 Int BE Sec !#0 N1210 P154 LD 12 -1 FP BE Sec !#0 N1211 P155 MEMBAR !#0 N1212 P156 BST 8 0x3f800157 FP BE Sec !#0 N1213 P156 BST 9 0x3f800158 FP BE Sec !#0 N1214 P157 MEMBAR !#0 N1215 P158 BST 29 0x3f800159 FP BE Pri !#0 N1216 P159 MEMBAR !#0 N1217 P160 BSTC 0 0x3f80015a FP BE Pri !#0 N1218 P160 BSTC 1 0x3f80015b FP BE Pri !#A N1217 N1218 !#0 N1219 P160 BSTC 2 0x3f80015c FP BE Pri !#0 N1220 P160 BSTC 3 0x3f80015d FP BE Pri !#0 N1221 P160 BSTC 4 0x3f80015e FP BE Pri !#0 N1222 P161 MEMBAR !#0 N1223 P162 PREFETCH 7 Int BE Pri !#0 N1224 P163 MEMBAR !#0 N1225 P164 BLD 15 -1 FP BE Sec !#0 N1226 P165 MEMBAR !#0 N1227 P166 BLD 33 -1 FP BE Pri !#0 N1228 P167 MEMBAR !#0 N1229 P168 ST 27 0x24 Int BE Pri !#0 N1230 P169 PREFETCH 21 Int BE Pri !#0 N1231 P170 LD 14 -1 Int BE Pri !#0 N1232 P171 MEMBAR !#0 N1233 P172 BST 5 0x3f80015f FP BE Pri !#0 N1234 P172 BST 6 0x3f800160 FP BE Pri !#0 N1235 P173 MEMBAR !#0 N1236 P174 ST 33 0x25 Int LE Nuc !#0 N1237 P175 MEMBAR !#0 N1238 P176 BLD 21 -1 FP BE Pri !#0 N1239 P176 BLD 22 -1 FP BE Pri !#A N1238 N1239 !#0 N1240 P176 BLD 23 -1 FP BE Pri !#0 N1241 P177 MEMBAR !#0 N1242 P178 BLD 0 -1 FP BE Pri !#0 N1243 P178 BLD 1 -1 FP BE Pri !#A N1242 N1243 !#0 N1244 P178 BLD 2 -1 FP BE Pri !#0 N1245 P178 BLD 3 -1 FP BE Pri !#0 N1246 P178 BLD 4 -1 FP BE Pri !#0 N1247 P179 MEMBAR !#0 N1248 P180 BLD 21 -1 FP BE Sec !#0 N1249 P180 BLD 22 -1 FP BE Sec !#A N1248 N1249 !#0 N1250 P180 BLD 23 -1 FP BE Sec !#0 N1251 P181 MEMBAR !#0 N1252 P182 LD 17 -1 FP BE Pri !#0 N1253 P183 LD 18 -1 FP BE Nuc !#0 N1254 P184 MEMBAR !#0 N1255 P185 BLD 20 -1 FP BE Pri !#0 N1256 P186 MEMBAR !#0 N1257 P187 REPLACEMENT 5 Int BE Pri !#0 N1258 P188 MEMBAR !#0 N1259 P189 BLD 11 -1 FP BE Pri !#0 N1260 P189 BLD 12 -1 FP BE Pri !#A N1259 N1260 !#0 N1261 P189 BLD 13 -1 FP BE Pri !#0 N1262 P190 MEMBAR !#0 N1263 P191 REPLACEMENT 28 Int BE Sec !#0 N1264 P192 PREFETCH 4 Int BE Nuc !#0 N1265 P193 PREFETCH 21 Int BE Sec !#0 N1266 P194 ST 24 0x3f800161 FP BE Pri !#0 N1267 P195 ST 5 0x26 Int LE Pri !#0 N1268 P196 FLUSHI 0 Int BE Pri !#0 N1269 P197 ST 4 0x27 Int BE Pri !#0 N1270 P198 REPLACEMENT 32 Int BE Pri !#0 N1271 P199 MEMBAR !#0 N1272 P200 BSTC 21 0x3f800162 FP BE Pri !#0 N1273 P200 BSTC 22 0x3f800163 FP BE Pri !#A N1272 N1273 !#0 N1274 P200 BSTC 23 0x3f800164 FP BE Pri !#0 N1275 P201 MEMBAR !#0 N1276 P202 BST 10 0x3f800165 FP BE Pri !#0 N1277 P203 MEMBAR !#0 N1278 P204 ST 28 0x3f800166 FP BE Pri !#0 N1279 P205 MEMBAR !#0 N1280 P206 BLD 0 -1 FP BE Pri !#0 N1281 P206 BLD 1 -1 FP BE Pri !#A N1280 N1281 !#0 N1282 P206 BLD 2 -1 FP BE Pri !#0 N1283 P206 BLD 3 -1 FP BE Pri !#0 N1284 P206 BLD 4 -1 FP BE Pri !#0 N1285 P207 MEMBAR !#0 N1286 P208 ST 7 0x28 Int BE Pri !#0 N1287 P209 MEMBAR !#0 N1288 P210 BST 15 0x3f800167 FP BE Pri !#0 N1289 P211 MEMBAR !#0 N1290 P212 REPLACEMENT 1 Int BE Pri !#0 N1291 P213 MEMBAR !#0 N1292 P214 BLD 14 -1 FP BE Pri !#0 N1293 P215 MEMBAR !#0 N1294 P216 BSTC 33 0x3f800168 FP BE Pri !#0 N1295 P217 MEMBAR !#0 N1296 P218 BSTC 0 0x3f800169 FP BE Pri !#0 N1297 P218 BSTC 1 0x3f80016a FP BE Pri !#A N1296 N1297 !#0 N1298 P218 BSTC 2 0x3f80016b FP BE Pri !#0 N1299 P218 BSTC 3 0x3f80016c FP BE Pri !#0 N1300 P218 BSTC 4 0x3f80016d FP BE Pri !#0 N1301 P219 MEMBAR !#0 N1302 P220 ST 19 0x3f80016e FP BE Pri !#0 N1303 P221 MEMBAR !#0 N1304 P222 BST 10 0x3f80016f FP BE Pri !#0 N1305 P223 MEMBAR !#0 N1306 P224 REPLACEMENT 21 Int BE Pri !#0 N1307 P225 MEMBAR !#0 N1308 P226 BLD 5 -1 FP BE Pri !#0 N1309 P226 BLD 6 -1 FP BE Pri !#0 N1310 P227 MEMBAR !#0 N1311 P228 BLD 26 -1 FP BE Pri !#0 N1312 P228 BLD 27 -1 FP BE Pri !#0 N1313 P229 MEMBAR !#0 N1314 P230 LD 22 -1 Int BE Sec !#0 N1315 P231 MEMBAR !#0 N1316 P232 BLD 33 -1 FP BE Pri !#0 N1317 P233 MEMBAR !#0 N1318 P234 BST 7 0x3f800170 FP BE Pri !#0 N1319 P235 MEMBAR !#0 N1320 P236 LD 28 -1 Int BE Pri Loop_exit !#0 N1321 P1 REPLACEMENT 8 Int BE Pri Loop_entry !#0 N1322 P2 LD 33 -1 Int BE Pri !#0 N1323 P3 ST 17 0x29 Int BE Pri !#0 N1324 P4 MEMBAR !#0 N1325 P5 BLD 21 -1 FP BE Pri !#0 N1326 P5 BLD 22 -1 FP BE Pri !#A N1325 N1326 !#0 N1327 P5 BLD 23 -1 FP BE Pri !#0 N1328 P6 MEMBAR !#0 N1329 P7 LD 2 -1 Int BE Pri !#0 N1330 P8 MEMBAR !#0 N1331 P9 BLD 21 -1 FP BE Pri !#0 N1332 P9 BLD 22 -1 FP BE Pri !#A N1331 N1332 !#0 N1333 P9 BLD 23 -1 FP BE Pri !#0 N1334 P10 MEMBAR !#0 N1335 P11 BST 21 0x3f800171 FP BE Pri !#0 N1336 P11 BST 22 0x3f800172 FP BE Pri !#A N1335 N1336 !#0 N1337 P11 BST 23 0x3f800173 FP BE Pri !#0 N1338 P12 MEMBAR !#0 N1339 P13 BST 0 0x3f800174 FP BE Sec !#0 N1340 P13 BST 1 0x3f800175 FP BE Sec !#A N1339 N1340 !#0 N1341 P13 BST 2 0x3f800176 FP BE Sec !#0 N1342 P13 BST 3 0x3f800177 FP BE Sec !#0 N1343 P13 BST 4 0x3f800178 FP BE Sec !#0 N1344 P14 MEMBAR !#0 N1345 P15 BSTC 31 0x3f800179 FP BE Pri !#0 N1346 P16 MEMBAR !#0 N1347 P17 BSTC 5 0x3f80017a FP BE Pri !#0 N1348 P17 BSTC 6 0x3f80017b FP BE Pri !#0 N1349 P18 MEMBAR !#0 N1350 P19 REPLACEMENT 29 Int BE Pri !#0 N1351 P20 REPLACEMENT 16 Int BE Pri !#0 N1352 P21 MEMBAR !#0 N1353 P22 BST 30 0x3f80017c FP BE Pri !#0 N1354 P23 MEMBAR !#0 N1355 P24 REPLACEMENT 25 Int BE Pri !#0 N1356 P25 IDC_FLIP 33 Int BE Pri !#0 N1357 P26 LD 22 -1 FP BE Pri !#0 N1358 P27 ST 17 0x3f80017d FP BE Pri !#0 N1359 P28 MEMBAR !#0 N1360 P29 BLD 0 -1 FP BE Pri !#0 N1361 P29 BLD 1 -1 FP BE Pri !#A N1360 N1361 !#0 N1362 P29 BLD 2 -1 FP BE Pri !#0 N1363 P29 BLD 3 -1 FP BE Pri !#0 N1364 P29 BLD 4 -1 FP BE Pri !#0 N1365 P30 MEMBAR !#0 N1366 P31 REPLACEMENT 2 Int BE Pri !#0 N1367 P32 MEMBAR !#0 N1368 P33 BST 18 0x3f80017e FP BE Pri !#0 N1369 P34 MEMBAR !#0 N1370 P35 BST 7 0x3f80017f FP BE Pri !#0 N1371 P36 MEMBAR !#0 N1372 P37 BLD 20 -1 FP BE Pri !#0 N1373 P38 MEMBAR !#0 N1374 P39 ST 23 0x2a Int BE Pri !#0 N1375 P40 IDC_FLIP 8 Int BE Pri !#0 N1376 P41 MEMBAR !#0 N1377 P42 BSTC 0 0x3f800180 FP BE Pri !#0 N1378 P42 BSTC 1 0x3f800181 FP BE Pri !#A N1377 N1378 !#0 N1379 P42 BSTC 2 0x3f800182 FP BE Pri !#0 N1380 P42 BSTC 3 0x3f800183 FP BE Pri !#0 N1381 P42 BSTC 4 0x3f800184 FP BE Pri !#0 N1382 P43 MEMBAR !#0 N1383 P44 BLD 29 -1 FP BE Pri !#0 N1384 P45 MEMBAR !#0 N1385 P46 BLD 26 -1 FP BE Pri !#0 N1386 P46 BLD 27 -1 FP BE Pri !#0 N1387 P47 MEMBAR !#0 N1388 P48 REPLACEMENT 30 Int BE Pri !#0 N1389 P49 MEMBAR !#0 N1390 P50 BST 24 0x3f800185 FP BE Pri !#0 N1391 P50 BST 25 0x3f800186 FP BE Pri !#0 N1392 P51 MEMBAR !#0 N1393 P52 BSTC 0 0x3f800187 FP BE Pri !#0 N1394 P52 BSTC 1 0x3f800188 FP BE Pri !#A N1393 N1394 !#0 N1395 P52 BSTC 2 0x3f800189 FP BE Pri !#0 N1396 P52 BSTC 3 0x3f80018a FP BE Pri !#0 N1397 P52 BSTC 4 0x3f80018b FP BE Pri !#0 N1398 P53 MEMBAR !#0 N1399 P54 LD 24 -1 FP BE Pri !#0 N1400 P55 MEMBAR !#0 N1401 P56 BLD 26 -1 FP BE Pri !#0 N1402 P56 BLD 27 -1 FP BE Pri !#0 N1403 P57 MEMBAR !#0 N1404 P58 REPLACEMENT 28 Int BE Pri !#0 N1405 P59 MEMBAR !#0 N1406 P60 BLD 21 -1 FP BE Sec !#0 N1407 P60 BLD 22 -1 FP BE Sec !#A N1406 N1407 !#0 N1408 P60 BLD 23 -1 FP BE Sec !#0 N1409 P61 MEMBAR !#0 N1410 P62 BST 0 0x3f80018c FP BE Pri !#0 N1411 P62 BST 1 0x3f80018d FP BE Pri !#A N1410 N1411 !#0 N1412 P62 BST 2 0x3f80018e FP BE Pri !#0 N1413 P62 BST 3 0x3f80018f FP BE Pri !#0 N1414 P62 BST 4 0x3f800190 FP BE Pri !#0 N1415 P63 MEMBAR !#0 N1416 P64 LD 31 -1 Int BE Pri !#0 N1417 P65 MEMBAR !#0 N1418 P66 BLD 0 -1 FP BE Pri !#0 N1419 P66 BLD 1 -1 FP BE Pri !#A N1418 N1419 !#0 N1420 P66 BLD 2 -1 FP BE Pri !#0 N1421 P66 BLD 3 -1 FP BE Pri !#0 N1422 P66 BLD 4 -1 FP BE Pri !#0 N1423 P67 MEMBAR !#0 N1424 P68 LD 27 -1 Int BE Pri !#0 N1425 P69 MEMBAR !#0 N1426 P70 BST 11 0x3f800191 FP BE Pri !#0 N1427 P70 BST 12 0x3f800192 FP BE Pri !#A N1426 N1427 !#0 N1428 P70 BST 13 0x3f800193 FP BE Pri !#0 N1429 P71 MEMBAR !#0 N1430 P72 BST 8 0x3f800194 FP BE Pri !#0 N1431 P72 BST 9 0x3f800195 FP BE Pri !#0 N1432 P73 MEMBAR !#0 N1433 P74 BLD 10 -1 FP BE Pri !#0 N1434 P75 MEMBAR !#0 N1435 P76 REPLACEMENT 15 Int BE Pri !#0 N1436 P77 MEMBAR !#0 N1437 P78 BLD 30 -1 FP BE Pri !#0 N1438 P79 MEMBAR !#0 N1439 P80 LD 32 -1 Int BE Pri !#0 N1440 P81 MEMBAR !#0 N1441 P82 BLD 0 -1 FP BE Pri !#0 N1442 P82 BLD 1 -1 FP BE Pri !#A N1441 N1442 !#0 N1443 P82 BLD 2 -1 FP BE Pri !#0 N1444 P82 BLD 3 -1 FP BE Pri !#0 N1445 P82 BLD 4 -1 FP BE Pri !#0 N1446 P83 MEMBAR !#0 N1447 P84 BLD 7 -1 FP BE Pri !#0 N1448 P85 MEMBAR !#0 N1449 P86 REPLACEMENT 18 Int BE Pri !#0 N1450 P87 LD 6 -1 FP BE Pri !#0 N1451 P88 MEMBAR !#0 N1452 P89 BLD 21 -1 FP BE Pri !#0 N1453 P89 BLD 22 -1 FP BE Pri !#A N1452 N1453 !#0 N1454 P89 BLD 23 -1 FP BE Pri !#0 N1455 P90 MEMBAR !#0 N1456 P91 BSTC 0 0x3f800196 FP BE Pri !#0 N1457 P91 BSTC 1 0x3f800197 FP BE Pri !#A N1456 N1457 !#0 N1458 P91 BSTC 2 0x3f800198 FP BE Pri !#0 N1459 P91 BSTC 3 0x3f800199 FP BE Pri !#0 N1460 P91 BSTC 4 0x3f80019a FP BE Pri !#0 N1461 P92 MEMBAR !#0 N1462 P93 BSTC 0 0x3f80019b FP BE Sec !#0 N1463 P93 BSTC 1 0x3f80019c FP BE Sec !#A N1462 N1463 !#0 N1464 P93 BSTC 2 0x3f80019d FP BE Sec !#0 N1465 P93 BSTC 3 0x3f80019e FP BE Sec !#0 N1466 P93 BSTC 4 0x3f80019f FP BE Sec !#0 N1467 P94 MEMBAR !#0 N1468 P95 PREFETCH 14 Int LE Pri !#0 N1469 P96 LD 18 -1 FP BE Pri !#0 N1470 P97 LD 27 -1 FP BE Pri !#0 N1471 P98 ST 32 0x2b Int BE Pri !#0 N1472 P99 IDC_FLIP 31 Int BE Pri !#0 N1473 P100 MEMBAR !#0 N1474 P101 BLD 26 -1 FP BE Pri !#0 N1475 P101 BLD 27 -1 FP BE Pri !#0 N1476 P102 MEMBAR !#0 N1477 P103 IDC_FLIP 7 Int BE Pri !#0 N1478 P104 IDC_FLIP 17 Int BE Pri !#0 N1479 P105 MEMBAR !#0 N1480 P106 BSTC 29 0x3f8001a0 FP BE Sec !#0 N1481 P107 MEMBAR !#0 N1482 P108 REPLACEMENT 29 Int BE Pri !#0 N1483 P109 PREFETCH 33 Int BE Pri !#0 N1484 P110 REPLACEMENT 29 Int BE Pri !#0 N1485 P111 MEMBAR !#0 N1486 P112 BST 21 0x3f8001a1 FP BE Pri !#0 N1487 P112 BST 22 0x3f8001a2 FP BE Pri !#A N1486 N1487 !#0 N1488 P112 BST 23 0x3f8001a3 FP BE Pri !#0 N1489 P113 MEMBAR !#0 N1490 P114 REPLACEMENT 12 Int BE Pri !#0 N1491 P115 MEMBAR !#0 N1492 P116 BST 0 0x3f8001a4 FP BE Pri !#0 N1493 P116 BST 1 0x3f8001a5 FP BE Pri !#A N1492 N1493 !#0 N1494 P116 BST 2 0x3f8001a6 FP BE Pri !#0 N1495 P116 BST 3 0x3f8001a7 FP BE Pri !#0 N1496 P116 BST 4 0x3f8001a8 FP BE Pri !#0 N1497 P117 MEMBAR !#0 N1498 P118 REPLACEMENT 9 Int BE Pri !#0 N1499 P119 ST 8 0x3f8001a9 FP BE Sec !#0 N1500 P120 PREFETCH 12 Int BE Pri !#0 N1501 P121 MEMBAR !#0 N1502 P122 BLD 32 -1 FP BE Pri !#0 N1503 P123 MEMBAR !#0 N1504 P124 IDC_FLIP 11 Int BE Pri !#0 N1505 P125 LD 2 -1 FP BE Pri !#0 N1506 P126 ST 24 0x2c Int BE Pri !#0 N1507 P127 LD 27 -1 Int BE Pri !#0 N1508 P128 MEMBAR !#0 N1509 P129 BLD 24 -1 FP BE Pri !#0 N1510 P129 BLD 25 -1 FP BE Pri !#0 N1511 P130 MEMBAR !#0 N1512 P131 BST 11 0x3f8001aa FP BE Pri !#0 N1513 P131 BST 12 0x3f8001ab FP BE Pri !#A N1512 N1513 !#0 N1514 P131 BST 13 0x3f8001ac FP BE Pri !#0 N1515 P132 MEMBAR !#0 N1516 P133 REPLACEMENT 11 Int BE Pri !#0 N1517 P134 ST 12 0x2d Int BE Pri !#0 N1518 P135 PREFETCH 4 Int LE Pri !#0 N1519 P136 MEMBAR !#0 N1520 P137 BSTC 20 0x3f8001ad FP BE Pri !#0 N1521 P138 MEMBAR !#0 N1522 P139 LD 20 -1 Int BE Nuc !#0 N1523 P140 MEMBAR !#0 N1524 P141 BSTC 7 0x3f8001ae FP BE Pri !#0 N1525 P142 MEMBAR !#0 N1526 P143 BSTC 19 0x3f8001af FP BE Pri !#0 N1527 P144 MEMBAR !#0 N1528 P145 BLD 8 -1 FP BE Pri !#0 N1529 P145 BLD 9 -1 FP BE Pri !#0 N1530 P146 MEMBAR !#0 N1531 P147 BSTC 11 0x3f8001b0 FP BE Pri !#0 N1532 P147 BSTC 12 0x3f8001b1 FP BE Pri !#A N1531 N1532 !#0 N1533 P147 BSTC 13 0x3f8001b2 FP BE Pri !#0 N1534 P148 MEMBAR !#0 N1535 P149 PREFETCH 26 Int BE Pri !#0 N1536 P150 MEMBAR !#0 N1537 P151 BLD 16 -1 FP BE Pri !#0 N1538 P152 MEMBAR !#0 N1539 P153 REPLACEMENT 17 Int BE Sec !#0 N1540 P154 LD 12 -1 FP BE Sec !#0 N1541 P155 MEMBAR !#0 N1542 P156 BST 8 0x3f8001b3 FP BE Sec !#0 N1543 P156 BST 9 0x3f8001b4 FP BE Sec !#0 N1544 P157 MEMBAR !#0 N1545 P158 BST 29 0x3f8001b5 FP BE Pri !#0 N1546 P159 MEMBAR !#0 N1547 P160 BSTC 0 0x3f8001b6 FP BE Pri !#0 N1548 P160 BSTC 1 0x3f8001b7 FP BE Pri !#A N1547 N1548 !#0 N1549 P160 BSTC 2 0x3f8001b8 FP BE Pri !#0 N1550 P160 BSTC 3 0x3f8001b9 FP BE Pri !#0 N1551 P160 BSTC 4 0x3f8001ba FP BE Pri !#0 N1552 P161 MEMBAR !#0 N1553 P162 PREFETCH 7 Int BE Pri !#0 N1554 P163 MEMBAR !#0 N1555 P164 BLD 15 -1 FP BE Sec !#0 N1556 P165 MEMBAR !#0 N1557 P166 BLD 33 -1 FP BE Pri !#0 N1558 P167 MEMBAR !#0 N1559 P168 ST 27 0x2e Int BE Pri !#0 N1560 P169 PREFETCH 21 Int BE Pri !#0 N1561 P170 LD 14 -1 Int BE Pri !#0 N1562 P171 MEMBAR !#0 N1563 P172 BST 5 0x3f8001bb FP BE Pri !#0 N1564 P172 BST 6 0x3f8001bc FP BE Pri !#0 N1565 P173 MEMBAR !#0 N1566 P174 ST 33 0x2f Int LE Nuc !#0 N1567 P175 MEMBAR !#0 N1568 P176 BLD 21 -1 FP BE Pri !#0 N1569 P176 BLD 22 -1 FP BE Pri !#A N1568 N1569 !#0 N1570 P176 BLD 23 -1 FP BE Pri !#0 N1571 P177 MEMBAR !#0 N1572 P178 BLD 0 -1 FP BE Pri !#0 N1573 P178 BLD 1 -1 FP BE Pri !#A N1572 N1573 !#0 N1574 P178 BLD 2 -1 FP BE Pri !#0 N1575 P178 BLD 3 -1 FP BE Pri !#0 N1576 P178 BLD 4 -1 FP BE Pri !#0 N1577 P179 MEMBAR !#0 N1578 P180 BLD 21 -1 FP BE Sec !#0 N1579 P180 BLD 22 -1 FP BE Sec !#A N1578 N1579 !#0 N1580 P180 BLD 23 -1 FP BE Sec !#0 N1581 P181 MEMBAR !#0 N1582 P182 LD 17 -1 FP BE Pri !#0 N1583 P183 LD 18 -1 FP BE Nuc !#0 N1584 P184 MEMBAR !#0 N1585 P185 BLD 20 -1 FP BE Pri !#0 N1586 P186 MEMBAR !#0 N1587 P187 REPLACEMENT 5 Int BE Pri !#0 N1588 P188 MEMBAR !#0 N1589 P189 BLD 11 -1 FP BE Pri !#0 N1590 P189 BLD 12 -1 FP BE Pri !#A N1589 N1590 !#0 N1591 P189 BLD 13 -1 FP BE Pri !#0 N1592 P190 MEMBAR !#0 N1593 P191 REPLACEMENT 28 Int BE Sec !#0 N1594 P192 PREFETCH 4 Int BE Nuc !#0 N1595 P193 PREFETCH 21 Int BE Sec !#0 N1596 P194 ST 24 0x3f8001bd FP BE Pri !#0 N1597 P195 ST 5 0x30 Int LE Pri !#0 N1598 P196 FLUSHI 0 Int BE Pri !#0 N1599 P197 ST 4 0x31 Int BE Pri !#0 N1600 P198 REPLACEMENT 32 Int BE Pri !#0 N1601 P199 MEMBAR !#0 N1602 P200 BSTC 21 0x3f8001be FP BE Pri !#0 N1603 P200 BSTC 22 0x3f8001bf FP BE Pri !#A N1602 N1603 !#0 N1604 P200 BSTC 23 0x3f8001c0 FP BE Pri !#0 N1605 P201 MEMBAR !#0 N1606 P202 BST 10 0x3f8001c1 FP BE Pri !#0 N1607 P203 MEMBAR !#0 N1608 P204 ST 28 0x3f8001c2 FP BE Pri !#0 N1609 P205 MEMBAR !#0 N1610 P206 BLD 0 -1 FP BE Pri !#0 N1611 P206 BLD 1 -1 FP BE Pri !#A N1610 N1611 !#0 N1612 P206 BLD 2 -1 FP BE Pri !#0 N1613 P206 BLD 3 -1 FP BE Pri !#0 N1614 P206 BLD 4 -1 FP BE Pri !#0 N1615 P207 MEMBAR !#0 N1616 P208 ST 7 0x32 Int BE Pri !#0 N1617 P209 MEMBAR !#0 N1618 P210 BST 15 0x3f8001c3 FP BE Pri !#0 N1619 P211 MEMBAR !#0 N1620 P212 REPLACEMENT 1 Int BE Pri !#0 N1621 P213 MEMBAR !#0 N1622 P214 BLD 14 -1 FP BE Pri !#0 N1623 P215 MEMBAR !#0 N1624 P216 BSTC 33 0x3f8001c4 FP BE Pri !#0 N1625 P217 MEMBAR !#0 N1626 P218 BSTC 0 0x3f8001c5 FP BE Pri !#0 N1627 P218 BSTC 1 0x3f8001c6 FP BE Pri !#A N1626 N1627 !#0 N1628 P218 BSTC 2 0x3f8001c7 FP BE Pri !#0 N1629 P218 BSTC 3 0x3f8001c8 FP BE Pri !#0 N1630 P218 BSTC 4 0x3f8001c9 FP BE Pri !#0 N1631 P219 MEMBAR !#0 N1632 P220 ST 19 0x3f8001ca FP BE Pri !#0 N1633 P221 MEMBAR !#0 N1634 P222 BST 10 0x3f8001cb FP BE Pri !#0 N1635 P223 MEMBAR !#0 N1636 P224 REPLACEMENT 21 Int BE Pri !#0 N1637 P225 MEMBAR !#0 N1638 P226 BLD 5 -1 FP BE Pri !#0 N1639 P226 BLD 6 -1 FP BE Pri !#0 N1640 P227 MEMBAR !#0 N1641 P228 BLD 26 -1 FP BE Pri !#0 N1642 P228 BLD 27 -1 FP BE Pri !#0 N1643 P229 MEMBAR !#0 N1644 P230 LD 22 -1 Int BE Sec !#0 N1645 P231 MEMBAR !#0 N1646 P232 BLD 33 -1 FP BE Pri !#0 N1647 P233 MEMBAR !#0 N1648 P234 BST 7 0x3f8001cc FP BE Pri !#0 N1649 P235 MEMBAR !#0 N1650 P236 LD 28 -1 Int BE Pri Loop_exit !#0 N1651 P237 MEMBAR !#1 N1652 P238 MEMBAR !#1 N1653 P239 BLD 0 -1 FP BE Pri !#1 N1654 P239 BLD 1 -1 FP BE Pri !#A N1653 N1654 !#1 N1655 P239 BLD 2 -1 FP BE Pri !#1 N1656 P239 BLD 3 -1 FP BE Pri !#1 N1657 P239 BLD 4 -1 FP BE Pri !#1 N1658 P240 MEMBAR !#1 N1659 P241 IDC_FLIP 19 Int BE Pri !#1 N1660 P242 MEMBAR !#1 N1661 P243 BLD 8 -1 FP BE Pri !#1 N1662 P243 BLD 9 -1 FP BE Pri !#1 N1663 P244 MEMBAR !#1 N1664 P245 PREFETCH 13 Int BE Pri !#1 N1665 P246 REPLACEMENT 18 Int BE Pri !#1 N1666 P247 LD 14 -1 FP BE Pri !#1 N1667 P248 MEMBAR !#1 N1668 P249 BST 16 0x40000001 FP BE Sec !#1 N1669 P250 MEMBAR !#1 N1670 P251 BLD 5 -1 FP BE Pri !#1 N1671 P251 BLD 6 -1 FP BE Pri !#1 N1672 P252 MEMBAR !#1 N1673 P253 BSTC 14 0x40000002 FP BE Pri !#1 N1674 P254 MEMBAR !#1 N1675 P255 REPLACEMENT 13 Int BE Pri !#1 N1676 P256 PREFETCH 17 Int BE Pri !#1 N1677 P257 MEMBAR !#1 N1678 P258 BST 18 0x40000003 FP BE Pri !#1 N1679 P259 MEMBAR !#1 N1680 P260 LD 24 -1 FP BE Pri !#1 N1681 P261 REPLACEMENT 24 Int BE Sec !#1 N1682 P262 MEMBAR !#1 N1683 P263 BST 24 0x40000004 FP BE Sec !#1 N1684 P263 BST 25 0x40000005 FP BE Sec !#1 N1685 P264 MEMBAR !#1 N1686 P265 LD 22 -1 Int BE Pri !#1 N1687 P266 MEMBAR !#1 N1688 P267 BST 0 0x40000006 FP BE Pri !#1 N1689 P267 BST 1 0x40000007 FP BE Pri !#A N1688 N1689 !#1 N1690 P267 BST 2 0x40000008 FP BE Pri !#1 N1691 P267 BST 3 0x40000009 FP BE Pri !#1 N1692 P267 BST 4 0x4000000a FP BE Pri !#1 N1693 P268 MEMBAR !#1 N1694 P269 BSTC 11 0x4000000b FP BE Pri !#1 N1695 P269 BSTC 12 0x4000000c FP BE Pri !#A N1694 N1695 !#1 N1696 P269 BSTC 13 0x4000000d FP BE Pri !#1 N1697 P270 MEMBAR !#1 N1698 P271 PREFETCH 31 Int BE Sec !#1 N1699 P272 LD 11 -1 Int BE Pri !#1 N1700 P273 LD 9 -1 Int BE Pri !#1 N1701 P274 REPLACEMENT 20 Int BE Pri !#1 N1702 P275 REPLACEMENT 20 Int BE Nuc !#1 N1703 P276 MEMBAR !#1 N1704 P277 BLD 21 -1 FP BE Pri !#1 N1705 P277 BLD 22 -1 FP BE Pri !#A N1704 N1705 !#1 N1706 P277 BLD 23 -1 FP BE Pri !#1 N1707 P278 MEMBAR !#1 N1708 P279 BSTC 30 0x4000000e FP BE Pri !#1 N1709 P280 MEMBAR !#1 N1710 P281 BSTC 15 0x4000000f FP BE Pri !#1 N1711 P282 MEMBAR !#1 N1712 P283 PREFETCH 12 Int BE Pri !#1 N1713 P284 LD 26 -1 FP BE Pri !#1 N1714 P285 MEMBAR !#1 N1715 P286 BLD 20 -1 FP BE Pri !#1 N1716 P287 MEMBAR !#1 N1717 P288 BST 0 0x40000010 FP BE Pri !#1 N1718 P288 BST 1 0x40000011 FP BE Pri !#A N1717 N1718 !#1 N1719 P288 BST 2 0x40000012 FP BE Pri !#1 N1720 P288 BST 3 0x40000013 FP BE Pri !#1 N1721 P288 BST 4 0x40000014 FP BE Pri !#1 N1722 P289 MEMBAR !#1 N1723 P290 REPLACEMENT 21 Int BE Sec !#1 N1724 P291 REPLACEMENT 1 Int BE Pri !#1 N1725 P292 REPLACEMENT 29 Int BE Pri !#1 N1726 P293 PREFETCH 25 Int LE Sec !#1 N1727 P294 MEMBAR !#1 N1728 P295 BLD 29 -1 FP BE Pri !#1 N1729 P296 MEMBAR !#1 N1730 P297 BST 33 0x40000015 FP BE Pri !#1 N1731 P298 MEMBAR !#1 N1732 P299 BSTC 30 0x40000016 FP BE Pri !#1 N1733 P300 MEMBAR !#1 N1734 P301 BSTC 32 0x40000017 FP BE Sec !#1 N1735 P302 MEMBAR !#1 N1736 P303 ST 19 0x40000018 FP BE Sec !#1 N1737 P304 MEMBAR !#1 N1738 P305 BLD 8 -1 FP BE Pri !#1 N1739 P305 BLD 9 -1 FP BE Pri !#1 N1740 P306 MEMBAR !#1 N1741 P307 BST 26 0x40000019 FP BE Pri !#1 N1742 P307 BST 27 0x4000001a FP BE Pri !#1 N1743 P308 MEMBAR !#1 N1744 P309 PREFETCH 28 Int BE Pri !#1 N1745 P310 REPLACEMENT 15 Int BE Pri !#1 N1746 P311 MEMBAR !#1 N1747 P312 BLD 15 -1 FP BE Sec !#1 N1748 P313 MEMBAR !#1 N1749 P314 BSTC 21 0x4000001b FP BE Sec !#1 N1750 P314 BSTC 22 0x4000001c FP BE Sec !#A N1749 N1750 !#1 N1751 P314 BSTC 23 0x4000001d FP BE Sec !#1 N1752 P315 MEMBAR !#1 N1753 P316 BLD 30 -1 FP BE Sec !#1 N1754 P317 MEMBAR !#1 N1755 P318 BST 17 0x4000001e FP BE Pri !#1 N1756 P319 MEMBAR !#1 N1757 P320 PREFETCH 21 Int BE Pri !#1 N1758 P321 MEMBAR !#1 N1759 P322 BLD 29 -1 FP BE Pri !#1 N1760 P323 MEMBAR !#1 N1761 P324 IDC_FLIP 6 Int BE Pri !#1 N1762 P325 REPLACEMENT 24 Int BE Nuc !#1 N1763 P326 MEMBAR !#1 N1764 P327 BLD 0 -1 FP BE Sec !#1 N1765 P327 BLD 1 -1 FP BE Sec !#A N1764 N1765 !#1 N1766 P327 BLD 2 -1 FP BE Sec !#1 N1767 P327 BLD 3 -1 FP BE Sec !#1 N1768 P327 BLD 4 -1 FP BE Sec !#1 N1769 P328 MEMBAR !#1 N1770 P329 REPLACEMENT 26 Int BE Pri !#1 N1771 P330 MEMBAR !#1 N1772 P331 BSTC 14 0x4000001f FP BE Pri !#1 N1773 P332 MEMBAR !#1 N1774 P333 BLD 11 -1 FP BE Pri !#1 N1775 P333 BLD 12 -1 FP BE Pri !#A N1774 N1775 !#1 N1776 P333 BLD 13 -1 FP BE Pri !#1 N1777 P334 MEMBAR !#1 N1778 P335 LD 8 -1 Int BE Pri !#1 N1779 P336 MEMBAR !#1 N1780 P337 BLD 11 -1 FP BE Pri !#1 N1781 P337 BLD 12 -1 FP BE Pri !#A N1780 N1781 !#1 N1782 P337 BLD 13 -1 FP BE Pri !#1 N1783 P338 MEMBAR !#1 N1784 P339 ST 21 0x800001 Int BE Pri !#1 N1785 P340 ST 17 0x40000020 FP BE Sec !#1 N1786 P341 MEMBAR !#1 N1787 P342 BLD 24 -1 FP BE Pri !#1 N1788 P342 BLD 25 -1 FP BE Pri !#1 N1789 P343 MEMBAR !#1 N1790 P344 BST 7 0x40000021 FP BE Sec !#1 N1791 P345 MEMBAR !#1 N1792 P346 BLD 28 -1 FP BE Pri !#1 N1793 P347 MEMBAR !#1 N1794 P348 ST 6 0x40000022 FP BE Sec !#1 N1795 P349 MEMBAR !#1 N1796 P350 BSTC 8 0x40000023 FP BE Pri !#1 N1797 P350 BSTC 9 0x40000024 FP BE Pri !#1 N1798 P351 MEMBAR !#1 N1799 P352 BLD 21 -1 FP BE Pri !#1 N1800 P352 BLD 22 -1 FP BE Pri !#A N1799 N1800 !#1 N1801 P352 BLD 23 -1 FP BE Pri !#1 N1802 P353 MEMBAR !#1 N1803 P354 BLD 17 -1 FP BE Pri !#1 N1804 P355 MEMBAR !#1 N1805 P356 BSTC 10 0x40000025 FP BE Pri !#1 N1806 P357 MEMBAR !#1 N1807 P358 REPLACEMENT 19 Int BE Pri !#1 N1808 P359 MEMBAR !#1 N1809 P360 BST 31 0x40000026 FP BE Sec !#1 N1810 P361 MEMBAR !#1 N1811 P362 BSTC 20 0x40000027 FP BE Sec !#1 N1812 P363 MEMBAR !#1 N1813 P364 BLD 0 -1 FP BE Pri !#1 N1814 P364 BLD 1 -1 FP BE Pri !#A N1813 N1814 !#1 N1815 P364 BLD 2 -1 FP BE Pri !#1 N1816 P364 BLD 3 -1 FP BE Pri !#1 N1817 P364 BLD 4 -1 FP BE Pri !#1 N1818 P365 MEMBAR !#1 N1819 P366 BST 5 0x40000028 FP BE Pri !#1 N1820 P366 BST 6 0x40000029 FP BE Pri !#1 N1821 P367 MEMBAR !#1 N1822 P368 LD 16 -1 Int BE Pri !#1 N1823 P369 REPLACEMENT 11 Int BE Nuc !#1 N1824 P370 REPLACEMENT 16 Int BE Pri !#1 N1825 P371 LD 3 -1 Int BE Pri !#1 N1826 P372 MEMBAR !#1 N1827 P373 BSTC 28 0x4000002a FP BE Sec !#1 N1828 P374 MEMBAR !#1 N1829 P375 BSTC 24 0x4000002b FP BE Pri !#1 N1830 P375 BSTC 25 0x4000002c FP BE Pri !#1 N1831 P376 MEMBAR !#1 N1832 P377 BST 0 0x4000002d FP BE Pri !#1 N1833 P377 BST 1 0x4000002e FP BE Pri !#A N1832 N1833 !#1 N1834 P377 BST 2 0x4000002f FP BE Pri !#1 N1835 P377 BST 3 0x40000030 FP BE Pri !#1 N1836 P377 BST 4 0x40000031 FP BE Pri !#1 N1837 P378 MEMBAR !#1 N1838 P379 BLD 10 -1 FP BE Pri !#1 N1839 P380 MEMBAR !#1 N1840 P381 REPLACEMENT 9 Int BE Pri !#1 N1841 P382 REPLACEMENT 32 Int BE Pri !#1 N1842 P383 MEMBAR !#1 N1843 P384 BSTC 31 0x40000032 FP BE Pri !#1 N1844 P385 MEMBAR !#1 N1845 P386 BSTC 5 0x40000033 FP BE Pri !#1 N1846 P386 BSTC 6 0x40000034 FP BE Pri !#1 N1847 P387 MEMBAR !#1 N1848 P388 LD 8 -1 Int BE Pri !#1 N1849 P389 MEMBAR !#1 N1850 P390 BSTC 5 0x40000035 FP BE Sec !#1 N1851 P390 BSTC 6 0x40000036 FP BE Sec !#1 N1852 P391 MEMBAR !#1 N1853 P392 LD 3 -1 FP BE Pri !#1 N1854 P393 REPLACEMENT 32 Int BE Sec !#1 N1855 P394 ST 25 0x800002 Int BE Pri !#1 N1856 P395 MEMBAR !#1 N1857 P396 BST 24 0x40000037 FP BE Pri !#1 N1858 P396 BST 25 0x40000038 FP BE Pri !#1 N1859 P397 MEMBAR !#1 N1860 P398 BLD 29 -1 FP BE Pri !#1 N1861 P399 MEMBAR !#1 N1862 P400 REPLACEMENT 19 Int BE Pri !#1 N1863 P401 MEMBAR !#1 N1864 P402 BLD 19 -1 FP BE Pri !#1 N1865 P403 MEMBAR !#1 N1866 P404 BSTC 19 0x40000039 FP BE Pri !#1 N1867 P405 MEMBAR !#1 N1868 P406 LD 8 -1 Int BE Pri !#1 N1869 P407 MEMBAR !#1 N1870 P408 BLD 21 -1 FP BE Pri !#1 N1871 P408 BLD 22 -1 FP BE Pri !#A N1870 N1871 !#1 N1872 P408 BLD 23 -1 FP BE Pri !#1 N1873 P409 MEMBAR !#1 N1874 P410 BSTC 26 0x4000003a FP BE Pri !#1 N1875 P410 BSTC 27 0x4000003b FP BE Pri !#1 N1876 P411 MEMBAR !#1 N1877 P412 REPLACEMENT 19 Int BE Sec !#1 N1878 P413 MEMBAR !#1 N1879 P414 BLD 28 -1 FP BE Pri !#1 N1880 P415 MEMBAR !#1 N1881 P416 BSTC 11 0x4000003c FP BE Pri !#1 N1882 P416 BSTC 12 0x4000003d FP BE Pri !#A N1881 N1882 !#1 N1883 P416 BSTC 13 0x4000003e FP BE Pri !#1 N1884 P417 MEMBAR !#1 N1885 P418 BSTC 32 0x4000003f FP BE Pri !#1 N1886 P419 MEMBAR !#1 N1887 P420 BSTC 0 0x40000040 FP BE Pri !#1 N1888 P420 BSTC 1 0x40000041 FP BE Pri !#A N1887 N1888 !#1 N1889 P420 BSTC 2 0x40000042 FP BE Pri !#1 N1890 P420 BSTC 3 0x40000043 FP BE Pri !#1 N1891 P420 BSTC 4 0x40000044 FP BE Pri !#1 N1892 P421 MEMBAR !#1 N1893 P422 BLD 31 -1 FP BE Pri !#1 N1894 P423 MEMBAR !#1 N1895 P424 ST 27 0x40000045 FP BE Pri !#1 N1896 P425 MEMBAR !#1 N1897 P426 BSTC 8 0x40000046 FP BE Pri !#1 N1898 P426 BSTC 9 0x40000047 FP BE Pri !#1 N1899 P427 MEMBAR !#1 N1900 P428 PREFETCH 3 Int BE Nuc !#1 N1901 P429 REPLACEMENT 16 Int BE Sec !#1 N1902 P430 MEMBAR !#1 N1903 P431 BST 0 0x40000048 FP BE Pri !#1 N1904 P431 BST 1 0x40000049 FP BE Pri !#A N1903 N1904 !#1 N1905 P431 BST 2 0x4000004a FP BE Pri !#1 N1906 P431 BST 3 0x4000004b FP BE Pri !#1 N1907 P431 BST 4 0x4000004c FP BE Pri !#1 N1908 P432 MEMBAR !#1 N1909 P433 ST 23 0x800003 Int BE Sec !#1 N1910 P434 MEMBAR !#1 N1911 P435 BST 26 0x4000004d FP BE Pri !#1 N1912 P435 BST 27 0x4000004e FP BE Pri !#1 N1913 P436 MEMBAR !#1 N1914 P437 LD 11 -1 FP BE Sec !#1 N1915 P438 LD 5 -1 FP BE Pri !#1 N1916 P439 LD 11 -1 Int BE Pri !#1 N1917 P440 LD 31 -1 FP BE Pri !#1 N1918 P441 LD 12 -1 FP BE Pri !#1 N1919 P442 REPLACEMENT 23 Int BE Sec !#1 N1920 P443 MEMBAR !#1 N1921 P444 BSTC 20 0x4000004f FP BE Pri !#1 N1922 P445 MEMBAR !#1 N1923 P446 BLD 0 -1 FP BE Pri !#1 N1924 P446 BLD 1 -1 FP BE Pri !#A N1923 N1924 !#1 N1925 P446 BLD 2 -1 FP BE Pri !#1 N1926 P446 BLD 3 -1 FP BE Pri !#1 N1927 P446 BLD 4 -1 FP BE Pri !#1 N1928 P447 MEMBAR !#1 N1929 P448 BSTC 5 0x40000050 FP BE Pri !#1 N1930 P448 BSTC 6 0x40000051 FP BE Pri !#1 N1931 P449 MEMBAR !#1 N1932 P450 REPLACEMENT 20 Int BE Sec !#1 N1933 P451 MEMBAR !#1 N1934 P452 BLD 5 -1 FP BE Pri !#1 N1935 P452 BLD 6 -1 FP BE Pri !#1 N1936 P453 MEMBAR !#1 N1937 P454 PREFETCH 23 Int BE Pri !#1 N1938 P455 PREFETCH 5 Int BE Pri !#1 N1939 P456 PREFETCH 27 Int BE Sec !#1 N1940 P457 MEMBAR !#1 N1941 P458 BSTC 29 0x40000052 FP BE Pri !#1 N1942 P459 MEMBAR !#1 N1943 P460 BST 11 0x40000053 FP BE Pri !#1 N1944 P460 BST 12 0x40000054 FP BE Pri !#A N1943 N1944 !#1 N1945 P460 BST 13 0x40000055 FP BE Pri !#1 N1946 P461 MEMBAR !#1 N1947 P462 BSTC 15 0x40000056 FP BE Pri !#1 N1948 P463 MEMBAR !#1 N1949 P464 REPLACEMENT 8 Int BE Pri !#1 N1950 P465 PREFETCH 7 Int BE Sec !#1 N1951 P466 MEMBAR !#1 N1952 P467 BLD 14 -1 FP BE Pri !#1 N1953 P468 MEMBAR !#1 N1954 P469 BST 14 0x40000057 FP BE Pri !#1 N1955 P470 MEMBAR !#1 N1956 P471 REPLACEMENT 8 Int BE Pri !#1 N1957 P472 MEMBAR !#1 N1958 P473 BLD 24 -1 FP BE Pri !#1 N1959 P473 BLD 25 -1 FP BE Pri !#1 N1960 P474 MEMBAR !#1 N1961 P475 BLD 5 -1 FP BE Pri !#1 N1962 P475 BLD 6 -1 FP BE Pri !#1 N1963 P476 MEMBAR !#1 N1964 P477 PREFETCH 12 Int BE Pri !#1 N1965 P478 REPLACEMENT 20 Int BE Pri !#1 N1966 P479 REPLACEMENT 5 Int BE Pri !#1 N1967 P480 ST 28 0x800004 Int BE Sec !#1 N1968 P481 MEMBAR !#1 N1969 P482 BLD 30 -1 FP BE Pri !#1 N1970 P483 MEMBAR !#1 N1971 P484 REPLACEMENT 13 Int BE Sec !#1 N1972 P485 MEMBAR !#1 N1973 P486 BST 11 0x40000058 FP BE Pri !#1 N1974 P486 BST 12 0x40000059 FP BE Pri !#A N1973 N1974 !#1 N1975 P486 BST 13 0x4000005a FP BE Pri !#1 N1976 P487 MEMBAR !#1 N1977 P488 ST 24 0x4000005b FP BE Pri !#1 N1978 P489 MEMBAR !#1 N1979 P490 BSTC 20 0x4000005c FP BE Pri !#1 N1980 P491 MEMBAR !#1 N1981 P492 BLD 16 -1 FP BE Pri !#1 N1982 P493 MEMBAR !#1 N1983 P494 BLD 0 -1 FP BE Pri !#1 N1984 P494 BLD 1 -1 FP BE Pri !#A N1983 N1984 !#1 N1985 P494 BLD 2 -1 FP BE Pri !#1 N1986 P494 BLD 3 -1 FP BE Pri !#1 N1987 P494 BLD 4 -1 FP BE Pri !#1 N1988 P495 MEMBAR !#1 N1989 P496 PREFETCH 5 Int BE Pri !#1 N1990 P497 MEMBAR !#1 N1991 P498 BLD 28 -1 FP BE Pri !#1 N1992 P499 MEMBAR !#1 N1993 P500 BLD 0 -1 FP BE Pri !#1 N1994 P500 BLD 1 -1 FP BE Pri !#A N1993 N1994 !#1 N1995 P500 BLD 2 -1 FP BE Pri !#1 N1996 P500 BLD 3 -1 FP BE Pri !#1 N1997 P500 BLD 4 -1 FP BE Pri !#1 N1998 P501 MEMBAR !#1 N1999 P502 REPLACEMENT 11 Int BE Pri !#1 N2000 P503 LD 13 -1 Int BE Pri !#1 N2001 P504 MEMBAR !#1 N2002 P505 BST 31 0x4000005d FP BE Pri !#1 N2003 P506 MEMBAR !#1 N2004 P507 BLD 0 -1 FP BE Sec !#1 N2005 P507 BLD 1 -1 FP BE Sec !#A N2004 N2005 !#1 N2006 P507 BLD 2 -1 FP BE Sec !#1 N2007 P507 BLD 3 -1 FP BE Sec !#1 N2008 P507 BLD 4 -1 FP BE Sec !#1 N2009 P508 MEMBAR !#1 N2010 P509 BLD 19 -1 FP BE Pri !#1 N2011 P510 MEMBAR !#1 N2012 P511 BLD 20 -1 FP BE Pri !#1 N2013 P512 MEMBAR !#1 N2014 P513 ST 26 0x800005 Int BE Pri !#1 N2015 P514 MEMBAR !#1 N2016 P515 BLD 11 -1 FP BE Pri !#1 N2017 P515 BLD 12 -1 FP BE Pri !#A N2016 N2017 !#1 N2018 P515 BLD 13 -1 FP BE Pri !#1 N2019 P516 MEMBAR !#1 N2020 P517 ST 3 0x4000005e FP BE Pri !#1 N2021 P518 ST 27 0x800006 Int BE Pri !#1 N2022 P519 MEMBAR !#1 N2023 P520 BLD 8 -1 FP BE Pri !#1 N2024 P520 BLD 9 -1 FP BE Pri !#1 N2025 P521 MEMBAR !#1 N2026 P522 BST 29 0x4000005f FP BE Pri !#1 N2027 P523 MEMBAR !#1 N2028 P524 LD 33 -1 Int BE Pri !#1 N2029 P525 PREFETCH 23 Int BE Pri !#1 N2030 P526 ST 30 0x40000060 FP BE Pri !#1 N2031 P527 ST 33 0x40000061 FP BE Pri !#1 N2032 P528 ST 16 0x800007 Int BE Nuc !#1 N2033 P529 LD 9 -1 FP BE Pri !#1 N2034 P530 MEMBAR !#1 N2035 P531 BST 7 0x40000062 FP BE Pri !#1 N2036 P532 MEMBAR !#1 N2037 P533 BLD 30 -1 FP BE Pri !#1 N2038 P534 MEMBAR !#1 N2039 P535 LD 20 -1 Int BE Nuc !#1 N2040 P536 IDC_FLIP 13 Int BE Pri !#1 N2041 P537 REPLACEMENT 19 Int BE Pri !#1 N2042 P538 MEMBAR !#1 N2043 P539 BLD 10 -1 FP BE Sec !#1 N2044 P540 MEMBAR !#1 N2045 P541 IDC_FLIP 21 Int BE Pri !#1 N2046 P542 REPLACEMENT 2 Int BE Sec !#1 N2047 P543 PREFETCH 6 Int LE Pri !#1 N2048 P544 PREFETCH 4 Int BE Pri !#1 N2049 P545 MEMBAR !#1 N2050 P546 BLD 11 -1 FP BE Pri !#1 N2051 P546 BLD 12 -1 FP BE Pri !#A N2050 N2051 !#1 N2052 P546 BLD 13 -1 FP BE Pri !#1 N2053 P547 MEMBAR !#1 N2054 P548 LD 21 -1 Int BE Sec !#1 N2055 P549 PREFETCH 16 Int BE Pri !#1 N2056 P550 LD 5 -1 FP BE Pri !#1 N2057 P551 MEMBAR !#1 N2058 P552 BLD 0 -1 FP BE Sec !#1 N2059 P552 BLD 1 -1 FP BE Sec !#A N2058 N2059 !#1 N2060 P552 BLD 2 -1 FP BE Sec !#1 N2061 P552 BLD 3 -1 FP BE Sec !#1 N2062 P552 BLD 4 -1 FP BE Sec !#1 N2063 P553 MEMBAR !#1 N2064 P554 BLD 24 -1 FP BE Pri !#1 N2065 P554 BLD 25 -1 FP BE Pri !#1 N2066 P555 MEMBAR !#1 N2067 P556 IDC_FLIP 22 Int BE Pri !#1 N2068 P557 MEMBAR !#1 N2069 P558 BLD 24 -1 FP BE Pri !#1 N2070 P558 BLD 25 -1 FP BE Pri !#1 N2071 P559 MEMBAR !#1 N2072 P560 BSTC 18 0x40000063 FP BE Pri !#1 N2073 P561 MEMBAR !#1 N2074 P562 REPLACEMENT 17 Int BE Sec !#1 N2075 P563 MEMBAR !#1 N2076 P564 BLD 29 -1 FP BE Pri !#1 N2077 P565 MEMBAR !#1 N2078 P566 BST 17 0x40000064 FP BE Sec !#1 N2079 P567 MEMBAR !#1 N2080 P568 PREFETCH 19 Int BE Pri !#1 N2081 P569 REPLACEMENT 22 Int BE Pri !#1 N2082 P570 MEMBAR !#1 N2083 P571 BLD 31 -1 FP BE Pri !#1 N2084 P572 MEMBAR !#1 N2085 P573 PREFETCH 31 Int BE Pri !#1 N2086 P574 LD 23 -1 Int BE Pri !#1 N2087 P575 MEMBAR !#1 N2088 P576 BLD 24 -1 FP BE Pri !#1 N2089 P576 BLD 25 -1 FP BE Pri !#1 N2090 P577 MEMBAR !#1 N2091 P578 PREFETCH 26 Int BE Pri !#1 N2092 P579 LD 2 -1 FP BE Pri !#1 N2093 P580 MEMBAR !#1 N2094 P581 BSTC 32 0x40000065 FP BE Pri !#1 N2095 P582 MEMBAR !#1 N2096 P583 LD 0 -1 Int LE Pri !#1 N2097 P584 MEMBAR !#1 N2098 P585 BSTC 26 0x40000066 FP BE Pri !#1 N2099 P585 BSTC 27 0x40000067 FP BE Pri !#1 N2100 P586 MEMBAR !#1 N2101 P587 BST 14 0x40000068 FP BE Pri !#1 N2102 P588 MEMBAR !#1 N2103 P589 BLD 10 -1 FP BE Sec !#1 N2104 P590 MEMBAR !#1 N2105 P591 PREFETCH 0 Int BE Pri !#1 N2106 P592 REPLACEMENT 18 Int BE Pri !#1 N2107 P593 MEMBAR !#1 N2108 P594 BLD 8 -1 FP BE Pri !#1 N2109 P594 BLD 9 -1 FP BE Pri !#1 N2110 P595 MEMBAR !#1 N2111 P596 REPLACEMENT 18 Int BE Pri !#1 N2112 P597 MEMBAR !#1 N2113 P598 BST 0 0x40000069 FP BE Pri !#1 N2114 P598 BST 1 0x4000006a FP BE Pri !#A N2113 N2114 !#1 N2115 P598 BST 2 0x4000006b FP BE Pri !#1 N2116 P598 BST 3 0x4000006c FP BE Pri !#1 N2117 P598 BST 4 0x4000006d FP BE Pri !#1 N2118 P599 MEMBAR !#1 N2119 P600 BST 5 0x4000006e FP BE Pri !#1 N2120 P600 BST 6 0x4000006f FP BE Pri !#1 N2121 P601 MEMBAR !#1 N2122 P602 BLD 15 -1 FP BE Pri !#1 N2123 P603 MEMBAR !#1 N2124 P604 REPLACEMENT 33 Int BE Pri !#1 N2125 P605 MEMBAR !#1 N2126 P606 BLD 0 -1 FP BE Pri !#1 N2127 P606 BLD 1 -1 FP BE Pri !#A N2126 N2127 !#1 N2128 P606 BLD 2 -1 FP BE Pri !#1 N2129 P606 BLD 3 -1 FP BE Pri !#1 N2130 P606 BLD 4 -1 FP BE Pri !#1 N2131 P607 MEMBAR !#1 N2132 P608 REPLACEMENT 21 Int BE Pri !#1 N2133 P609 MEMBAR !#1 N2134 P610 BLD 15 -1 FP BE Pri !#1 N2135 P611 MEMBAR !#1 N2136 P612 REPLACEMENT 29 Int BE Pri !#1 N2137 P613 LD 28 -1 Int BE Nuc !#1 N2138 P614 MEMBAR !#1 N2139 P615 BLD 24 -1 FP BE Pri !#1 N2140 P615 BLD 25 -1 FP BE Pri !#1 N2141 P616 MEMBAR !#1 N2142 P617 ST 23 0x40000070 FP BE Pri !#1 N2143 P618 MEMBAR !#1 N2144 P619 BST 19 0x40000071 FP BE Pri !#1 N2145 P620 MEMBAR !#1 N2146 P621 BLD 5 -1 FP BE Pri !#1 N2147 P621 BLD 6 -1 FP BE Pri !#1 N2148 P622 MEMBAR !#1 N2149 P623 BST 24 0x40000072 FP BE Pri !#1 N2150 P623 BST 25 0x40000073 FP BE Pri !#1 N2151 P624 MEMBAR !#1 N2152 P625 PREFETCH 23 Int BE Sec !#1 N2153 P626 MEMBAR !#1 N2154 P627 BLD 0 -1 FP BE Pri !#1 N2155 P627 BLD 1 -1 FP BE Pri !#A N2154 N2155 !#1 N2156 P627 BLD 2 -1 FP BE Pri !#1 N2157 P627 BLD 3 -1 FP BE Pri !#1 N2158 P627 BLD 4 -1 FP BE Pri !#1 N2159 P628 MEMBAR !#1 N2160 P629 BST 24 0x40000074 FP BE Pri !#1 N2161 P629 BST 25 0x40000075 FP BE Pri !#1 N2162 P630 MEMBAR !#1 N2163 P631 BLD 21 -1 FP BE Pri !#1 N2164 P631 BLD 22 -1 FP BE Pri !#A N2163 N2164 !#1 N2165 P631 BLD 23 -1 FP BE Pri !#1 N2166 P632 MEMBAR !#1 N2167 P633 BLD 20 -1 FP BE Pri !#1 N2168 P634 MEMBAR !#1 N2169 P635 REPLACEMENT 27 Int BE Pri !#1 N2170 P636 REPLACEMENT 33 Int BE Sec !#1 N2171 P637 LD 7 -1 Int BE Pri !#1 N2172 P638 MEMBAR !#1 N2173 P639 BLD 26 -1 FP BE Pri !#1 N2174 P639 BLD 27 -1 FP BE Pri !#1 N2175 P640 MEMBAR !#1 N2176 P641 ST 28 0x800008 Int BE Pri !#1 N2177 P642 MEMBAR !#1 N2178 P643 BLD 0 -1 FP BE Pri !#1 N2179 P643 BLD 1 -1 FP BE Pri !#A N2178 N2179 !#1 N2180 P643 BLD 2 -1 FP BE Pri !#1 N2181 P643 BLD 3 -1 FP BE Pri !#1 N2182 P643 BLD 4 -1 FP BE Pri !#1 N2183 P644 MEMBAR !#1 N2184 P645 BST 0 0x40000076 FP BE Pri !#1 N2185 P645 BST 1 0x40000077 FP BE Pri !#A N2184 N2185 !#1 N2186 P645 BST 2 0x40000078 FP BE Pri !#1 N2187 P645 BST 3 0x40000079 FP BE Pri !#1 N2188 P645 BST 4 0x4000007a FP BE Pri !#1 N2189 P646 MEMBAR !#1 N2190 P647 REPLACEMENT 3 Int BE Pri !#1 N2191 P648 LD 8 -1 FP BE Sec !#1 N2192 P649 ST 8 0x800009 Int BE Pri !#1 N2193 P650 MEMBAR !#1 N2194 P651 BLD 18 -1 FP BE Pri !#1 N2195 P652 MEMBAR !#1 N2196 P653 ST 13 0x4000007b FP BE Pri !#1 N2197 P654 REPLACEMENT 17 Int BE Nuc !#1 N2198 P655 ST 19 0x80000a Int BE Pri !#1 N2199 P656 MEMBAR !#1 N2200 P657 BLD 19 -1 FP BE Pri !#1 N2201 P658 MEMBAR !#1 N2202 P659 BLD 5 -1 FP BE Pri !#1 N2203 P659 BLD 6 -1 FP BE Pri !#1 N2204 P660 MEMBAR !#1 N2205 P661 BST 5 0x4000007c FP BE Pri !#1 N2206 P661 BST 6 0x4000007d FP BE Pri !#1 N2207 P662 MEMBAR !#1 N2208 P663 BLD 30 -1 FP BE Pri !#1 N2209 P664 MEMBAR !#1 N2210 P665 REPLACEMENT 24 Int BE Pri !#1 N2211 P666 MEMBAR !#1 N2212 P667 BSTC 16 0x4000007e FP BE Pri !#1 N2213 P668 MEMBAR !#1 N2214 P669 LD 7 -1 Int BE Pri !#1 N2215 P670 LD 19 -1 FP BE Pri !#1 N2216 P671 MEMBAR !#1 N2217 P672 BLD 24 -1 FP BE Pri !#1 N2218 P672 BLD 25 -1 FP BE Pri !#1 N2219 P673 MEMBAR !#1 N2220 P674 IDC_FLIP 2 Int BE Pri !#1 N2221 P675 MEMBAR !#1 N2222 P676 BLD 11 -1 FP BE Pri !#1 N2223 P676 BLD 12 -1 FP BE Pri !#A N2222 N2223 !#1 N2224 P676 BLD 13 -1 FP BE Pri !#1 N2225 P677 MEMBAR !#1 N2226 P678 BST 15 0x4000007f FP BE Pri !#1 N2227 P679 MEMBAR !#1 N2228 P680 BLD 5 -1 FP BE Sec !#1 N2229 P680 BLD 6 -1 FP BE Sec !#1 N2230 P681 MEMBAR !#1 N2231 P682 BLD 21 -1 FP BE Pri !#1 N2232 P682 BLD 22 -1 FP BE Pri !#A N2231 N2232 !#1 N2233 P682 BLD 23 -1 FP BE Pri !#1 N2234 P683 MEMBAR !#1 N2235 P684 REPLACEMENT 23 Int BE Pri !#1 N2236 P685 MEMBAR !#1 N2237 P686 BST 5 0x40000080 FP BE Sec !#1 N2238 P686 BST 6 0x40000081 FP BE Sec !#1 N2239 P687 MEMBAR !#1 N2240 P688 BSTC 11 0x40000082 FP BE Pri !#1 N2241 P688 BSTC 12 0x40000083 FP BE Pri !#A N2240 N2241 !#1 N2242 P688 BSTC 13 0x40000084 FP BE Pri !#1 N2243 P689 MEMBAR !#1 N2244 P690 REPLACEMENT 12 Int BE Nuc !#1 N2245 P691 REPLACEMENT 8 Int BE Pri !#1 N2246 P692 MEMBAR !#1 N2247 P693 BSTC 21 0x40000085 FP BE Pri !#1 N2248 P693 BSTC 22 0x40000086 FP BE Pri !#A N2247 N2248 !#1 N2249 P693 BSTC 23 0x40000087 FP BE Pri !#1 N2250 P694 MEMBAR !#1 N2251 P695 LD 25 -1 FP BE Pri !#1 N2252 P696 MEMBAR !#1 N2253 P697 BLD 15 -1 FP BE Pri !#1 N2254 P698 MEMBAR !#1 N2255 P699 ST 30 0x80000b Int BE Sec !#1 N2256 P700 REPLACEMENT 11 Int BE Nuc !#1 N2257 P701 REPLACEMENT 20 Int BE Pri !#1 N2258 P702 REPLACEMENT 9 Int BE Pri !#1 N2259 P703 MEMBAR !#1 N2260 P704 BST 11 0x40000088 FP BE Pri !#1 N2261 P704 BST 12 0x40000089 FP BE Pri !#A N2260 N2261 !#1 N2262 P704 BST 13 0x4000008a FP BE Pri !#1 N2263 P705 MEMBAR !#1 N2264 P706 LD 10 -1 Int BE Pri !#1 N2265 P707 REPLACEMENT 5 Int BE Pri !#1 N2266 P708 LD 27 -1 FP BE Sec !#1 N2267 P709 MEMBAR !#1 N2268 P710 BST 11 0x4000008b FP BE Sec !#1 N2269 P710 BST 12 0x4000008c FP BE Sec !#A N2268 N2269 !#1 N2270 P710 BST 13 0x4000008d FP BE Sec !#1 N2271 P711 MEMBAR !#1 N2272 P712 LD 17 -1 Int BE Pri Loop_exit !#1 N2273 P238 MEMBAR !#1 N2274 P239 BLD 0 -1 FP BE Pri !#1 N2275 P239 BLD 1 -1 FP BE Pri !#A N2274 N2275 !#1 N2276 P239 BLD 2 -1 FP BE Pri !#1 N2277 P239 BLD 3 -1 FP BE Pri !#1 N2278 P239 BLD 4 -1 FP BE Pri !#1 N2279 P240 MEMBAR !#1 N2280 P241 IDC_FLIP 19 Int BE Pri !#1 N2281 P242 MEMBAR !#1 N2282 P243 BLD 8 -1 FP BE Pri !#1 N2283 P243 BLD 9 -1 FP BE Pri !#1 N2284 P244 MEMBAR !#1 N2285 P245 PREFETCH 13 Int BE Pri !#1 N2286 P246 REPLACEMENT 18 Int BE Pri !#1 N2287 P247 LD 14 -1 FP BE Pri !#1 N2288 P248 MEMBAR !#1 N2289 P249 BST 16 0x4000008e FP BE Sec !#1 N2290 P250 MEMBAR !#1 N2291 P251 BLD 5 -1 FP BE Pri !#1 N2292 P251 BLD 6 -1 FP BE Pri !#1 N2293 P252 MEMBAR !#1 N2294 P253 BSTC 14 0x4000008f FP BE Pri !#1 N2295 P254 MEMBAR !#1 N2296 P255 REPLACEMENT 13 Int BE Pri !#1 N2297 P256 PREFETCH 17 Int BE Pri !#1 N2298 P257 MEMBAR !#1 N2299 P258 BST 18 0x40000090 FP BE Pri !#1 N2300 P259 MEMBAR !#1 N2301 P260 LD 24 -1 FP BE Pri !#1 N2302 P261 REPLACEMENT 24 Int BE Sec !#1 N2303 P262 MEMBAR !#1 N2304 P263 BST 24 0x40000091 FP BE Sec !#1 N2305 P263 BST 25 0x40000092 FP BE Sec !#1 N2306 P264 MEMBAR !#1 N2307 P265 LD 22 -1 Int BE Pri !#1 N2308 P266 MEMBAR !#1 N2309 P267 BST 0 0x40000093 FP BE Pri !#1 N2310 P267 BST 1 0x40000094 FP BE Pri !#A N2309 N2310 !#1 N2311 P267 BST 2 0x40000095 FP BE Pri !#1 N2312 P267 BST 3 0x40000096 FP BE Pri !#1 N2313 P267 BST 4 0x40000097 FP BE Pri !#1 N2314 P268 MEMBAR !#1 N2315 P269 BSTC 11 0x40000098 FP BE Pri !#1 N2316 P269 BSTC 12 0x40000099 FP BE Pri !#A N2315 N2316 !#1 N2317 P269 BSTC 13 0x4000009a FP BE Pri !#1 N2318 P270 MEMBAR !#1 N2319 P271 PREFETCH 31 Int BE Sec !#1 N2320 P272 LD 11 -1 Int BE Pri !#1 N2321 P273 LD 9 -1 Int BE Pri !#1 N2322 P274 REPLACEMENT 20 Int BE Pri !#1 N2323 P275 REPLACEMENT 20 Int BE Nuc !#1 N2324 P276 MEMBAR !#1 N2325 P277 BLD 21 -1 FP BE Pri !#1 N2326 P277 BLD 22 -1 FP BE Pri !#A N2325 N2326 !#1 N2327 P277 BLD 23 -1 FP BE Pri !#1 N2328 P278 MEMBAR !#1 N2329 P279 BSTC 30 0x4000009b FP BE Pri !#1 N2330 P280 MEMBAR !#1 N2331 P281 BSTC 15 0x4000009c FP BE Pri !#1 N2332 P282 MEMBAR !#1 N2333 P283 PREFETCH 12 Int BE Pri !#1 N2334 P284 LD 26 -1 FP BE Pri !#1 N2335 P285 MEMBAR !#1 N2336 P286 BLD 20 -1 FP BE Pri !#1 N2337 P287 MEMBAR !#1 N2338 P288 BST 0 0x4000009d FP BE Pri !#1 N2339 P288 BST 1 0x4000009e FP BE Pri !#A N2338 N2339 !#1 N2340 P288 BST 2 0x4000009f FP BE Pri !#1 N2341 P288 BST 3 0x400000a0 FP BE Pri !#1 N2342 P288 BST 4 0x400000a1 FP BE Pri !#1 N2343 P289 MEMBAR !#1 N2344 P290 REPLACEMENT 21 Int BE Sec !#1 N2345 P291 REPLACEMENT 1 Int BE Pri !#1 N2346 P292 REPLACEMENT 29 Int BE Pri !#1 N2347 P293 PREFETCH 25 Int LE Sec !#1 N2348 P294 MEMBAR !#1 N2349 P295 BLD 29 -1 FP BE Pri !#1 N2350 P296 MEMBAR !#1 N2351 P297 BST 33 0x400000a2 FP BE Pri !#1 N2352 P298 MEMBAR !#1 N2353 P299 BSTC 30 0x400000a3 FP BE Pri !#1 N2354 P300 MEMBAR !#1 N2355 P301 BSTC 32 0x400000a4 FP BE Sec !#1 N2356 P302 MEMBAR !#1 N2357 P303 ST 19 0x400000a5 FP BE Sec !#1 N2358 P304 MEMBAR !#1 N2359 P305 BLD 8 -1 FP BE Pri !#1 N2360 P305 BLD 9 -1 FP BE Pri !#1 N2361 P306 MEMBAR !#1 N2362 P307 BST 26 0x400000a6 FP BE Pri !#1 N2363 P307 BST 27 0x400000a7 FP BE Pri !#1 N2364 P308 MEMBAR !#1 N2365 P309 PREFETCH 28 Int BE Pri !#1 N2366 P310 REPLACEMENT 15 Int BE Pri !#1 N2367 P311 MEMBAR !#1 N2368 P312 BLD 15 -1 FP BE Sec !#1 N2369 P313 MEMBAR !#1 N2370 P314 BSTC 21 0x400000a8 FP BE Sec !#1 N2371 P314 BSTC 22 0x400000a9 FP BE Sec !#A N2370 N2371 !#1 N2372 P314 BSTC 23 0x400000aa FP BE Sec !#1 N2373 P315 MEMBAR !#1 N2374 P316 BLD 30 -1 FP BE Sec !#1 N2375 P317 MEMBAR !#1 N2376 P318 BST 17 0x400000ab FP BE Pri !#1 N2377 P319 MEMBAR !#1 N2378 P320 PREFETCH 21 Int BE Pri !#1 N2379 P321 MEMBAR !#1 N2380 P322 BLD 29 -1 FP BE Pri !#1 N2381 P323 MEMBAR !#1 N2382 P324 IDC_FLIP 6 Int BE Pri !#1 N2383 P325 REPLACEMENT 24 Int BE Nuc !#1 N2384 P326 MEMBAR !#1 N2385 P327 BLD 0 -1 FP BE Sec !#1 N2386 P327 BLD 1 -1 FP BE Sec !#A N2385 N2386 !#1 N2387 P327 BLD 2 -1 FP BE Sec !#1 N2388 P327 BLD 3 -1 FP BE Sec !#1 N2389 P327 BLD 4 -1 FP BE Sec !#1 N2390 P328 MEMBAR !#1 N2391 P329 REPLACEMENT 26 Int BE Pri !#1 N2392 P330 MEMBAR !#1 N2393 P331 BSTC 14 0x400000ac FP BE Pri !#1 N2394 P332 MEMBAR !#1 N2395 P333 BLD 11 -1 FP BE Pri !#1 N2396 P333 BLD 12 -1 FP BE Pri !#A N2395 N2396 !#1 N2397 P333 BLD 13 -1 FP BE Pri !#1 N2398 P334 MEMBAR !#1 N2399 P335 LD 8 -1 Int BE Pri !#1 N2400 P336 MEMBAR !#1 N2401 P337 BLD 11 -1 FP BE Pri !#1 N2402 P337 BLD 12 -1 FP BE Pri !#A N2401 N2402 !#1 N2403 P337 BLD 13 -1 FP BE Pri !#1 N2404 P338 MEMBAR !#1 N2405 P339 ST 21 0x80000c Int BE Pri !#1 N2406 P340 ST 17 0x400000ad FP BE Sec !#1 N2407 P341 MEMBAR !#1 N2408 P342 BLD 24 -1 FP BE Pri !#1 N2409 P342 BLD 25 -1 FP BE Pri !#1 N2410 P343 MEMBAR !#1 N2411 P344 BST 7 0x400000ae FP BE Sec !#1 N2412 P345 MEMBAR !#1 N2413 P346 BLD 28 -1 FP BE Pri !#1 N2414 P347 MEMBAR !#1 N2415 P348 ST 6 0x400000af FP BE Sec !#1 N2416 P349 MEMBAR !#1 N2417 P350 BSTC 8 0x400000b0 FP BE Pri !#1 N2418 P350 BSTC 9 0x400000b1 FP BE Pri !#1 N2419 P351 MEMBAR !#1 N2420 P352 BLD 21 -1 FP BE Pri !#1 N2421 P352 BLD 22 -1 FP BE Pri !#A N2420 N2421 !#1 N2422 P352 BLD 23 -1 FP BE Pri !#1 N2423 P353 MEMBAR !#1 N2424 P354 BLD 17 -1 FP BE Pri !#1 N2425 P355 MEMBAR !#1 N2426 P356 BSTC 10 0x400000b2 FP BE Pri !#1 N2427 P357 MEMBAR !#1 N2428 P358 REPLACEMENT 19 Int BE Pri !#1 N2429 P359 MEMBAR !#1 N2430 P360 BST 31 0x400000b3 FP BE Sec !#1 N2431 P361 MEMBAR !#1 N2432 P362 BSTC 20 0x400000b4 FP BE Sec !#1 N2433 P363 MEMBAR !#1 N2434 P364 BLD 0 -1 FP BE Pri !#1 N2435 P364 BLD 1 -1 FP BE Pri !#A N2434 N2435 !#1 N2436 P364 BLD 2 -1 FP BE Pri !#1 N2437 P364 BLD 3 -1 FP BE Pri !#1 N2438 P364 BLD 4 -1 FP BE Pri !#1 N2439 P365 MEMBAR !#1 N2440 P366 BST 5 0x400000b5 FP BE Pri !#1 N2441 P366 BST 6 0x400000b6 FP BE Pri !#1 N2442 P367 MEMBAR !#1 N2443 P368 LD 16 -1 Int BE Pri !#1 N2444 P369 REPLACEMENT 11 Int BE Nuc !#1 N2445 P370 REPLACEMENT 16 Int BE Pri !#1 N2446 P371 LD 3 -1 Int BE Pri !#1 N2447 P372 MEMBAR !#1 N2448 P373 BSTC 28 0x400000b7 FP BE Sec !#1 N2449 P374 MEMBAR !#1 N2450 P375 BSTC 24 0x400000b8 FP BE Pri !#1 N2451 P375 BSTC 25 0x400000b9 FP BE Pri !#1 N2452 P376 MEMBAR !#1 N2453 P377 BST 0 0x400000ba FP BE Pri !#1 N2454 P377 BST 1 0x400000bb FP BE Pri !#A N2453 N2454 !#1 N2455 P377 BST 2 0x400000bc FP BE Pri !#1 N2456 P377 BST 3 0x400000bd FP BE Pri !#1 N2457 P377 BST 4 0x400000be FP BE Pri !#1 N2458 P378 MEMBAR !#1 N2459 P379 BLD 10 -1 FP BE Pri !#1 N2460 P380 MEMBAR !#1 N2461 P381 REPLACEMENT 9 Int BE Pri !#1 N2462 P382 REPLACEMENT 32 Int BE Pri !#1 N2463 P383 MEMBAR !#1 N2464 P384 BSTC 31 0x400000bf FP BE Pri !#1 N2465 P385 MEMBAR !#1 N2466 P386 BSTC 5 0x400000c0 FP BE Pri !#1 N2467 P386 BSTC 6 0x400000c1 FP BE Pri !#1 N2468 P387 MEMBAR !#1 N2469 P388 LD 8 -1 Int BE Pri !#1 N2470 P389 MEMBAR !#1 N2471 P390 BSTC 5 0x400000c2 FP BE Sec !#1 N2472 P390 BSTC 6 0x400000c3 FP BE Sec !#1 N2473 P391 MEMBAR !#1 N2474 P392 LD 3 -1 FP BE Pri !#1 N2475 P393 REPLACEMENT 32 Int BE Sec !#1 N2476 P394 ST 25 0x80000d Int BE Pri !#1 N2477 P395 MEMBAR !#1 N2478 P396 BST 24 0x400000c4 FP BE Pri !#1 N2479 P396 BST 25 0x400000c5 FP BE Pri !#1 N2480 P397 MEMBAR !#1 N2481 P398 BLD 29 -1 FP BE Pri !#1 N2482 P399 MEMBAR !#1 N2483 P400 REPLACEMENT 19 Int BE Pri !#1 N2484 P401 MEMBAR !#1 N2485 P402 BLD 19 -1 FP BE Pri !#1 N2486 P403 MEMBAR !#1 N2487 P404 BSTC 19 0x400000c6 FP BE Pri !#1 N2488 P405 MEMBAR !#1 N2489 P406 LD 8 -1 Int BE Pri !#1 N2490 P407 MEMBAR !#1 N2491 P408 BLD 21 -1 FP BE Pri !#1 N2492 P408 BLD 22 -1 FP BE Pri !#A N2491 N2492 !#1 N2493 P408 BLD 23 -1 FP BE Pri !#1 N2494 P409 MEMBAR !#1 N2495 P410 BSTC 26 0x400000c7 FP BE Pri !#1 N2496 P410 BSTC 27 0x400000c8 FP BE Pri !#1 N2497 P411 MEMBAR !#1 N2498 P412 REPLACEMENT 19 Int BE Sec !#1 N2499 P413 MEMBAR !#1 N2500 P414 BLD 28 -1 FP BE Pri !#1 N2501 P415 MEMBAR !#1 N2502 P416 BSTC 11 0x400000c9 FP BE Pri !#1 N2503 P416 BSTC 12 0x400000ca FP BE Pri !#A N2502 N2503 !#1 N2504 P416 BSTC 13 0x400000cb FP BE Pri !#1 N2505 P417 MEMBAR !#1 N2506 P418 BSTC 32 0x400000cc FP BE Pri !#1 N2507 P419 MEMBAR !#1 N2508 P420 BSTC 0 0x400000cd FP BE Pri !#1 N2509 P420 BSTC 1 0x400000ce FP BE Pri !#A N2508 N2509 !#1 N2510 P420 BSTC 2 0x400000cf FP BE Pri !#1 N2511 P420 BSTC 3 0x400000d0 FP BE Pri !#1 N2512 P420 BSTC 4 0x400000d1 FP BE Pri !#1 N2513 P421 MEMBAR !#1 N2514 P422 BLD 31 -1 FP BE Pri !#1 N2515 P423 MEMBAR !#1 N2516 P424 ST 27 0x400000d2 FP BE Pri !#1 N2517 P425 MEMBAR !#1 N2518 P426 BSTC 8 0x400000d3 FP BE Pri !#1 N2519 P426 BSTC 9 0x400000d4 FP BE Pri !#1 N2520 P427 MEMBAR !#1 N2521 P428 PREFETCH 3 Int BE Nuc !#1 N2522 P429 REPLACEMENT 16 Int BE Sec !#1 N2523 P430 MEMBAR !#1 N2524 P431 BST 0 0x400000d5 FP BE Pri !#1 N2525 P431 BST 1 0x400000d6 FP BE Pri !#A N2524 N2525 !#1 N2526 P431 BST 2 0x400000d7 FP BE Pri !#1 N2527 P431 BST 3 0x400000d8 FP BE Pri !#1 N2528 P431 BST 4 0x400000d9 FP BE Pri !#1 N2529 P432 MEMBAR !#1 N2530 P433 ST 23 0x80000e Int BE Sec !#1 N2531 P434 MEMBAR !#1 N2532 P435 BST 26 0x400000da FP BE Pri !#1 N2533 P435 BST 27 0x400000db FP BE Pri !#1 N2534 P436 MEMBAR !#1 N2535 P437 LD 11 -1 FP BE Sec !#1 N2536 P438 LD 5 -1 FP BE Pri !#1 N2537 P439 LD 11 -1 Int BE Pri !#1 N2538 P440 LD 31 -1 FP BE Pri !#1 N2539 P441 LD 12 -1 FP BE Pri !#1 N2540 P442 REPLACEMENT 23 Int BE Sec !#1 N2541 P443 MEMBAR !#1 N2542 P444 BSTC 20 0x400000dc FP BE Pri !#1 N2543 P445 MEMBAR !#1 N2544 P446 BLD 0 -1 FP BE Pri !#1 N2545 P446 BLD 1 -1 FP BE Pri !#A N2544 N2545 !#1 N2546 P446 BLD 2 -1 FP BE Pri !#1 N2547 P446 BLD 3 -1 FP BE Pri !#1 N2548 P446 BLD 4 -1 FP BE Pri !#1 N2549 P447 MEMBAR !#1 N2550 P448 BSTC 5 0x400000dd FP BE Pri !#1 N2551 P448 BSTC 6 0x400000de FP BE Pri !#1 N2552 P449 MEMBAR !#1 N2553 P450 REPLACEMENT 20 Int BE Sec !#1 N2554 P451 MEMBAR !#1 N2555 P452 BLD 5 -1 FP BE Pri !#1 N2556 P452 BLD 6 -1 FP BE Pri !#1 N2557 P453 MEMBAR !#1 N2558 P454 PREFETCH 23 Int BE Pri !#1 N2559 P455 PREFETCH 5 Int BE Pri !#1 N2560 P456 PREFETCH 27 Int BE Sec !#1 N2561 P457 MEMBAR !#1 N2562 P458 BSTC 29 0x400000df FP BE Pri !#1 N2563 P459 MEMBAR !#1 N2564 P460 BST 11 0x400000e0 FP BE Pri !#1 N2565 P460 BST 12 0x400000e1 FP BE Pri !#A N2564 N2565 !#1 N2566 P460 BST 13 0x400000e2 FP BE Pri !#1 N2567 P461 MEMBAR !#1 N2568 P462 BSTC 15 0x400000e3 FP BE Pri !#1 N2569 P463 MEMBAR !#1 N2570 P464 REPLACEMENT 8 Int BE Pri !#1 N2571 P465 PREFETCH 7 Int BE Sec !#1 N2572 P466 MEMBAR !#1 N2573 P467 BLD 14 -1 FP BE Pri !#1 N2574 P468 MEMBAR !#1 N2575 P469 BST 14 0x400000e4 FP BE Pri !#1 N2576 P470 MEMBAR !#1 N2577 P471 REPLACEMENT 8 Int BE Pri !#1 N2578 P472 MEMBAR !#1 N2579 P473 BLD 24 -1 FP BE Pri !#1 N2580 P473 BLD 25 -1 FP BE Pri !#1 N2581 P474 MEMBAR !#1 N2582 P475 BLD 5 -1 FP BE Pri !#1 N2583 P475 BLD 6 -1 FP BE Pri !#1 N2584 P476 MEMBAR !#1 N2585 P477 PREFETCH 12 Int BE Pri !#1 N2586 P478 REPLACEMENT 20 Int BE Pri !#1 N2587 P479 REPLACEMENT 5 Int BE Pri !#1 N2588 P480 ST 28 0x80000f Int BE Sec !#1 N2589 P481 MEMBAR !#1 N2590 P482 BLD 30 -1 FP BE Pri !#1 N2591 P483 MEMBAR !#1 N2592 P484 REPLACEMENT 13 Int BE Sec !#1 N2593 P485 MEMBAR !#1 N2594 P486 BST 11 0x400000e5 FP BE Pri !#1 N2595 P486 BST 12 0x400000e6 FP BE Pri !#A N2594 N2595 !#1 N2596 P486 BST 13 0x400000e7 FP BE Pri !#1 N2597 P487 MEMBAR !#1 N2598 P488 ST 24 0x400000e8 FP BE Pri !#1 N2599 P489 MEMBAR !#1 N2600 P490 BSTC 20 0x400000e9 FP BE Pri !#1 N2601 P491 MEMBAR !#1 N2602 P492 BLD 16 -1 FP BE Pri !#1 N2603 P493 MEMBAR !#1 N2604 P494 BLD 0 -1 FP BE Pri !#1 N2605 P494 BLD 1 -1 FP BE Pri !#A N2604 N2605 !#1 N2606 P494 BLD 2 -1 FP BE Pri !#1 N2607 P494 BLD 3 -1 FP BE Pri !#1 N2608 P494 BLD 4 -1 FP BE Pri !#1 N2609 P495 MEMBAR !#1 N2610 P496 PREFETCH 5 Int BE Pri !#1 N2611 P497 MEMBAR !#1 N2612 P498 BLD 28 -1 FP BE Pri !#1 N2613 P499 MEMBAR !#1 N2614 P500 BLD 0 -1 FP BE Pri !#1 N2615 P500 BLD 1 -1 FP BE Pri !#A N2614 N2615 !#1 N2616 P500 BLD 2 -1 FP BE Pri !#1 N2617 P500 BLD 3 -1 FP BE Pri !#1 N2618 P500 BLD 4 -1 FP BE Pri !#1 N2619 P501 MEMBAR !#1 N2620 P502 REPLACEMENT 11 Int BE Pri !#1 N2621 P503 LD 13 -1 Int BE Pri !#1 N2622 P504 MEMBAR !#1 N2623 P505 BST 31 0x400000ea FP BE Pri !#1 N2624 P506 MEMBAR !#1 N2625 P507 BLD 0 -1 FP BE Sec !#1 N2626 P507 BLD 1 -1 FP BE Sec !#A N2625 N2626 !#1 N2627 P507 BLD 2 -1 FP BE Sec !#1 N2628 P507 BLD 3 -1 FP BE Sec !#1 N2629 P507 BLD 4 -1 FP BE Sec !#1 N2630 P508 MEMBAR !#1 N2631 P509 BLD 19 -1 FP BE Pri !#1 N2632 P510 MEMBAR !#1 N2633 P511 BLD 20 -1 FP BE Pri !#1 N2634 P512 MEMBAR !#1 N2635 P513 ST 26 0x800010 Int BE Pri !#1 N2636 P514 MEMBAR !#1 N2637 P515 BLD 11 -1 FP BE Pri !#1 N2638 P515 BLD 12 -1 FP BE Pri !#A N2637 N2638 !#1 N2639 P515 BLD 13 -1 FP BE Pri !#1 N2640 P516 MEMBAR !#1 N2641 P517 ST 3 0x400000eb FP BE Pri !#1 N2642 P518 ST 27 0x800011 Int BE Pri !#1 N2643 P519 MEMBAR !#1 N2644 P520 BLD 8 -1 FP BE Pri !#1 N2645 P520 BLD 9 -1 FP BE Pri !#1 N2646 P521 MEMBAR !#1 N2647 P522 BST 29 0x400000ec FP BE Pri !#1 N2648 P523 MEMBAR !#1 N2649 P524 LD 33 -1 Int BE Pri !#1 N2650 P525 PREFETCH 23 Int BE Pri !#1 N2651 P526 ST 30 0x400000ed FP BE Pri !#1 N2652 P527 ST 33 0x400000ee FP BE Pri !#1 N2653 P528 ST 16 0x800012 Int BE Nuc !#1 N2654 P529 LD 9 -1 FP BE Pri !#1 N2655 P530 MEMBAR !#1 N2656 P531 BST 7 0x400000ef FP BE Pri !#1 N2657 P532 MEMBAR !#1 N2658 P533 BLD 30 -1 FP BE Pri !#1 N2659 P534 MEMBAR !#1 N2660 P535 LD 20 -1 Int BE Nuc !#1 N2661 P536 IDC_FLIP 13 Int BE Pri !#1 N2662 P537 REPLACEMENT 19 Int BE Pri !#1 N2663 P538 MEMBAR !#1 N2664 P539 BLD 10 -1 FP BE Sec !#1 N2665 P540 MEMBAR !#1 N2666 P541 IDC_FLIP 21 Int BE Pri !#1 N2667 P542 REPLACEMENT 2 Int BE Sec !#1 N2668 P543 PREFETCH 6 Int LE Pri !#1 N2669 P544 PREFETCH 4 Int BE Pri !#1 N2670 P545 MEMBAR !#1 N2671 P546 BLD 11 -1 FP BE Pri !#1 N2672 P546 BLD 12 -1 FP BE Pri !#A N2671 N2672 !#1 N2673 P546 BLD 13 -1 FP BE Pri !#1 N2674 P547 MEMBAR !#1 N2675 P548 LD 21 -1 Int BE Sec !#1 N2676 P549 PREFETCH 16 Int BE Pri !#1 N2677 P550 LD 5 -1 FP BE Pri !#1 N2678 P551 MEMBAR !#1 N2679 P552 BLD 0 -1 FP BE Sec !#1 N2680 P552 BLD 1 -1 FP BE Sec !#A N2679 N2680 !#1 N2681 P552 BLD 2 -1 FP BE Sec !#1 N2682 P552 BLD 3 -1 FP BE Sec !#1 N2683 P552 BLD 4 -1 FP BE Sec !#1 N2684 P553 MEMBAR !#1 N2685 P554 BLD 24 -1 FP BE Pri !#1 N2686 P554 BLD 25 -1 FP BE Pri !#1 N2687 P555 MEMBAR !#1 N2688 P556 IDC_FLIP 22 Int BE Pri !#1 N2689 P557 MEMBAR !#1 N2690 P558 BLD 24 -1 FP BE Pri !#1 N2691 P558 BLD 25 -1 FP BE Pri !#1 N2692 P559 MEMBAR !#1 N2693 P560 BSTC 18 0x400000f0 FP BE Pri !#1 N2694 P561 MEMBAR !#1 N2695 P562 REPLACEMENT 17 Int BE Sec !#1 N2696 P563 MEMBAR !#1 N2697 P564 BLD 29 -1 FP BE Pri !#1 N2698 P565 MEMBAR !#1 N2699 P566 BST 17 0x400000f1 FP BE Sec !#1 N2700 P567 MEMBAR !#1 N2701 P568 PREFETCH 19 Int BE Pri !#1 N2702 P569 REPLACEMENT 22 Int BE Pri !#1 N2703 P570 MEMBAR !#1 N2704 P571 BLD 31 -1 FP BE Pri !#1 N2705 P572 MEMBAR !#1 N2706 P573 PREFETCH 31 Int BE Pri !#1 N2707 P574 LD 23 -1 Int BE Pri !#1 N2708 P575 MEMBAR !#1 N2709 P576 BLD 24 -1 FP BE Pri !#1 N2710 P576 BLD 25 -1 FP BE Pri !#1 N2711 P577 MEMBAR !#1 N2712 P578 PREFETCH 26 Int BE Pri !#1 N2713 P579 LD 2 -1 FP BE Pri !#1 N2714 P580 MEMBAR !#1 N2715 P581 BSTC 32 0x400000f2 FP BE Pri !#1 N2716 P582 MEMBAR !#1 N2717 P583 LD 0 -1 Int LE Pri !#1 N2718 P584 MEMBAR !#1 N2719 P585 BSTC 26 0x400000f3 FP BE Pri !#1 N2720 P585 BSTC 27 0x400000f4 FP BE Pri !#1 N2721 P586 MEMBAR !#1 N2722 P587 BST 14 0x400000f5 FP BE Pri !#1 N2723 P588 MEMBAR !#1 N2724 P589 BLD 10 -1 FP BE Sec !#1 N2725 P590 MEMBAR !#1 N2726 P591 PREFETCH 0 Int BE Pri !#1 N2727 P592 REPLACEMENT 18 Int BE Pri !#1 N2728 P593 MEMBAR !#1 N2729 P594 BLD 8 -1 FP BE Pri !#1 N2730 P594 BLD 9 -1 FP BE Pri !#1 N2731 P595 MEMBAR !#1 N2732 P596 REPLACEMENT 18 Int BE Pri !#1 N2733 P597 MEMBAR !#1 N2734 P598 BST 0 0x400000f6 FP BE Pri !#1 N2735 P598 BST 1 0x400000f7 FP BE Pri !#A N2734 N2735 !#1 N2736 P598 BST 2 0x400000f8 FP BE Pri !#1 N2737 P598 BST 3 0x400000f9 FP BE Pri !#1 N2738 P598 BST 4 0x400000fa FP BE Pri !#1 N2739 P599 MEMBAR !#1 N2740 P600 BST 5 0x400000fb FP BE Pri !#1 N2741 P600 BST 6 0x400000fc FP BE Pri !#1 N2742 P601 MEMBAR !#1 N2743 P602 BLD 15 -1 FP BE Pri !#1 N2744 P603 MEMBAR !#1 N2745 P604 REPLACEMENT 33 Int BE Pri !#1 N2746 P605 MEMBAR !#1 N2747 P606 BLD 0 -1 FP BE Pri !#1 N2748 P606 BLD 1 -1 FP BE Pri !#A N2747 N2748 !#1 N2749 P606 BLD 2 -1 FP BE Pri !#1 N2750 P606 BLD 3 -1 FP BE Pri !#1 N2751 P606 BLD 4 -1 FP BE Pri !#1 N2752 P607 MEMBAR !#1 N2753 P608 REPLACEMENT 21 Int BE Pri !#1 N2754 P609 MEMBAR !#1 N2755 P610 BLD 15 -1 FP BE Pri !#1 N2756 P611 MEMBAR !#1 N2757 P612 REPLACEMENT 29 Int BE Pri !#1 N2758 P613 LD 28 -1 Int BE Nuc !#1 N2759 P614 MEMBAR !#1 N2760 P615 BLD 24 -1 FP BE Pri !#1 N2761 P615 BLD 25 -1 FP BE Pri !#1 N2762 P616 MEMBAR !#1 N2763 P617 ST 23 0x400000fd FP BE Pri !#1 N2764 P618 MEMBAR !#1 N2765 P619 BST 19 0x400000fe FP BE Pri !#1 N2766 P620 MEMBAR !#1 N2767 P621 BLD 5 -1 FP BE Pri !#1 N2768 P621 BLD 6 -1 FP BE Pri !#1 N2769 P622 MEMBAR !#1 N2770 P623 BST 24 0x400000ff FP BE Pri !#1 N2771 P623 BST 25 0x40000100 FP BE Pri !#1 N2772 P624 MEMBAR !#1 N2773 P625 PREFETCH 23 Int BE Sec !#1 N2774 P626 MEMBAR !#1 N2775 P627 BLD 0 -1 FP BE Pri !#1 N2776 P627 BLD 1 -1 FP BE Pri !#A N2775 N2776 !#1 N2777 P627 BLD 2 -1 FP BE Pri !#1 N2778 P627 BLD 3 -1 FP BE Pri !#1 N2779 P627 BLD 4 -1 FP BE Pri !#1 N2780 P628 MEMBAR !#1 N2781 P629 BST 24 0x40000101 FP BE Pri !#1 N2782 P629 BST 25 0x40000102 FP BE Pri !#1 N2783 P630 MEMBAR !#1 N2784 P631 BLD 21 -1 FP BE Pri !#1 N2785 P631 BLD 22 -1 FP BE Pri !#A N2784 N2785 !#1 N2786 P631 BLD 23 -1 FP BE Pri !#1 N2787 P632 MEMBAR !#1 N2788 P633 BLD 20 -1 FP BE Pri !#1 N2789 P634 MEMBAR !#1 N2790 P635 REPLACEMENT 27 Int BE Pri !#1 N2791 P636 REPLACEMENT 33 Int BE Sec !#1 N2792 P637 LD 7 -1 Int BE Pri !#1 N2793 P638 MEMBAR !#1 N2794 P639 BLD 26 -1 FP BE Pri !#1 N2795 P639 BLD 27 -1 FP BE Pri !#1 N2796 P640 MEMBAR !#1 N2797 P641 ST 28 0x800013 Int BE Pri !#1 N2798 P642 MEMBAR !#1 N2799 P643 BLD 0 -1 FP BE Pri !#1 N2800 P643 BLD 1 -1 FP BE Pri !#A N2799 N2800 !#1 N2801 P643 BLD 2 -1 FP BE Pri !#1 N2802 P643 BLD 3 -1 FP BE Pri !#1 N2803 P643 BLD 4 -1 FP BE Pri !#1 N2804 P644 MEMBAR !#1 N2805 P645 BST 0 0x40000103 FP BE Pri !#1 N2806 P645 BST 1 0x40000104 FP BE Pri !#A N2805 N2806 !#1 N2807 P645 BST 2 0x40000105 FP BE Pri !#1 N2808 P645 BST 3 0x40000106 FP BE Pri !#1 N2809 P645 BST 4 0x40000107 FP BE Pri !#1 N2810 P646 MEMBAR !#1 N2811 P647 REPLACEMENT 3 Int BE Pri !#1 N2812 P648 LD 8 -1 FP BE Sec !#1 N2813 P649 ST 8 0x800014 Int BE Pri !#1 N2814 P650 MEMBAR !#1 N2815 P651 BLD 18 -1 FP BE Pri !#1 N2816 P652 MEMBAR !#1 N2817 P653 ST 13 0x40000108 FP BE Pri !#1 N2818 P654 REPLACEMENT 17 Int BE Nuc !#1 N2819 P655 ST 19 0x800015 Int BE Pri !#1 N2820 P656 MEMBAR !#1 N2821 P657 BLD 19 -1 FP BE Pri !#1 N2822 P658 MEMBAR !#1 N2823 P659 BLD 5 -1 FP BE Pri !#1 N2824 P659 BLD 6 -1 FP BE Pri !#1 N2825 P660 MEMBAR !#1 N2826 P661 BST 5 0x40000109 FP BE Pri !#1 N2827 P661 BST 6 0x4000010a FP BE Pri !#1 N2828 P662 MEMBAR !#1 N2829 P663 BLD 30 -1 FP BE Pri !#1 N2830 P664 MEMBAR !#1 N2831 P665 REPLACEMENT 24 Int BE Pri !#1 N2832 P666 MEMBAR !#1 N2833 P667 BSTC 16 0x4000010b FP BE Pri !#1 N2834 P668 MEMBAR !#1 N2835 P669 LD 7 -1 Int BE Pri !#1 N2836 P670 LD 19 -1 FP BE Pri !#1 N2837 P671 MEMBAR !#1 N2838 P672 BLD 24 -1 FP BE Pri !#1 N2839 P672 BLD 25 -1 FP BE Pri !#1 N2840 P673 MEMBAR !#1 N2841 P674 IDC_FLIP 2 Int BE Pri !#1 N2842 P675 MEMBAR !#1 N2843 P676 BLD 11 -1 FP BE Pri !#1 N2844 P676 BLD 12 -1 FP BE Pri !#A N2843 N2844 !#1 N2845 P676 BLD 13 -1 FP BE Pri !#1 N2846 P677 MEMBAR !#1 N2847 P678 BST 15 0x4000010c FP BE Pri !#1 N2848 P679 MEMBAR !#1 N2849 P680 BLD 5 -1 FP BE Sec !#1 N2850 P680 BLD 6 -1 FP BE Sec !#1 N2851 P681 MEMBAR !#1 N2852 P682 BLD 21 -1 FP BE Pri !#1 N2853 P682 BLD 22 -1 FP BE Pri !#A N2852 N2853 !#1 N2854 P682 BLD 23 -1 FP BE Pri !#1 N2855 P683 MEMBAR !#1 N2856 P684 REPLACEMENT 23 Int BE Pri !#1 N2857 P685 MEMBAR !#1 N2858 P686 BST 5 0x4000010d FP BE Sec !#1 N2859 P686 BST 6 0x4000010e FP BE Sec !#1 N2860 P687 MEMBAR !#1 N2861 P688 BSTC 11 0x4000010f FP BE Pri !#1 N2862 P688 BSTC 12 0x40000110 FP BE Pri !#A N2861 N2862 !#1 N2863 P688 BSTC 13 0x40000111 FP BE Pri !#1 N2864 P689 MEMBAR !#1 N2865 P690 REPLACEMENT 12 Int BE Nuc !#1 N2866 P691 REPLACEMENT 8 Int BE Pri !#1 N2867 P692 MEMBAR !#1 N2868 P693 BSTC 21 0x40000112 FP BE Pri !#1 N2869 P693 BSTC 22 0x40000113 FP BE Pri !#A N2868 N2869 !#1 N2870 P693 BSTC 23 0x40000114 FP BE Pri !#1 N2871 P694 MEMBAR !#1 N2872 P695 LD 25 -1 FP BE Pri !#1 N2873 P696 MEMBAR !#1 N2874 P697 BLD 15 -1 FP BE Pri !#1 N2875 P698 MEMBAR !#1 N2876 P699 ST 30 0x800016 Int BE Sec !#1 N2877 P700 REPLACEMENT 11 Int BE Nuc !#1 N2878 P701 REPLACEMENT 20 Int BE Pri !#1 N2879 P702 REPLACEMENT 9 Int BE Pri !#1 N2880 P703 MEMBAR !#1 N2881 P704 BST 11 0x40000115 FP BE Pri !#1 N2882 P704 BST 12 0x40000116 FP BE Pri !#A N2881 N2882 !#1 N2883 P704 BST 13 0x40000117 FP BE Pri !#1 N2884 P705 MEMBAR !#1 N2885 P706 LD 10 -1 Int BE Pri !#1 N2886 P707 REPLACEMENT 5 Int BE Pri !#1 N2887 P708 LD 27 -1 FP BE Sec !#1 N2888 P709 MEMBAR !#1 N2889 P710 BST 11 0x40000118 FP BE Sec !#1 N2890 P710 BST 12 0x40000119 FP BE Sec !#A N2889 N2890 !#1 N2891 P710 BST 13 0x4000011a FP BE Sec !#1 N2892 P711 MEMBAR !#1 N2893 P712 LD 17 -1 Int BE Pri Loop_exit !#1 N2894 P238 MEMBAR !#1 N2895 P239 BLD 0 -1 FP BE Pri !#1 N2896 P239 BLD 1 -1 FP BE Pri !#A N2895 N2896 !#1 N2897 P239 BLD 2 -1 FP BE Pri !#1 N2898 P239 BLD 3 -1 FP BE Pri !#1 N2899 P239 BLD 4 -1 FP BE Pri !#1 N2900 P240 MEMBAR !#1 N2901 P241 IDC_FLIP 19 Int BE Pri !#1 N2902 P242 MEMBAR !#1 N2903 P243 BLD 8 -1 FP BE Pri !#1 N2904 P243 BLD 9 -1 FP BE Pri !#1 N2905 P244 MEMBAR !#1 N2906 P245 PREFETCH 13 Int BE Pri !#1 N2907 P246 REPLACEMENT 18 Int BE Pri !#1 N2908 P247 LD 14 -1 FP BE Pri !#1 N2909 P248 MEMBAR !#1 N2910 P249 BST 16 0x4000011b FP BE Sec !#1 N2911 P250 MEMBAR !#1 N2912 P251 BLD 5 -1 FP BE Pri !#1 N2913 P251 BLD 6 -1 FP BE Pri !#1 N2914 P252 MEMBAR !#1 N2915 P253 BSTC 14 0x4000011c FP BE Pri !#1 N2916 P254 MEMBAR !#1 N2917 P255 REPLACEMENT 13 Int BE Pri !#1 N2918 P256 PREFETCH 17 Int BE Pri !#1 N2919 P257 MEMBAR !#1 N2920 P258 BST 18 0x4000011d FP BE Pri !#1 N2921 P259 MEMBAR !#1 N2922 P260 LD 24 -1 FP BE Pri !#1 N2923 P261 REPLACEMENT 24 Int BE Sec !#1 N2924 P262 MEMBAR !#1 N2925 P263 BST 24 0x4000011e FP BE Sec !#1 N2926 P263 BST 25 0x4000011f FP BE Sec !#1 N2927 P264 MEMBAR !#1 N2928 P265 LD 22 -1 Int BE Pri !#1 N2929 P266 MEMBAR !#1 N2930 P267 BST 0 0x40000120 FP BE Pri !#1 N2931 P267 BST 1 0x40000121 FP BE Pri !#A N2930 N2931 !#1 N2932 P267 BST 2 0x40000122 FP BE Pri !#1 N2933 P267 BST 3 0x40000123 FP BE Pri !#1 N2934 P267 BST 4 0x40000124 FP BE Pri !#1 N2935 P268 MEMBAR !#1 N2936 P269 BSTC 11 0x40000125 FP BE Pri !#1 N2937 P269 BSTC 12 0x40000126 FP BE Pri !#A N2936 N2937 !#1 N2938 P269 BSTC 13 0x40000127 FP BE Pri !#1 N2939 P270 MEMBAR !#1 N2940 P271 PREFETCH 31 Int BE Sec !#1 N2941 P272 LD 11 -1 Int BE Pri !#1 N2942 P273 LD 9 -1 Int BE Pri !#1 N2943 P274 REPLACEMENT 20 Int BE Pri !#1 N2944 P275 REPLACEMENT 20 Int BE Nuc !#1 N2945 P276 MEMBAR !#1 N2946 P277 BLD 21 -1 FP BE Pri !#1 N2947 P277 BLD 22 -1 FP BE Pri !#A N2946 N2947 !#1 N2948 P277 BLD 23 -1 FP BE Pri !#1 N2949 P278 MEMBAR !#1 N2950 P279 BSTC 30 0x40000128 FP BE Pri !#1 N2951 P280 MEMBAR !#1 N2952 P281 BSTC 15 0x40000129 FP BE Pri !#1 N2953 P282 MEMBAR !#1 N2954 P283 PREFETCH 12 Int BE Pri !#1 N2955 P284 LD 26 -1 FP BE Pri !#1 N2956 P285 MEMBAR !#1 N2957 P286 BLD 20 -1 FP BE Pri !#1 N2958 P287 MEMBAR !#1 N2959 P288 BST 0 0x4000012a FP BE Pri !#1 N2960 P288 BST 1 0x4000012b FP BE Pri !#A N2959 N2960 !#1 N2961 P288 BST 2 0x4000012c FP BE Pri !#1 N2962 P288 BST 3 0x4000012d FP BE Pri !#1 N2963 P288 BST 4 0x4000012e FP BE Pri !#1 N2964 P289 MEMBAR !#1 N2965 P290 REPLACEMENT 21 Int BE Sec !#1 N2966 P291 REPLACEMENT 1 Int BE Pri !#1 N2967 P292 REPLACEMENT 29 Int BE Pri !#1 N2968 P293 PREFETCH 25 Int LE Sec !#1 N2969 P294 MEMBAR !#1 N2970 P295 BLD 29 -1 FP BE Pri !#1 N2971 P296 MEMBAR !#1 N2972 P297 BST 33 0x4000012f FP BE Pri !#1 N2973 P298 MEMBAR !#1 N2974 P299 BSTC 30 0x40000130 FP BE Pri !#1 N2975 P300 MEMBAR !#1 N2976 P301 BSTC 32 0x40000131 FP BE Sec !#1 N2977 P302 MEMBAR !#1 N2978 P303 ST 19 0x40000132 FP BE Sec !#1 N2979 P304 MEMBAR !#1 N2980 P305 BLD 8 -1 FP BE Pri !#1 N2981 P305 BLD 9 -1 FP BE Pri !#1 N2982 P306 MEMBAR !#1 N2983 P307 BST 26 0x40000133 FP BE Pri !#1 N2984 P307 BST 27 0x40000134 FP BE Pri !#1 N2985 P308 MEMBAR !#1 N2986 P309 PREFETCH 28 Int BE Pri !#1 N2987 P310 REPLACEMENT 15 Int BE Pri !#1 N2988 P311 MEMBAR !#1 N2989 P312 BLD 15 -1 FP BE Sec !#1 N2990 P313 MEMBAR !#1 N2991 P314 BSTC 21 0x40000135 FP BE Sec !#1 N2992 P314 BSTC 22 0x40000136 FP BE Sec !#A N2991 N2992 !#1 N2993 P314 BSTC 23 0x40000137 FP BE Sec !#1 N2994 P315 MEMBAR !#1 N2995 P316 BLD 30 -1 FP BE Sec !#1 N2996 P317 MEMBAR !#1 N2997 P318 BST 17 0x40000138 FP BE Pri !#1 N2998 P319 MEMBAR !#1 N2999 P320 PREFETCH 21 Int BE Pri !#1 N3000 P321 MEMBAR !#1 N3001 P322 BLD 29 -1 FP BE Pri !#1 N3002 P323 MEMBAR !#1 N3003 P324 IDC_FLIP 6 Int BE Pri !#1 N3004 P325 REPLACEMENT 24 Int BE Nuc !#1 N3005 P326 MEMBAR !#1 N3006 P327 BLD 0 -1 FP BE Sec !#1 N3007 P327 BLD 1 -1 FP BE Sec !#A N3006 N3007 !#1 N3008 P327 BLD 2 -1 FP BE Sec !#1 N3009 P327 BLD 3 -1 FP BE Sec !#1 N3010 P327 BLD 4 -1 FP BE Sec !#1 N3011 P328 MEMBAR !#1 N3012 P329 REPLACEMENT 26 Int BE Pri !#1 N3013 P330 MEMBAR !#1 N3014 P331 BSTC 14 0x40000139 FP BE Pri !#1 N3015 P332 MEMBAR !#1 N3016 P333 BLD 11 -1 FP BE Pri !#1 N3017 P333 BLD 12 -1 FP BE Pri !#A N3016 N3017 !#1 N3018 P333 BLD 13 -1 FP BE Pri !#1 N3019 P334 MEMBAR !#1 N3020 P335 LD 8 -1 Int BE Pri !#1 N3021 P336 MEMBAR !#1 N3022 P337 BLD 11 -1 FP BE Pri !#1 N3023 P337 BLD 12 -1 FP BE Pri !#A N3022 N3023 !#1 N3024 P337 BLD 13 -1 FP BE Pri !#1 N3025 P338 MEMBAR !#1 N3026 P339 ST 21 0x800017 Int BE Pri !#1 N3027 P340 ST 17 0x4000013a FP BE Sec !#1 N3028 P341 MEMBAR !#1 N3029 P342 BLD 24 -1 FP BE Pri !#1 N3030 P342 BLD 25 -1 FP BE Pri !#1 N3031 P343 MEMBAR !#1 N3032 P344 BST 7 0x4000013b FP BE Sec !#1 N3033 P345 MEMBAR !#1 N3034 P346 BLD 28 -1 FP BE Pri !#1 N3035 P347 MEMBAR !#1 N3036 P348 ST 6 0x4000013c FP BE Sec !#1 N3037 P349 MEMBAR !#1 N3038 P350 BSTC 8 0x4000013d FP BE Pri !#1 N3039 P350 BSTC 9 0x4000013e FP BE Pri !#1 N3040 P351 MEMBAR !#1 N3041 P352 BLD 21 -1 FP BE Pri !#1 N3042 P352 BLD 22 -1 FP BE Pri !#A N3041 N3042 !#1 N3043 P352 BLD 23 -1 FP BE Pri !#1 N3044 P353 MEMBAR !#1 N3045 P354 BLD 17 -1 FP BE Pri !#1 N3046 P355 MEMBAR !#1 N3047 P356 BSTC 10 0x4000013f FP BE Pri !#1 N3048 P357 MEMBAR !#1 N3049 P358 REPLACEMENT 19 Int BE Pri !#1 N3050 P359 MEMBAR !#1 N3051 P360 BST 31 0x40000140 FP BE Sec !#1 N3052 P361 MEMBAR !#1 N3053 P362 BSTC 20 0x40000141 FP BE Sec !#1 N3054 P363 MEMBAR !#1 N3055 P364 BLD 0 -1 FP BE Pri !#1 N3056 P364 BLD 1 -1 FP BE Pri !#A N3055 N3056 !#1 N3057 P364 BLD 2 -1 FP BE Pri !#1 N3058 P364 BLD 3 -1 FP BE Pri !#1 N3059 P364 BLD 4 -1 FP BE Pri !#1 N3060 P365 MEMBAR !#1 N3061 P366 BST 5 0x40000142 FP BE Pri !#1 N3062 P366 BST 6 0x40000143 FP BE Pri !#1 N3063 P367 MEMBAR !#1 N3064 P368 LD 16 -1 Int BE Pri !#1 N3065 P369 REPLACEMENT 11 Int BE Nuc !#1 N3066 P370 REPLACEMENT 16 Int BE Pri !#1 N3067 P371 LD 3 -1 Int BE Pri !#1 N3068 P372 MEMBAR !#1 N3069 P373 BSTC 28 0x40000144 FP BE Sec !#1 N3070 P374 MEMBAR !#1 N3071 P375 BSTC 24 0x40000145 FP BE Pri !#1 N3072 P375 BSTC 25 0x40000146 FP BE Pri !#1 N3073 P376 MEMBAR !#1 N3074 P377 BST 0 0x40000147 FP BE Pri !#1 N3075 P377 BST 1 0x40000148 FP BE Pri !#A N3074 N3075 !#1 N3076 P377 BST 2 0x40000149 FP BE Pri !#1 N3077 P377 BST 3 0x4000014a FP BE Pri !#1 N3078 P377 BST 4 0x4000014b FP BE Pri !#1 N3079 P378 MEMBAR !#1 N3080 P379 BLD 10 -1 FP BE Pri !#1 N3081 P380 MEMBAR !#1 N3082 P381 REPLACEMENT 9 Int BE Pri !#1 N3083 P382 REPLACEMENT 32 Int BE Pri !#1 N3084 P383 MEMBAR !#1 N3085 P384 BSTC 31 0x4000014c FP BE Pri !#1 N3086 P385 MEMBAR !#1 N3087 P386 BSTC 5 0x4000014d FP BE Pri !#1 N3088 P386 BSTC 6 0x4000014e FP BE Pri !#1 N3089 P387 MEMBAR !#1 N3090 P388 LD 8 -1 Int BE Pri !#1 N3091 P389 MEMBAR !#1 N3092 P390 BSTC 5 0x4000014f FP BE Sec !#1 N3093 P390 BSTC 6 0x40000150 FP BE Sec !#1 N3094 P391 MEMBAR !#1 N3095 P392 LD 3 -1 FP BE Pri !#1 N3096 P393 REPLACEMENT 32 Int BE Sec !#1 N3097 P394 ST 25 0x800018 Int BE Pri !#1 N3098 P395 MEMBAR !#1 N3099 P396 BST 24 0x40000151 FP BE Pri !#1 N3100 P396 BST 25 0x40000152 FP BE Pri !#1 N3101 P397 MEMBAR !#1 N3102 P398 BLD 29 -1 FP BE Pri !#1 N3103 P399 MEMBAR !#1 N3104 P400 REPLACEMENT 19 Int BE Pri !#1 N3105 P401 MEMBAR !#1 N3106 P402 BLD 19 -1 FP BE Pri !#1 N3107 P403 MEMBAR !#1 N3108 P404 BSTC 19 0x40000153 FP BE Pri !#1 N3109 P405 MEMBAR !#1 N3110 P406 LD 8 -1 Int BE Pri !#1 N3111 P407 MEMBAR !#1 N3112 P408 BLD 21 -1 FP BE Pri !#1 N3113 P408 BLD 22 -1 FP BE Pri !#A N3112 N3113 !#1 N3114 P408 BLD 23 -1 FP BE Pri !#1 N3115 P409 MEMBAR !#1 N3116 P410 BSTC 26 0x40000154 FP BE Pri !#1 N3117 P410 BSTC 27 0x40000155 FP BE Pri !#1 N3118 P411 MEMBAR !#1 N3119 P412 REPLACEMENT 19 Int BE Sec !#1 N3120 P413 MEMBAR !#1 N3121 P414 BLD 28 -1 FP BE Pri !#1 N3122 P415 MEMBAR !#1 N3123 P416 BSTC 11 0x40000156 FP BE Pri !#1 N3124 P416 BSTC 12 0x40000157 FP BE Pri !#A N3123 N3124 !#1 N3125 P416 BSTC 13 0x40000158 FP BE Pri !#1 N3126 P417 MEMBAR !#1 N3127 P418 BSTC 32 0x40000159 FP BE Pri !#1 N3128 P419 MEMBAR !#1 N3129 P420 BSTC 0 0x4000015a FP BE Pri !#1 N3130 P420 BSTC 1 0x4000015b FP BE Pri !#A N3129 N3130 !#1 N3131 P420 BSTC 2 0x4000015c FP BE Pri !#1 N3132 P420 BSTC 3 0x4000015d FP BE Pri !#1 N3133 P420 BSTC 4 0x4000015e FP BE Pri !#1 N3134 P421 MEMBAR !#1 N3135 P422 BLD 31 -1 FP BE Pri !#1 N3136 P423 MEMBAR !#1 N3137 P424 ST 27 0x4000015f FP BE Pri !#1 N3138 P425 MEMBAR !#1 N3139 P426 BSTC 8 0x40000160 FP BE Pri !#1 N3140 P426 BSTC 9 0x40000161 FP BE Pri !#1 N3141 P427 MEMBAR !#1 N3142 P428 PREFETCH 3 Int BE Nuc !#1 N3143 P429 REPLACEMENT 16 Int BE Sec !#1 N3144 P430 MEMBAR !#1 N3145 P431 BST 0 0x40000162 FP BE Pri !#1 N3146 P431 BST 1 0x40000163 FP BE Pri !#A N3145 N3146 !#1 N3147 P431 BST 2 0x40000164 FP BE Pri !#1 N3148 P431 BST 3 0x40000165 FP BE Pri !#1 N3149 P431 BST 4 0x40000166 FP BE Pri !#1 N3150 P432 MEMBAR !#1 N3151 P433 ST 23 0x800019 Int BE Sec !#1 N3152 P434 MEMBAR !#1 N3153 P435 BST 26 0x40000167 FP BE Pri !#1 N3154 P435 BST 27 0x40000168 FP BE Pri !#1 N3155 P436 MEMBAR !#1 N3156 P437 LD 11 -1 FP BE Sec !#1 N3157 P438 LD 5 -1 FP BE Pri !#1 N3158 P439 LD 11 -1 Int BE Pri !#1 N3159 P440 LD 31 -1 FP BE Pri !#1 N3160 P441 LD 12 -1 FP BE Pri !#1 N3161 P442 REPLACEMENT 23 Int BE Sec !#1 N3162 P443 MEMBAR !#1 N3163 P444 BSTC 20 0x40000169 FP BE Pri !#1 N3164 P445 MEMBAR !#1 N3165 P446 BLD 0 -1 FP BE Pri !#1 N3166 P446 BLD 1 -1 FP BE Pri !#A N3165 N3166 !#1 N3167 P446 BLD 2 -1 FP BE Pri !#1 N3168 P446 BLD 3 -1 FP BE Pri !#1 N3169 P446 BLD 4 -1 FP BE Pri !#1 N3170 P447 MEMBAR !#1 N3171 P448 BSTC 5 0x4000016a FP BE Pri !#1 N3172 P448 BSTC 6 0x4000016b FP BE Pri !#1 N3173 P449 MEMBAR !#1 N3174 P450 REPLACEMENT 20 Int BE Sec !#1 N3175 P451 MEMBAR !#1 N3176 P452 BLD 5 -1 FP BE Pri !#1 N3177 P452 BLD 6 -1 FP BE Pri !#1 N3178 P453 MEMBAR !#1 N3179 P454 PREFETCH 23 Int BE Pri !#1 N3180 P455 PREFETCH 5 Int BE Pri !#1 N3181 P456 PREFETCH 27 Int BE Sec !#1 N3182 P457 MEMBAR !#1 N3183 P458 BSTC 29 0x4000016c FP BE Pri !#1 N3184 P459 MEMBAR !#1 N3185 P460 BST 11 0x4000016d FP BE Pri !#1 N3186 P460 BST 12 0x4000016e FP BE Pri !#A N3185 N3186 !#1 N3187 P460 BST 13 0x4000016f FP BE Pri !#1 N3188 P461 MEMBAR !#1 N3189 P462 BSTC 15 0x40000170 FP BE Pri !#1 N3190 P463 MEMBAR !#1 N3191 P464 REPLACEMENT 8 Int BE Pri !#1 N3192 P465 PREFETCH 7 Int BE Sec !#1 N3193 P466 MEMBAR !#1 N3194 P467 BLD 14 -1 FP BE Pri !#1 N3195 P468 MEMBAR !#1 N3196 P469 BST 14 0x40000171 FP BE Pri !#1 N3197 P470 MEMBAR !#1 N3198 P471 REPLACEMENT 8 Int BE Pri !#1 N3199 P472 MEMBAR !#1 N3200 P473 BLD 24 -1 FP BE Pri !#1 N3201 P473 BLD 25 -1 FP BE Pri !#1 N3202 P474 MEMBAR !#1 N3203 P475 BLD 5 -1 FP BE Pri !#1 N3204 P475 BLD 6 -1 FP BE Pri !#1 N3205 P476 MEMBAR !#1 N3206 P477 PREFETCH 12 Int BE Pri !#1 N3207 P478 REPLACEMENT 20 Int BE Pri !#1 N3208 P479 REPLACEMENT 5 Int BE Pri !#1 N3209 P480 ST 28 0x80001a Int BE Sec !#1 N3210 P481 MEMBAR !#1 N3211 P482 BLD 30 -1 FP BE Pri !#1 N3212 P483 MEMBAR !#1 N3213 P484 REPLACEMENT 13 Int BE Sec !#1 N3214 P485 MEMBAR !#1 N3215 P486 BST 11 0x40000172 FP BE Pri !#1 N3216 P486 BST 12 0x40000173 FP BE Pri !#A N3215 N3216 !#1 N3217 P486 BST 13 0x40000174 FP BE Pri !#1 N3218 P487 MEMBAR !#1 N3219 P488 ST 24 0x40000175 FP BE Pri !#1 N3220 P489 MEMBAR !#1 N3221 P490 BSTC 20 0x40000176 FP BE Pri !#1 N3222 P491 MEMBAR !#1 N3223 P492 BLD 16 -1 FP BE Pri !#1 N3224 P493 MEMBAR !#1 N3225 P494 BLD 0 -1 FP BE Pri !#1 N3226 P494 BLD 1 -1 FP BE Pri !#A N3225 N3226 !#1 N3227 P494 BLD 2 -1 FP BE Pri !#1 N3228 P494 BLD 3 -1 FP BE Pri !#1 N3229 P494 BLD 4 -1 FP BE Pri !#1 N3230 P495 MEMBAR !#1 N3231 P496 PREFETCH 5 Int BE Pri !#1 N3232 P497 MEMBAR !#1 N3233 P498 BLD 28 -1 FP BE Pri !#1 N3234 P499 MEMBAR !#1 N3235 P500 BLD 0 -1 FP BE Pri !#1 N3236 P500 BLD 1 -1 FP BE Pri !#A N3235 N3236 !#1 N3237 P500 BLD 2 -1 FP BE Pri !#1 N3238 P500 BLD 3 -1 FP BE Pri !#1 N3239 P500 BLD 4 -1 FP BE Pri !#1 N3240 P501 MEMBAR !#1 N3241 P502 REPLACEMENT 11 Int BE Pri !#1 N3242 P503 LD 13 -1 Int BE Pri !#1 N3243 P504 MEMBAR !#1 N3244 P505 BST 31 0x40000177 FP BE Pri !#1 N3245 P506 MEMBAR !#1 N3246 P507 BLD 0 -1 FP BE Sec !#1 N3247 P507 BLD 1 -1 FP BE Sec !#A N3246 N3247 !#1 N3248 P507 BLD 2 -1 FP BE Sec !#1 N3249 P507 BLD 3 -1 FP BE Sec !#1 N3250 P507 BLD 4 -1 FP BE Sec !#1 N3251 P508 MEMBAR !#1 N3252 P509 BLD 19 -1 FP BE Pri !#1 N3253 P510 MEMBAR !#1 N3254 P511 BLD 20 -1 FP BE Pri !#1 N3255 P512 MEMBAR !#1 N3256 P513 ST 26 0x80001b Int BE Pri !#1 N3257 P514 MEMBAR !#1 N3258 P515 BLD 11 -1 FP BE Pri !#1 N3259 P515 BLD 12 -1 FP BE Pri !#A N3258 N3259 !#1 N3260 P515 BLD 13 -1 FP BE Pri !#1 N3261 P516 MEMBAR !#1 N3262 P517 ST 3 0x40000178 FP BE Pri !#1 N3263 P518 ST 27 0x80001c Int BE Pri !#1 N3264 P519 MEMBAR !#1 N3265 P520 BLD 8 -1 FP BE Pri !#1 N3266 P520 BLD 9 -1 FP BE Pri !#1 N3267 P521 MEMBAR !#1 N3268 P522 BST 29 0x40000179 FP BE Pri !#1 N3269 P523 MEMBAR !#1 N3270 P524 LD 33 -1 Int BE Pri !#1 N3271 P525 PREFETCH 23 Int BE Pri !#1 N3272 P526 ST 30 0x4000017a FP BE Pri !#1 N3273 P527 ST 33 0x4000017b FP BE Pri !#1 N3274 P528 ST 16 0x80001d Int BE Nuc !#1 N3275 P529 LD 9 -1 FP BE Pri !#1 N3276 P530 MEMBAR !#1 N3277 P531 BST 7 0x4000017c FP BE Pri !#1 N3278 P532 MEMBAR !#1 N3279 P533 BLD 30 -1 FP BE Pri !#1 N3280 P534 MEMBAR !#1 N3281 P535 LD 20 -1 Int BE Nuc !#1 N3282 P536 IDC_FLIP 13 Int BE Pri !#1 N3283 P537 REPLACEMENT 19 Int BE Pri !#1 N3284 P538 MEMBAR !#1 N3285 P539 BLD 10 -1 FP BE Sec !#1 N3286 P540 MEMBAR !#1 N3287 P541 IDC_FLIP 21 Int BE Pri !#1 N3288 P542 REPLACEMENT 2 Int BE Sec !#1 N3289 P543 PREFETCH 6 Int LE Pri !#1 N3290 P544 PREFETCH 4 Int BE Pri !#1 N3291 P545 MEMBAR !#1 N3292 P546 BLD 11 -1 FP BE Pri !#1 N3293 P546 BLD 12 -1 FP BE Pri !#A N3292 N3293 !#1 N3294 P546 BLD 13 -1 FP BE Pri !#1 N3295 P547 MEMBAR !#1 N3296 P548 LD 21 -1 Int BE Sec !#1 N3297 P549 PREFETCH 16 Int BE Pri !#1 N3298 P550 LD 5 -1 FP BE Pri !#1 N3299 P551 MEMBAR !#1 N3300 P552 BLD 0 -1 FP BE Sec !#1 N3301 P552 BLD 1 -1 FP BE Sec !#A N3300 N3301 !#1 N3302 P552 BLD 2 -1 FP BE Sec !#1 N3303 P552 BLD 3 -1 FP BE Sec !#1 N3304 P552 BLD 4 -1 FP BE Sec !#1 N3305 P553 MEMBAR !#1 N3306 P554 BLD 24 -1 FP BE Pri !#1 N3307 P554 BLD 25 -1 FP BE Pri !#1 N3308 P555 MEMBAR !#1 N3309 P556 IDC_FLIP 22 Int BE Pri !#1 N3310 P557 MEMBAR !#1 N3311 P558 BLD 24 -1 FP BE Pri !#1 N3312 P558 BLD 25 -1 FP BE Pri !#1 N3313 P559 MEMBAR !#1 N3314 P560 BSTC 18 0x4000017d FP BE Pri !#1 N3315 P561 MEMBAR !#1 N3316 P562 REPLACEMENT 17 Int BE Sec !#1 N3317 P563 MEMBAR !#1 N3318 P564 BLD 29 -1 FP BE Pri !#1 N3319 P565 MEMBAR !#1 N3320 P566 BST 17 0x4000017e FP BE Sec !#1 N3321 P567 MEMBAR !#1 N3322 P568 PREFETCH 19 Int BE Pri !#1 N3323 P569 REPLACEMENT 22 Int BE Pri !#1 N3324 P570 MEMBAR !#1 N3325 P571 BLD 31 -1 FP BE Pri !#1 N3326 P572 MEMBAR !#1 N3327 P573 PREFETCH 31 Int BE Pri !#1 N3328 P574 LD 23 -1 Int BE Pri !#1 N3329 P575 MEMBAR !#1 N3330 P576 BLD 24 -1 FP BE Pri !#1 N3331 P576 BLD 25 -1 FP BE Pri !#1 N3332 P577 MEMBAR !#1 N3333 P578 PREFETCH 26 Int BE Pri !#1 N3334 P579 LD 2 -1 FP BE Pri !#1 N3335 P580 MEMBAR !#1 N3336 P581 BSTC 32 0x4000017f FP BE Pri !#1 N3337 P582 MEMBAR !#1 N3338 P583 LD 0 -1 Int LE Pri !#1 N3339 P584 MEMBAR !#1 N3340 P585 BSTC 26 0x40000180 FP BE Pri !#1 N3341 P585 BSTC 27 0x40000181 FP BE Pri !#1 N3342 P586 MEMBAR !#1 N3343 P587 BST 14 0x40000182 FP BE Pri !#1 N3344 P588 MEMBAR !#1 N3345 P589 BLD 10 -1 FP BE Sec !#1 N3346 P590 MEMBAR !#1 N3347 P591 PREFETCH 0 Int BE Pri !#1 N3348 P592 REPLACEMENT 18 Int BE Pri !#1 N3349 P593 MEMBAR !#1 N3350 P594 BLD 8 -1 FP BE Pri !#1 N3351 P594 BLD 9 -1 FP BE Pri !#1 N3352 P595 MEMBAR !#1 N3353 P596 REPLACEMENT 18 Int BE Pri !#1 N3354 P597 MEMBAR !#1 N3355 P598 BST 0 0x40000183 FP BE Pri !#1 N3356 P598 BST 1 0x40000184 FP BE Pri !#A N3355 N3356 !#1 N3357 P598 BST 2 0x40000185 FP BE Pri !#1 N3358 P598 BST 3 0x40000186 FP BE Pri !#1 N3359 P598 BST 4 0x40000187 FP BE Pri !#1 N3360 P599 MEMBAR !#1 N3361 P600 BST 5 0x40000188 FP BE Pri !#1 N3362 P600 BST 6 0x40000189 FP BE Pri !#1 N3363 P601 MEMBAR !#1 N3364 P602 BLD 15 -1 FP BE Pri !#1 N3365 P603 MEMBAR !#1 N3366 P604 REPLACEMENT 33 Int BE Pri !#1 N3367 P605 MEMBAR !#1 N3368 P606 BLD 0 -1 FP BE Pri !#1 N3369 P606 BLD 1 -1 FP BE Pri !#A N3368 N3369 !#1 N3370 P606 BLD 2 -1 FP BE Pri !#1 N3371 P606 BLD 3 -1 FP BE Pri !#1 N3372 P606 BLD 4 -1 FP BE Pri !#1 N3373 P607 MEMBAR !#1 N3374 P608 REPLACEMENT 21 Int BE Pri !#1 N3375 P609 MEMBAR !#1 N3376 P610 BLD 15 -1 FP BE Pri !#1 N3377 P611 MEMBAR !#1 N3378 P612 REPLACEMENT 29 Int BE Pri !#1 N3379 P613 LD 28 -1 Int BE Nuc !#1 N3380 P614 MEMBAR !#1 N3381 P615 BLD 24 -1 FP BE Pri !#1 N3382 P615 BLD 25 -1 FP BE Pri !#1 N3383 P616 MEMBAR !#1 N3384 P617 ST 23 0x4000018a FP BE Pri !#1 N3385 P618 MEMBAR !#1 N3386 P619 BST 19 0x4000018b FP BE Pri !#1 N3387 P620 MEMBAR !#1 N3388 P621 BLD 5 -1 FP BE Pri !#1 N3389 P621 BLD 6 -1 FP BE Pri !#1 N3390 P622 MEMBAR !#1 N3391 P623 BST 24 0x4000018c FP BE Pri !#1 N3392 P623 BST 25 0x4000018d FP BE Pri !#1 N3393 P624 MEMBAR !#1 N3394 P625 PREFETCH 23 Int BE Sec !#1 N3395 P626 MEMBAR !#1 N3396 P627 BLD 0 -1 FP BE Pri !#1 N3397 P627 BLD 1 -1 FP BE Pri !#A N3396 N3397 !#1 N3398 P627 BLD 2 -1 FP BE Pri !#1 N3399 P627 BLD 3 -1 FP BE Pri !#1 N3400 P627 BLD 4 -1 FP BE Pri !#1 N3401 P628 MEMBAR !#1 N3402 P629 BST 24 0x4000018e FP BE Pri !#1 N3403 P629 BST 25 0x4000018f FP BE Pri !#1 N3404 P630 MEMBAR !#1 N3405 P631 BLD 21 -1 FP BE Pri !#1 N3406 P631 BLD 22 -1 FP BE Pri !#A N3405 N3406 !#1 N3407 P631 BLD 23 -1 FP BE Pri !#1 N3408 P632 MEMBAR !#1 N3409 P633 BLD 20 -1 FP BE Pri !#1 N3410 P634 MEMBAR !#1 N3411 P635 REPLACEMENT 27 Int BE Pri !#1 N3412 P636 REPLACEMENT 33 Int BE Sec !#1 N3413 P637 LD 7 -1 Int BE Pri !#1 N3414 P638 MEMBAR !#1 N3415 P639 BLD 26 -1 FP BE Pri !#1 N3416 P639 BLD 27 -1 FP BE Pri !#1 N3417 P640 MEMBAR !#1 N3418 P641 ST 28 0x80001e Int BE Pri !#1 N3419 P642 MEMBAR !#1 N3420 P643 BLD 0 -1 FP BE Pri !#1 N3421 P643 BLD 1 -1 FP BE Pri !#A N3420 N3421 !#1 N3422 P643 BLD 2 -1 FP BE Pri !#1 N3423 P643 BLD 3 -1 FP BE Pri !#1 N3424 P643 BLD 4 -1 FP BE Pri !#1 N3425 P644 MEMBAR !#1 N3426 P645 BST 0 0x40000190 FP BE Pri !#1 N3427 P645 BST 1 0x40000191 FP BE Pri !#A N3426 N3427 !#1 N3428 P645 BST 2 0x40000192 FP BE Pri !#1 N3429 P645 BST 3 0x40000193 FP BE Pri !#1 N3430 P645 BST 4 0x40000194 FP BE Pri !#1 N3431 P646 MEMBAR !#1 N3432 P647 REPLACEMENT 3 Int BE Pri !#1 N3433 P648 LD 8 -1 FP BE Sec !#1 N3434 P649 ST 8 0x80001f Int BE Pri !#1 N3435 P650 MEMBAR !#1 N3436 P651 BLD 18 -1 FP BE Pri !#1 N3437 P652 MEMBAR !#1 N3438 P653 ST 13 0x40000195 FP BE Pri !#1 N3439 P654 REPLACEMENT 17 Int BE Nuc !#1 N3440 P655 ST 19 0x800020 Int BE Pri !#1 N3441 P656 MEMBAR !#1 N3442 P657 BLD 19 -1 FP BE Pri !#1 N3443 P658 MEMBAR !#1 N3444 P659 BLD 5 -1 FP BE Pri !#1 N3445 P659 BLD 6 -1 FP BE Pri !#1 N3446 P660 MEMBAR !#1 N3447 P661 BST 5 0x40000196 FP BE Pri !#1 N3448 P661 BST 6 0x40000197 FP BE Pri !#1 N3449 P662 MEMBAR !#1 N3450 P663 BLD 30 -1 FP BE Pri !#1 N3451 P664 MEMBAR !#1 N3452 P665 REPLACEMENT 24 Int BE Pri !#1 N3453 P666 MEMBAR !#1 N3454 P667 BSTC 16 0x40000198 FP BE Pri !#1 N3455 P668 MEMBAR !#1 N3456 P669 LD 7 -1 Int BE Pri !#1 N3457 P670 LD 19 -1 FP BE Pri !#1 N3458 P671 MEMBAR !#1 N3459 P672 BLD 24 -1 FP BE Pri !#1 N3460 P672 BLD 25 -1 FP BE Pri !#1 N3461 P673 MEMBAR !#1 N3462 P674 IDC_FLIP 2 Int BE Pri !#1 N3463 P675 MEMBAR !#1 N3464 P676 BLD 11 -1 FP BE Pri !#1 N3465 P676 BLD 12 -1 FP BE Pri !#A N3464 N3465 !#1 N3466 P676 BLD 13 -1 FP BE Pri !#1 N3467 P677 MEMBAR !#1 N3468 P678 BST 15 0x40000199 FP BE Pri !#1 N3469 P679 MEMBAR !#1 N3470 P680 BLD 5 -1 FP BE Sec !#1 N3471 P680 BLD 6 -1 FP BE Sec !#1 N3472 P681 MEMBAR !#1 N3473 P682 BLD 21 -1 FP BE Pri !#1 N3474 P682 BLD 22 -1 FP BE Pri !#A N3473 N3474 !#1 N3475 P682 BLD 23 -1 FP BE Pri !#1 N3476 P683 MEMBAR !#1 N3477 P684 REPLACEMENT 23 Int BE Pri !#1 N3478 P685 MEMBAR !#1 N3479 P686 BST 5 0x4000019a FP BE Sec !#1 N3480 P686 BST 6 0x4000019b FP BE Sec !#1 N3481 P687 MEMBAR !#1 N3482 P688 BSTC 11 0x4000019c FP BE Pri !#1 N3483 P688 BSTC 12 0x4000019d FP BE Pri !#A N3482 N3483 !#1 N3484 P688 BSTC 13 0x4000019e FP BE Pri !#1 N3485 P689 MEMBAR !#1 N3486 P690 REPLACEMENT 12 Int BE Nuc !#1 N3487 P691 REPLACEMENT 8 Int BE Pri !#1 N3488 P692 MEMBAR !#1 N3489 P693 BSTC 21 0x4000019f FP BE Pri !#1 N3490 P693 BSTC 22 0x400001a0 FP BE Pri !#A N3489 N3490 !#1 N3491 P693 BSTC 23 0x400001a1 FP BE Pri !#1 N3492 P694 MEMBAR !#1 N3493 P695 LD 25 -1 FP BE Pri !#1 N3494 P696 MEMBAR !#1 N3495 P697 BLD 15 -1 FP BE Pri !#1 N3496 P698 MEMBAR !#1 N3497 P699 ST 30 0x800021 Int BE Sec !#1 N3498 P700 REPLACEMENT 11 Int BE Nuc !#1 N3499 P701 REPLACEMENT 20 Int BE Pri !#1 N3500 P702 REPLACEMENT 9 Int BE Pri !#1 N3501 P703 MEMBAR !#1 N3502 P704 BST 11 0x400001a2 FP BE Pri !#1 N3503 P704 BST 12 0x400001a3 FP BE Pri !#A N3502 N3503 !#1 N3504 P704 BST 13 0x400001a4 FP BE Pri !#1 N3505 P705 MEMBAR !#1 N3506 P706 LD 10 -1 Int BE Pri !#1 N3507 P707 REPLACEMENT 5 Int BE Pri !#1 N3508 P708 LD 27 -1 FP BE Sec !#1 N3509 P709 MEMBAR !#1 N3510 P710 BST 11 0x400001a5 FP BE Sec !#1 N3511 P710 BST 12 0x400001a6 FP BE Sec !#A N3510 N3511 !#1 N3512 P710 BST 13 0x400001a7 FP BE Sec !#1 N3513 P711 MEMBAR !#1 N3514 P712 LD 17 -1 Int BE Pri Loop_exit !#1 N3515 P713 MEMBAR !#2 N3516 P714 MEMBAR !#2 N3517 P715 BST 33 0x40800001 FP BE Pri !#2 N3518 P716 MEMBAR !#2 N3519 P717 REPLACEMENT 12 Int BE Pri !#2 N3520 P718 REPLACEMENT 13 Int BE Sec !#2 N3521 P719 ST 6 0x40800002 FP BE Pri !#2 N3522 P720 REPLACEMENT 5 Int BE Nuc !#2 N3523 P721 MEMBAR !#2 N3524 P722 BSTC 5 0x40800003 FP BE Pri !#2 N3525 P722 BSTC 6 0x40800004 FP BE Pri !#2 N3526 P723 MEMBAR !#2 N3527 P724 BLD 0 -1 FP BE Pri !#2 N3528 P724 BLD 1 -1 FP BE Pri !#A N3527 N3528 !#2 N3529 P724 BLD 2 -1 FP BE Pri !#2 N3530 P724 BLD 3 -1 FP BE Pri !#2 N3531 P724 BLD 4 -1 FP BE Pri !#2 N3532 P725 MEMBAR !#2 N3533 P726 BLD 24 -1 FP BE Sec !#2 N3534 P726 BLD 25 -1 FP BE Sec !#2 N3535 P727 MEMBAR !#2 N3536 P728 REPLACEMENT 9 Int BE Pri !#2 N3537 P729 MEMBAR !#2 N3538 P730 BST 0 0x40800005 FP BE Pri !#2 N3539 P730 BST 1 0x40800006 FP BE Pri !#A N3538 N3539 !#2 N3540 P730 BST 2 0x40800007 FP BE Pri !#2 N3541 P730 BST 3 0x40800008 FP BE Pri !#2 N3542 P730 BST 4 0x40800009 FP BE Pri !#2 N3543 P731 MEMBAR !#2 N3544 P732 ST 9 0x4080000a FP BE Sec !#2 N3545 P733 LD 26 -1 Int BE Pri !#2 N3546 P734 LD 21 -1 FP BE Sec !#2 N3547 P735 LD 11 -1 FP BE Sec !#2 N3548 P736 MEMBAR !#2 N3549 P737 BST 10 0x4080000b FP BE Pri !#2 N3550 P738 MEMBAR !#2 N3551 P739 REPLACEMENT 7 Int BE Pri !#2 N3552 P740 ST 29 0x4080000c FP BE Pri !#2 N3553 P741 LD 22 -1 Int BE Pri !#2 N3554 P742 REPLACEMENT 21 Int BE Pri !#2 N3555 P743 MEMBAR !#2 N3556 P744 BSTC 30 0x4080000d FP BE Pri !#2 N3557 P745 MEMBAR !#2 N3558 P746 PREFETCH 24 Int BE Sec !#2 N3559 P747 REPLACEMENT 14 Int BE Nuc !#2 N3560 P748 PREFETCH 8 Int BE Nuc !#2 N3561 P749 MEMBAR !#2 N3562 P750 BLD 0 -1 FP BE Pri !#2 N3563 P750 BLD 1 -1 FP BE Pri !#A N3562 N3563 !#2 N3564 P750 BLD 2 -1 FP BE Pri !#2 N3565 P750 BLD 3 -1 FP BE Pri !#2 N3566 P750 BLD 4 -1 FP BE Pri !#2 N3567 P751 MEMBAR !#2 N3568 P752 PREFETCH 1 Int BE Pri !#2 N3569 P753 ST 30 0x1000001 Int BE Sec !#2 N3570 P754 PREFETCH 20 Int BE Nuc !#2 N3571 P755 MEMBAR !#2 N3572 P756 BLD 0 -1 FP BE Pri !#2 N3573 P756 BLD 1 -1 FP BE Pri !#A N3572 N3573 !#2 N3574 P756 BLD 2 -1 FP BE Pri !#2 N3575 P756 BLD 3 -1 FP BE Pri !#2 N3576 P756 BLD 4 -1 FP BE Pri !#2 N3577 P757 MEMBAR !#2 N3578 P758 BLD 11 -1 FP BE Pri !#2 N3579 P758 BLD 12 -1 FP BE Pri !#A N3578 N3579 !#2 N3580 P758 BLD 13 -1 FP BE Pri !#2 N3581 P759 MEMBAR !#2 N3582 P760 LD 24 -1 FP BE Pri !#2 N3583 P761 LD 23 -1 Int BE Pri !#2 N3584 P762 LD 16 -1 FP BE Pri !#2 N3585 P763 MEMBAR !#2 N3586 P764 BLD 0 -1 FP BE Pri !#2 N3587 P764 BLD 1 -1 FP BE Pri !#A N3586 N3587 !#2 N3588 P764 BLD 2 -1 FP BE Pri !#2 N3589 P764 BLD 3 -1 FP BE Pri !#2 N3590 P764 BLD 4 -1 FP BE Pri !#2 N3591 P765 MEMBAR !#2 N3592 P766 BST 17 0x4080000e FP BE Sec !#2 N3593 P767 MEMBAR !#2 N3594 P768 BLD 5 -1 FP BE Pri !#2 N3595 P768 BLD 6 -1 FP BE Pri !#2 N3596 P769 MEMBAR !#2 N3597 P770 PREFETCH 19 Int BE Pri !#2 N3598 P771 LD 7 -1 FP BE Pri !#2 N3599 P772 IDC_FLIP 12 Int BE Pri !#2 N3600 P773 MEMBAR !#2 N3601 P774 BSTC 0 0x4080000f FP BE Pri !#2 N3602 P774 BSTC 1 0x40800010 FP BE Pri !#A N3601 N3602 !#2 N3603 P774 BSTC 2 0x40800011 FP BE Pri !#2 N3604 P774 BSTC 3 0x40800012 FP BE Pri !#2 N3605 P774 BSTC 4 0x40800013 FP BE Pri !#2 N3606 P775 MEMBAR !#2 N3607 P776 BSTC 8 0x40800014 FP BE Pri !#2 N3608 P776 BSTC 9 0x40800015 FP BE Pri !#2 N3609 P777 MEMBAR !#2 N3610 P778 IDC_FLIP 24 Int BE Pri !#2 N3611 P779 MEMBAR !#2 N3612 P780 BSTC 14 0x40800016 FP BE Pri !#2 N3613 P781 MEMBAR !#2 N3614 P782 LD 11 -1 Int BE Pri !#2 N3615 P783 ST 0 0x40800017 FP BE Nuc !#2 N3616 P784 ST 31 0x40800018 FP BE Pri !#2 N3617 P785 REPLACEMENT 24 Int BE Pri !#2 N3618 P786 REPLACEMENT 27 Int BE Sec !#2 N3619 P787 MEMBAR !#2 N3620 P788 BST 21 0x40800019 FP BE Pri !#2 N3621 P788 BST 22 0x4080001a FP BE Pri !#A N3620 N3621 !#2 N3622 P788 BST 23 0x4080001b FP BE Pri !#2 N3623 P789 MEMBAR !#2 N3624 P790 BLD 0 -1 FP BE Pri !#2 N3625 P790 BLD 1 -1 FP BE Pri !#A N3624 N3625 !#2 N3626 P790 BLD 2 -1 FP BE Pri !#2 N3627 P790 BLD 3 -1 FP BE Pri !#2 N3628 P790 BLD 4 -1 FP BE Pri !#2 N3629 P791 MEMBAR !#2 N3630 P792 LD 28 -1 FP BE Pri !#2 N3631 P793 LD 29 -1 FP BE Nuc !#2 N3632 P794 PREFETCH 0 Int BE Pri !#2 N3633 P795 MEMBAR !#2 N3634 P796 BST 32 0x4080001c FP BE Pri !#2 N3635 P797 MEMBAR !#2 N3636 P798 BLD 5 -1 FP BE Pri !#2 N3637 P798 BLD 6 -1 FP BE Pri !#2 N3638 P799 MEMBAR !#2 N3639 P800 BSTC 33 0x4080001d FP BE Pri !#2 N3640 P801 MEMBAR !#2 N3641 P802 BLD 16 -1 FP BE Pri !#2 N3642 P803 MEMBAR !#2 N3643 P804 ST 25 0x4080001e FP BE Sec !#2 N3644 P805 LD 16 -1 FP BE Pri !#2 N3645 P806 MEMBAR !#2 N3646 P807 BLD 17 -1 FP BE Sec !#2 N3647 P808 MEMBAR !#2 N3648 P809 BLD 21 -1 FP BE Pri !#2 N3649 P809 BLD 22 -1 FP BE Pri !#A N3648 N3649 !#2 N3650 P809 BLD 23 -1 FP BE Pri !#2 N3651 P810 MEMBAR !#2 N3652 P811 BST 0 0x4080001f FP BE Pri !#2 N3653 P811 BST 1 0x40800020 FP BE Pri !#A N3652 N3653 !#2 N3654 P811 BST 2 0x40800021 FP BE Pri !#2 N3655 P811 BST 3 0x40800022 FP BE Pri !#2 N3656 P811 BST 4 0x40800023 FP BE Pri !#2 N3657 P812 MEMBAR !#2 N3658 P813 BLD 0 -1 FP BE Pri !#2 N3659 P813 BLD 1 -1 FP BE Pri !#A N3658 N3659 !#2 N3660 P813 BLD 2 -1 FP BE Pri !#2 N3661 P813 BLD 3 -1 FP BE Pri !#2 N3662 P813 BLD 4 -1 FP BE Pri !#2 N3663 P814 MEMBAR !#2 N3664 P815 BLD 33 -1 FP BE Sec !#2 N3665 P816 MEMBAR !#2 N3666 P817 BSTC 11 0x40800024 FP BE Sec !#2 N3667 P817 BSTC 12 0x40800025 FP BE Sec !#A N3666 N3667 !#2 N3668 P817 BSTC 13 0x40800026 FP BE Sec !#2 N3669 P818 MEMBAR !#2 N3670 P819 LD 10 -1 Int BE Pri !#2 N3671 P820 REPLACEMENT 27 Int BE Pri !#2 N3672 P821 PREFETCH 8 Int BE Pri !#2 N3673 P822 MEMBAR !#2 N3674 P823 BLD 14 -1 FP BE Pri !#2 N3675 P824 MEMBAR !#2 N3676 P825 BST 11 0x40800027 FP BE Pri !#2 N3677 P825 BST 12 0x40800028 FP BE Pri !#A N3676 N3677 !#2 N3678 P825 BST 13 0x40800029 FP BE Pri !#2 N3679 P826 MEMBAR !#2 N3680 P827 BLD 21 -1 FP BE Pri !#2 N3681 P827 BLD 22 -1 FP BE Pri !#A N3680 N3681 !#2 N3682 P827 BLD 23 -1 FP BE Pri !#2 N3683 P828 MEMBAR !#2 N3684 P829 IDC_FLIP 23 Int BE Pri !#2 N3685 P830 MEMBAR !#2 N3686 P831 BLD 21 -1 FP BE Pri !#2 N3687 P831 BLD 22 -1 FP BE Pri !#A N3686 N3687 !#2 N3688 P831 BLD 23 -1 FP BE Pri !#2 N3689 P832 MEMBAR !#2 N3690 P833 BSTC 19 0x4080002a FP BE Pri !#2 N3691 P834 MEMBAR !#2 N3692 P835 BLD 16 -1 FP BE Pri !#2 N3693 P836 MEMBAR !#2 N3694 P837 REPLACEMENT 33 Int BE Pri !#2 N3695 P838 REPLACEMENT 26 Int BE Nuc !#2 N3696 P839 IDC_FLIP 5 Int BE Pri !#2 N3697 P840 MEMBAR !#2 N3698 P841 BSTC 10 0x4080002b FP BE Pri !#2 N3699 P842 MEMBAR !#2 N3700 P843 BSTC 11 0x4080002c FP BE Pri !#2 N3701 P843 BSTC 12 0x4080002d FP BE Pri !#A N3700 N3701 !#2 N3702 P843 BSTC 13 0x4080002e FP BE Pri !#2 N3703 P844 MEMBAR !#2 N3704 P845 BLD 5 -1 FP BE Pri !#2 N3705 P845 BLD 6 -1 FP BE Pri !#2 N3706 P846 MEMBAR !#2 N3707 P847 BLD 24 -1 FP BE Pri !#2 N3708 P847 BLD 25 -1 FP BE Pri !#2 N3709 P848 MEMBAR !#2 N3710 P849 LD 7 -1 FP BE Pri !#2 N3711 P850 MEMBAR !#2 N3712 P851 BLD 17 -1 FP BE Sec !#2 N3713 P852 MEMBAR !#2 N3714 P853 BLD 19 -1 FP BE Pri !#2 N3715 P854 MEMBAR !#2 N3716 P855 REPLACEMENT 31 Int BE Pri !#2 N3717 P856 ST 26 0x4080002f FP BE Sec !#2 N3718 P857 PREFETCH 9 Int BE Nuc !#2 N3719 P858 MEMBAR !#2 N3720 P859 BST 33 0x40800030 FP BE Pri !#2 N3721 P860 MEMBAR !#2 N3722 P861 REPLACEMENT 10 Int BE Sec !#2 N3723 P862 MEMBAR !#2 N3724 P863 BLD 15 -1 FP BE Pri !#2 N3725 P864 MEMBAR !#2 N3726 P865 LD 31 -1 FP BE Pri !#2 N3727 P866 REPLACEMENT 25 Int BE Pri !#2 N3728 P867 ST 27 0x1000002 Int BE Pri !#2 N3729 P868 PREFETCH 27 Int LE Pri !#2 N3730 P869 MEMBAR !#2 N3731 P870 BLD 8 -1 FP BE Pri !#2 N3732 P870 BLD 9 -1 FP BE Pri !#2 N3733 P871 MEMBAR !#2 N3734 P872 BST 8 0x40800031 FP BE Pri !#2 N3735 P872 BST 9 0x40800032 FP BE Pri !#2 N3736 P873 MEMBAR !#2 N3737 P874 BLD 14 -1 FP BE Pri !#2 N3738 P875 MEMBAR !#2 N3739 P876 REPLACEMENT 14 Int BE Pri !#2 N3740 P877 LD 8 -1 Int LE Pri !#2 N3741 P878 REPLACEMENT 17 Int BE Pri !#2 N3742 P879 MEMBAR !#2 N3743 P880 BLD 5 -1 FP BE Pri !#2 N3744 P880 BLD 6 -1 FP BE Pri !#2 N3745 P881 MEMBAR !#2 N3746 P882 ST 28 0x1000003 Int BE Pri !#2 N3747 P883 MEMBAR !#2 N3748 P884 BSTC 0 0x40800033 FP BE Pri !#2 N3749 P884 BSTC 1 0x40800034 FP BE Pri !#A N3748 N3749 !#2 N3750 P884 BSTC 2 0x40800035 FP BE Pri !#2 N3751 P884 BSTC 3 0x40800036 FP BE Pri !#2 N3752 P884 BSTC 4 0x40800037 FP BE Pri !#2 N3753 P885 MEMBAR !#2 N3754 P886 BLD 7 -1 FP BE Pri !#2 N3755 P887 MEMBAR !#2 N3756 P888 LD 18 -1 Int BE Sec !#2 N3757 P889 REPLACEMENT 13 Int BE Pri !#2 N3758 P890 ST 19 0x1000004 Int BE Pri !#2 N3759 P891 MEMBAR !#2 N3760 P892 BST 24 0x40800038 FP BE Pri !#2 N3761 P892 BST 25 0x40800039 FP BE Pri !#2 N3762 P893 MEMBAR !#2 N3763 P894 BLD 0 -1 FP BE Pri !#2 N3764 P894 BLD 1 -1 FP BE Pri !#A N3763 N3764 !#2 N3765 P894 BLD 2 -1 FP BE Pri !#2 N3766 P894 BLD 3 -1 FP BE Pri !#2 N3767 P894 BLD 4 -1 FP BE Pri !#2 N3768 P895 MEMBAR !#2 N3769 P896 ST 33 0x1000005 Int BE Sec !#2 N3770 P897 MEMBAR !#2 N3771 P898 BST 19 0x4080003a FP BE Sec !#2 N3772 P899 MEMBAR !#2 N3773 P900 BLD 24 -1 FP BE Pri !#2 N3774 P900 BLD 25 -1 FP BE Pri !#2 N3775 P901 MEMBAR !#2 N3776 P902 BSTC 26 0x4080003b FP BE Pri !#2 N3777 P902 BSTC 27 0x4080003c FP BE Pri !#2 N3778 P903 MEMBAR !#2 N3779 P904 BLD 0 -1 FP BE Pri !#2 N3780 P904 BLD 1 -1 FP BE Pri !#A N3779 N3780 !#2 N3781 P904 BLD 2 -1 FP BE Pri !#2 N3782 P904 BLD 3 -1 FP BE Pri !#2 N3783 P904 BLD 4 -1 FP BE Pri !#2 N3784 P905 MEMBAR !#2 N3785 P906 REPLACEMENT 16 Int BE Pri !#2 N3786 P907 LD 33 -1 Int BE Pri !#2 N3787 P908 MEMBAR !#2 N3788 P909 BLD 19 -1 FP BE Pri !#2 N3789 P910 MEMBAR !#2 N3790 P911 BST 33 0x4080003d FP BE Pri !#2 N3791 P912 MEMBAR !#2 N3792 P913 REPLACEMENT 25 Int BE Pri !#2 N3793 P914 PREFETCH 11 Int BE Pri !#2 N3794 P915 ST 16 0x4080003e FP BE Sec !#2 N3795 P916 ST 32 0x1000006 Int BE Pri !#2 N3796 P917 MEMBAR !#2 N3797 P918 BST 0 0x4080003f FP BE Pri !#2 N3798 P918 BST 1 0x40800040 FP BE Pri !#A N3797 N3798 !#2 N3799 P918 BST 2 0x40800041 FP BE Pri !#2 N3800 P918 BST 3 0x40800042 FP BE Pri !#2 N3801 P918 BST 4 0x40800043 FP BE Pri !#2 N3802 P919 MEMBAR !#2 N3803 P920 REPLACEMENT 29 Int BE Pri !#2 N3804 P921 ST 15 0x1000007 Int BE Pri !#2 N3805 P922 MEMBAR !#2 N3806 P923 BSTC 10 0x40800044 FP BE Pri !#2 N3807 P924 MEMBAR !#2 N3808 P925 BLD 18 -1 FP BE Pri !#2 N3809 P926 MEMBAR !#2 N3810 P927 BSTC 15 0x40800045 FP BE Sec !#2 N3811 P928 MEMBAR !#2 N3812 P929 BSTC 16 0x40800046 FP BE Pri !#2 N3813 P930 MEMBAR !#2 N3814 P931 REPLACEMENT 2 Int BE Pri !#2 N3815 P932 PREFETCH 25 Int BE Sec !#2 N3816 P933 MEMBAR !#2 N3817 P934 BST 24 0x40800047 FP BE Sec !#2 N3818 P934 BST 25 0x40800048 FP BE Sec !#2 N3819 P935 MEMBAR !#2 N3820 P936 ST 14 0x1000008 Int BE Pri !#2 N3821 P937 REPLACEMENT 8 Int BE Nuc !#2 N3822 P938 MEMBAR !#2 N3823 P939 BLD 28 -1 FP BE Pri !#2 N3824 P940 MEMBAR !#2 N3825 P941 REPLACEMENT 26 Int BE Pri !#2 N3826 P942 MEMBAR !#2 N3827 P943 BST 21 0x40800049 FP BE Pri !#2 N3828 P943 BST 22 0x4080004a FP BE Pri !#A N3827 N3828 !#2 N3829 P943 BST 23 0x4080004b FP BE Pri !#2 N3830 P944 MEMBAR !#2 N3831 P945 ST 18 0x1000009 Int BE Pri !#2 N3832 P946 LD 1 -1 Int BE Pri !#2 N3833 P947 ST 14 0x4080004c FP BE Pri !#2 N3834 P948 MEMBAR !#2 N3835 P949 BLD 26 -1 FP BE Pri !#2 N3836 P949 BLD 27 -1 FP BE Pri !#2 N3837 P950 MEMBAR !#2 N3838 P951 BST 15 0x4080004d FP BE Pri !#2 N3839 P952 MEMBAR !#2 N3840 P953 LD 33 -1 FP BE Pri !#2 N3841 P954 MEMBAR !#2 N3842 P955 BLD 0 -1 FP BE Pri !#2 N3843 P955 BLD 1 -1 FP BE Pri !#A N3842 N3843 !#2 N3844 P955 BLD 2 -1 FP BE Pri !#2 N3845 P955 BLD 3 -1 FP BE Pri !#2 N3846 P955 BLD 4 -1 FP BE Pri !#2 N3847 P956 MEMBAR !#2 N3848 P957 LD 5 -1 Int BE Pri !#2 N3849 P958 LD 10 -1 FP BE Pri !#2 N3850 P959 IDC_FLIP 8 Int BE Pri !#2 N3851 P960 LD 12 -1 FP BE Sec !#2 N3852 P961 ST 5 0x4080004e FP BE Sec !#2 N3853 P962 LD 14 -1 FP BE Pri !#2 N3854 P963 MEMBAR !#2 N3855 P964 BSTC 14 0x4080004f FP BE Pri !#2 N3856 P965 MEMBAR !#2 N3857 P966 LD 0 -1 FP BE Pri !#2 N3858 P967 MEMBAR !#2 N3859 P968 BLD 0 -1 FP BE Sec !#2 N3860 P968 BLD 1 -1 FP BE Sec !#A N3859 N3860 !#2 N3861 P968 BLD 2 -1 FP BE Sec !#2 N3862 P968 BLD 3 -1 FP BE Sec !#2 N3863 P968 BLD 4 -1 FP BE Sec !#2 N3864 P969 MEMBAR !#2 N3865 P970 REPLACEMENT 16 Int BE Pri !#2 N3866 P971 MEMBAR !#2 N3867 P972 BST 19 0x40800050 FP BE Pri !#2 N3868 P973 MEMBAR !#2 N3869 P974 BST 19 0x40800051 FP BE Pri !#2 N3870 P975 MEMBAR !#2 N3871 P976 ST 23 0x40800052 FP BE Pri !#2 N3872 P977 ST 1 0x40800053 FP BE Pri !#2 N3873 P978 PREFETCH 11 Int BE Pri !#2 N3874 P979 MEMBAR !#2 N3875 P980 BST 11 0x40800054 FP BE Pri !#2 N3876 P980 BST 12 0x40800055 FP BE Pri !#A N3875 N3876 !#2 N3877 P980 BST 13 0x40800056 FP BE Pri !#2 N3878 P981 MEMBAR !#2 N3879 P982 REPLACEMENT 9 Int BE Pri !#2 N3880 P983 ST 13 0x40800057 FP BE Pri !#2 N3881 P984 REPLACEMENT 20 Int BE Pri !#2 N3882 P985 ST 12 0x100000a Int BE Pri !#2 N3883 P986 LD 3 -1 Int BE Sec !#2 N3884 P987 ST 12 0x100000b Int BE Nuc !#2 N3885 P988 MEMBAR !#2 N3886 P989 BST 28 0x40800058 FP BE Sec !#2 N3887 P990 MEMBAR !#2 N3888 P991 LD 25 -1 Int BE Pri !#2 N3889 P992 LD 33 -1 FP BE Pri !#2 N3890 P993 MEMBAR !#2 N3891 P994 BLD 8 -1 FP BE Pri !#2 N3892 P994 BLD 9 -1 FP BE Pri !#2 N3893 P995 MEMBAR !#2 N3894 P996 BLD 5 -1 FP BE Pri !#2 N3895 P996 BLD 6 -1 FP BE Pri !#2 N3896 P997 MEMBAR !#2 N3897 P998 REPLACEMENT 18 Int BE Nuc !#2 N3898 P999 MEMBAR !#2 N3899 P1000 BLD 16 -1 FP BE Pri !#2 N3900 P1001 MEMBAR !#2 N3901 P1002 BLD 28 -1 FP BE Pri !#2 N3902 P1003 MEMBAR !#2 N3903 P1004 REPLACEMENT 16 Int BE Sec !#2 N3904 P1005 LD 4 -1 FP BE Pri !#2 N3905 P1006 MEMBAR !#2 N3906 P1007 BLD 28 -1 FP BE Pri !#2 N3907 P1008 MEMBAR !#2 N3908 P1009 LD 33 -1 Int BE Pri !#2 N3909 P1010 ST 1 0x100000c Int BE Pri !#2 N3910 P1011 MEMBAR !#2 N3911 P1012 BST 0 0x40800059 FP BE Pri !#2 N3912 P1012 BST 1 0x4080005a FP BE Pri !#A N3911 N3912 !#2 N3913 P1012 BST 2 0x4080005b FP BE Pri !#2 N3914 P1012 BST 3 0x4080005c FP BE Pri !#2 N3915 P1012 BST 4 0x4080005d FP BE Pri !#2 N3916 P1013 MEMBAR !#2 N3917 P1014 BST 20 0x4080005e FP BE Sec !#2 N3918 P1015 MEMBAR !#2 N3919 P1016 ST 8 0x100000d Int BE Pri !#2 N3920 P1017 PREFETCH 2 Int BE Pri !#2 N3921 P1018 ST 23 0x100000e Int BE Pri !#2 N3922 P1019 MEMBAR !#2 N3923 P1020 BSTC 21 0x4080005f FP BE Pri !#2 N3924 P1020 BSTC 22 0x40800060 FP BE Pri !#A N3923 N3924 !#2 N3925 P1020 BSTC 23 0x40800061 FP BE Pri !#2 N3926 P1021 MEMBAR !#2 N3927 P1022 ST 29 0x40800062 FP BE Pri !#2 N3928 P1023 MEMBAR !#2 N3929 P1024 BSTC 21 0x40800063 FP BE Pri !#2 N3930 P1024 BSTC 22 0x40800064 FP BE Pri !#A N3929 N3930 !#2 N3931 P1024 BSTC 23 0x40800065 FP BE Pri !#2 N3932 P1025 MEMBAR !#2 N3933 P1026 REPLACEMENT 1 Int BE Pri !#2 N3934 P1027 REPLACEMENT 30 Int BE Nuc !#2 N3935 P1028 REPLACEMENT 28 Int BE Pri !#2 N3936 P1029 REPLACEMENT 8 Int BE Pri !#2 N3937 P1030 LD 32 -1 FP BE Pri !#2 N3938 P1031 REPLACEMENT 2 Int BE Pri !#2 N3939 P1032 ST 21 0x40800066 FP BE Pri !#2 N3940 P1033 REPLACEMENT 25 Int BE Pri !#2 N3941 P1034 MEMBAR !#2 N3942 P1035 BLD 15 -1 FP BE Pri !#2 N3943 P1036 MEMBAR !#2 N3944 P1037 BSTC 5 0x40800067 FP BE Pri !#2 N3945 P1037 BSTC 6 0x40800068 FP BE Pri !#2 N3946 P1038 MEMBAR !#2 N3947 P1039 BSTC 21 0x40800069 FP BE Pri !#2 N3948 P1039 BSTC 22 0x4080006a FP BE Pri !#A N3947 N3948 !#2 N3949 P1039 BSTC 23 0x4080006b FP BE Pri !#2 N3950 P1040 MEMBAR !#2 N3951 P1041 ST 0 0x4080006c FP BE Pri !#2 N3952 P1042 ST 11 0x4080006d FP BE Pri !#2 N3953 P1043 MEMBAR !#2 N3954 P1044 BSTC 7 0x4080006e FP BE Pri !#2 N3955 P1045 MEMBAR !#2 N3956 P1046 REPLACEMENT 28 Int BE Pri !#2 N3957 P1047 LD 3 -1 FP BE Pri !#2 N3958 P1048 LD 19 -1 Int BE Pri !#2 N3959 P1049 PREFETCH 19 Int BE Nuc !#2 N3960 P1050 PREFETCH 6 Int BE Sec !#2 N3961 P1051 IDC_FLIP 9 Int BE Pri !#2 N3962 P1052 MEMBAR !#2 N3963 P1053 BST 14 0x4080006f FP BE Pri !#2 N3964 P1054 MEMBAR !#2 N3965 P1055 ST 3 0x40800070 FP BE Pri !#2 N3966 P1056 MEMBAR !#2 N3967 P1057 BLD 32 -1 FP BE Sec !#2 N3968 P1058 MEMBAR !#2 N3969 P1059 BSTC 0 0x40800071 FP BE Pri !#2 N3970 P1059 BSTC 1 0x40800072 FP BE Pri !#A N3969 N3970 !#2 N3971 P1059 BSTC 2 0x40800073 FP BE Pri !#2 N3972 P1059 BSTC 3 0x40800074 FP BE Pri !#2 N3973 P1059 BSTC 4 0x40800075 FP BE Pri !#2 N3974 P1060 MEMBAR !#2 N3975 P1061 BSTC 26 0x40800076 FP BE Pri !#2 N3976 P1061 BSTC 27 0x40800077 FP BE Pri !#2 N3977 P1062 MEMBAR !#2 N3978 P1063 BSTC 29 0x40800078 FP BE Pri !#2 N3979 P1064 MEMBAR !#2 N3980 P1065 BST 29 0x40800079 FP BE Pri !#2 N3981 P1066 MEMBAR !#2 N3982 P1067 IDC_FLIP 0 Int BE Pri !#2 N3983 P1068 MEMBAR !#2 N3984 P1069 BLD 8 -1 FP BE Pri !#2 N3985 P1069 BLD 9 -1 FP BE Pri !#2 N3986 P1070 MEMBAR !#2 N3987 P1071 BLD 26 -1 FP BE Pri !#2 N3988 P1071 BLD 27 -1 FP BE Pri !#2 N3989 P1072 MEMBAR !#2 N3990 P1073 PREFETCH 18 Int LE Pri !#2 N3991 P1074 PREFETCH 3 Int BE Pri !#2 N3992 P1075 MEMBAR !#2 N3993 P1076 BSTC 0 0x4080007a FP BE Pri !#2 N3994 P1076 BSTC 1 0x4080007b FP BE Pri !#A N3993 N3994 !#2 N3995 P1076 BSTC 2 0x4080007c FP BE Pri !#2 N3996 P1076 BSTC 3 0x4080007d FP BE Pri !#2 N3997 P1076 BSTC 4 0x4080007e FP BE Pri !#2 N3998 P1077 MEMBAR !#2 N3999 P1078 ST 30 0x4080007f FP BE Pri !#2 N4000 P1079 MEMBAR !#2 N4001 P1080 BLD 29 -1 FP BE Sec !#2 N4002 P1081 MEMBAR !#2 N4003 P1082 BLD 0 -1 FP BE Pri !#2 N4004 P1082 BLD 1 -1 FP BE Pri !#A N4003 N4004 !#2 N4005 P1082 BLD 2 -1 FP BE Pri !#2 N4006 P1082 BLD 3 -1 FP BE Pri !#2 N4007 P1082 BLD 4 -1 FP BE Pri !#2 N4008 P1083 MEMBAR !#2 N4009 P1084 BST 21 0x40800080 FP BE Sec !#2 N4010 P1084 BST 22 0x40800081 FP BE Sec !#A N4009 N4010 !#2 N4011 P1084 BST 23 0x40800082 FP BE Sec !#2 N4012 P1085 MEMBAR !#2 N4013 P1086 BST 26 0x40800083 FP BE Pri !#2 N4014 P1086 BST 27 0x40800084 FP BE Pri !#2 N4015 P1087 MEMBAR !#2 N4016 P1088 BSTC 32 0x40800085 FP BE Pri !#2 N4017 P1089 MEMBAR !#2 N4018 P1090 BSTC 10 0x40800086 FP BE Pri !#2 N4019 P1091 MEMBAR !#2 N4020 P1092 PREFETCH 27 Int BE Pri !#2 N4021 P1093 REPLACEMENT 18 Int BE Pri !#2 N4022 P1094 PREFETCH 25 Int BE Pri !#2 N4023 P1095 REPLACEMENT 24 Int BE Pri !#2 N4024 P1096 MEMBAR !#2 N4025 P1097 BSTC 31 0x40800087 FP BE Pri !#2 N4026 P1098 MEMBAR !#2 N4027 P1099 REPLACEMENT 27 Int BE Pri !#2 N4028 P1100 MEMBAR !#2 N4029 P1101 BLD 7 -1 FP BE Pri !#2 N4030 P1102 MEMBAR !#2 N4031 P1103 REPLACEMENT 21 Int BE Pri !#2 N4032 P1104 REPLACEMENT 33 Int BE Pri !#2 N4033 P1105 MEMBAR !#2 N4034 P1106 BLD 19 -1 FP BE Pri !#2 N4035 P1107 MEMBAR !#2 N4036 P1108 BST 28 0x40800088 FP BE Sec !#2 N4037 P1109 MEMBAR !#2 N4038 P1110 BSTC 18 0x40800089 FP BE Sec !#2 N4039 P1111 MEMBAR !#2 N4040 P1112 BST 8 0x4080008a FP BE Pri !#2 N4041 P1112 BST 9 0x4080008b FP BE Pri !#2 N4042 P1113 MEMBAR !#2 N4043 P1114 BLD 29 -1 FP BE Pri !#2 N4044 P1115 MEMBAR !#2 N4045 P1116 ST 13 0x4080008c FP BE Nuc !#2 N4046 P1117 REPLACEMENT 10 Int BE Nuc !#2 N4047 P1118 MEMBAR !#2 N4048 P1119 BLD 7 -1 FP BE Pri !#2 N4049 P1120 MEMBAR !#2 N4050 P1121 BLD 21 -1 FP BE Pri !#2 N4051 P1121 BLD 22 -1 FP BE Pri !#A N4050 N4051 !#2 N4052 P1121 BLD 23 -1 FP BE Pri !#2 N4053 P1122 MEMBAR !#2 N4054 P1123 BLD 21 -1 FP BE Pri !#2 N4055 P1123 BLD 22 -1 FP BE Pri !#A N4054 N4055 !#2 N4056 P1123 BLD 23 -1 FP BE Pri !#2 N4057 P1124 MEMBAR !#2 N4058 P1125 REPLACEMENT 23 Int BE Pri !#2 N4059 P1126 MEMBAR !#2 N4060 P1127 BLD 8 -1 FP BE Pri !#2 N4061 P1127 BLD 9 -1 FP BE Pri !#2 N4062 P1128 MEMBAR !#2 N4063 P1129 REPLACEMENT 14 Int BE Pri !#2 N4064 P1130 MEMBAR !#2 N4065 P1131 BLD 0 -1 FP BE Pri !#2 N4066 P1131 BLD 1 -1 FP BE Pri !#A N4065 N4066 !#2 N4067 P1131 BLD 2 -1 FP BE Pri !#2 N4068 P1131 BLD 3 -1 FP BE Pri !#2 N4069 P1131 BLD 4 -1 FP BE Pri !#2 N4070 P1132 MEMBAR !#2 N4071 P1133 BLD 19 -1 FP BE Sec !#2 N4072 P1134 MEMBAR !#2 N4073 P1135 LD 24 -1 Int BE Sec !#2 N4074 P1136 REPLACEMENT 2 Int BE Pri !#2 N4075 P1137 REPLACEMENT 23 Int BE Sec !#2 N4076 P1138 MEMBAR !#2 N4077 P1139 BLD 33 -1 FP BE Pri !#2 N4078 P1140 MEMBAR !#2 N4079 P1141 LD 22 -1 Int BE Sec !#2 N4080 P1142 REPLACEMENT 18 Int BE Pri !#2 N4081 P1143 MEMBAR !#2 N4082 P1144 BLD 21 -1 FP BE Pri !#2 N4083 P1144 BLD 22 -1 FP BE Pri !#A N4082 N4083 !#2 N4084 P1144 BLD 23 -1 FP BE Pri !#2 N4085 P1145 MEMBAR !#2 N4086 P1146 BLD 21 -1 FP BE Pri !#2 N4087 P1146 BLD 22 -1 FP BE Pri !#A N4086 N4087 !#2 N4088 P1146 BLD 23 -1 FP BE Pri !#2 N4089 P1147 MEMBAR !#2 N4090 P1148 REPLACEMENT 19 Int BE Pri !#2 N4091 P1149 MEMBAR !#2 N4092 P1150 BSTC 33 0x4080008d FP BE Pri !#2 N4093 P1151 MEMBAR !#2 N4094 P1152 BLD 19 -1 FP BE Pri !#2 N4095 P1153 MEMBAR !#2 N4096 P1154 BST 11 0x4080008e FP BE Pri !#2 N4097 P1154 BST 12 0x4080008f FP BE Pri !#A N4096 N4097 !#2 N4098 P1154 BST 13 0x40800090 FP BE Pri !#2 N4099 P1155 MEMBAR !#2 N4100 P1156 BLD 16 -1 FP BE Pri !#2 N4101 P1157 MEMBAR !#2 N4102 P1158 REPLACEMENT 31 Int BE Nuc !#2 N4103 P1159 MEMBAR !#2 N4104 P1160 BLD 11 -1 FP BE Sec !#2 N4105 P1160 BLD 12 -1 FP BE Sec !#A N4104 N4105 !#2 N4106 P1160 BLD 13 -1 FP BE Sec !#2 N4107 P1161 MEMBAR !#2 N4108 P1162 REPLACEMENT 4 Int BE Nuc !#2 N4109 P1163 REPLACEMENT 24 Int BE Sec !#2 N4110 P1164 PREFETCH 13 Int BE Pri !#2 N4111 P1165 ST 29 0x40800091 FP BE Sec !#2 N4112 P1166 ST 32 0x100000f Int BE Pri !#2 N4113 P1167 REPLACEMENT 1 Int BE Pri !#2 N4114 P1168 MEMBAR !#2 N4115 P1169 BSTC 33 0x40800092 FP BE Pri !#2 N4116 P1170 MEMBAR !#2 N4117 P1171 BST 18 0x40800093 FP BE Pri !#2 N4118 P1172 MEMBAR !#2 N4119 P1173 REPLACEMENT 1 Int BE Nuc !#2 N4120 P1174 MEMBAR !#2 N4121 P1175 BLD 0 -1 FP BE Pri !#2 N4122 P1175 BLD 1 -1 FP BE Pri !#A N4121 N4122 !#2 N4123 P1175 BLD 2 -1 FP BE Pri !#2 N4124 P1175 BLD 3 -1 FP BE Pri !#2 N4125 P1175 BLD 4 -1 FP BE Pri !#2 N4126 P1176 MEMBAR !#2 N4127 P1177 IDC_FLIP 13 Int BE Pri !#2 N4128 P1178 MEMBAR !#2 N4129 P1179 BST 11 0x40800094 FP BE Pri !#2 N4130 P1179 BST 12 0x40800095 FP BE Pri !#A N4129 N4130 !#2 N4131 P1179 BST 13 0x40800096 FP BE Pri !#2 N4132 P1180 MEMBAR !#2 N4133 P1181 ST 25 0x1000010 Int BE Nuc !#2 N4134 P1182 ST 5 0x1000011 Int BE Pri !#2 N4135 P1183 MEMBAR !#2 N4136 P1184 BLD 8 -1 FP BE Pri !#2 N4137 P1184 BLD 9 -1 FP BE Pri !#2 N4138 P1185 MEMBAR !#2 N4139 P1186 BLD 21 -1 FP BE Pri !#2 N4140 P1186 BLD 22 -1 FP BE Pri !#A N4139 N4140 !#2 N4141 P1186 BLD 23 -1 FP BE Pri !#2 N4142 P1187 MEMBAR !#2 N4143 P1188 BSTC 24 0x40800097 FP BE Pri !#2 N4144 P1188 BSTC 25 0x40800098 FP BE Pri !#2 N4145 P1189 MEMBAR !#2 N4146 P1190 REPLACEMENT 21 Int BE Sec !#2 N4147 P1191 REPLACEMENT 16 Int BE Pri !#2 N4148 P1192 REPLACEMENT 32 Int BE Pri !#2 N4149 P1193 MEMBAR !#2 N4150 P1194 BSTC 20 0x40800099 FP BE Pri !#2 N4151 P1195 MEMBAR !#2 N4152 P1196 LD 2 -1 FP BE Nuc !#2 N4153 P1197 PREFETCH 23 Int BE Pri !#2 N4154 P1198 MEMBAR !#2 N4155 P1199 BLD 19 -1 FP BE Pri !#2 N4156 P1200 MEMBAR !#2 N4157 P1201 BLD 11 -1 FP BE Pri !#2 N4158 P1201 BLD 12 -1 FP BE Pri !#A N4157 N4158 !#2 N4159 P1201 BLD 13 -1 FP BE Pri !#2 N4160 P1202 MEMBAR !#2 N4161 P1203 BLD 0 -1 FP BE Pri !#2 N4162 P1203 BLD 1 -1 FP BE Pri !#A N4161 N4162 !#2 N4163 P1203 BLD 2 -1 FP BE Pri !#2 N4164 P1203 BLD 3 -1 FP BE Pri !#2 N4165 P1203 BLD 4 -1 FP BE Pri !#2 N4166 P1204 MEMBAR !#2 N4167 P1205 LD 30 -1 Int BE Pri !#2 N4168 P1206 IDC_FLIP 3 Int BE Pri !#2 N4169 P1207 MEMBAR !#2 N4170 P1208 BLD 11 -1 FP BE Pri !#2 N4171 P1208 BLD 12 -1 FP BE Pri !#A N4170 N4171 !#2 N4172 P1208 BLD 13 -1 FP BE Pri !#2 N4173 P1209 MEMBAR !#2 N4174 P1210 BLD 7 -1 FP BE Pri !#2 N4175 P1211 MEMBAR !#2 N4176 P1212 BST 26 0x4080009a FP BE Pri !#2 N4177 P1212 BST 27 0x4080009b FP BE Pri !#2 N4178 P1213 MEMBAR !#2 N4179 P1214 BSTC 7 0x4080009c FP BE Pri !#2 N4180 P1215 MEMBAR !#2 N4181 P1216 BLD 21 -1 FP BE Sec !#2 N4182 P1216 BLD 22 -1 FP BE Sec !#A N4181 N4182 !#2 N4183 P1216 BLD 23 -1 FP BE Sec !#2 N4184 P1217 MEMBAR !#2 N4185 P1218 BST 30 0x4080009d FP BE Pri !#2 N4186 P1219 MEMBAR !#2 N4187 P1220 LD 21 -1 FP BE Pri !#2 N4188 P1221 MEMBAR !#2 N4189 P1222 BLD 0 -1 FP BE Pri !#2 N4190 P1222 BLD 1 -1 FP BE Pri !#A N4189 N4190 !#2 N4191 P1222 BLD 2 -1 FP BE Pri !#2 N4192 P1222 BLD 3 -1 FP BE Pri !#2 N4193 P1222 BLD 4 -1 FP BE Pri !#2 N4194 P1223 MEMBAR !#2 N4195 P1224 REPLACEMENT 2 Int BE Sec !#2 N4196 P1225 ST 5 0x1000012 Int BE Sec !#2 N4197 P1226 MEMBAR !#2 N4198 P1227 BLD 16 -1 FP BE Pri !#2 N4199 P1228 MEMBAR !#2 N4200 P1229 REPLACEMENT 24 Int BE Pri !#2 N4201 P1230 REPLACEMENT 29 Int BE Pri !#2 N4202 P1231 PREFETCH 15 Int BE Pri !#2 N4203 P1232 MEMBAR !#2 N4204 P1233 BLD 24 -1 FP BE Pri !#2 N4205 P1233 BLD 25 -1 FP BE Pri !#2 N4206 P1234 MEMBAR !#2 N4207 P1235 REPLACEMENT 7 Int BE Pri !#2 N4208 P1236 REPLACEMENT 26 Int BE Pri !#2 N4209 P1237 ST 10 0x1000013 Int BE Pri !#2 N4210 P1238 MEMBAR !#2 N4211 P1239 BSTC 28 0x4080009e FP BE Pri !#2 N4212 P1240 MEMBAR !#2 N4213 P1241 BLD 21 -1 FP BE Pri !#2 N4214 P1241 BLD 22 -1 FP BE Pri !#A N4213 N4214 !#2 N4215 P1241 BLD 23 -1 FP BE Pri !#2 N4216 P1242 MEMBAR !#2 N4217 P1243 LD 32 -1 Int BE Pri !#2 N4218 P1244 MEMBAR !#2 N4219 P1245 BLD 0 -1 FP BE Pri !#2 N4220 P1245 BLD 1 -1 FP BE Pri !#A N4219 N4220 !#2 N4221 P1245 BLD 2 -1 FP BE Pri !#2 N4222 P1245 BLD 3 -1 FP BE Pri !#2 N4223 P1245 BLD 4 -1 FP BE Pri !#2 N4224 P1246 MEMBAR !#2 N4225 P1247 LD 1 -1 Int BE Pri !#2 N4226 P1248 MEMBAR !#2 N4227 P1249 BLD 0 -1 FP BE Pri !#2 N4228 P1249 BLD 1 -1 FP BE Pri !#A N4227 N4228 !#2 N4229 P1249 BLD 2 -1 FP BE Pri !#2 N4230 P1249 BLD 3 -1 FP BE Pri !#2 N4231 P1249 BLD 4 -1 FP BE Pri !#2 N4232 P1250 MEMBAR !#2 N4233 P1251 ST 33 0x1000014 Int BE Sec !#2 N4234 P1252 LD 29 -1 FP BE Pri !#2 N4235 P1253 ST 17 0x4080009f FP BE Pri !#2 N4236 P1254 PREFETCH 23 Int BE Pri !#2 N4237 P1255 MEMBAR !#2 N4238 P1256 BLD 16 -1 FP BE Pri !#2 N4239 P1257 MEMBAR !#2 N4240 P1258 BLD 29 -1 FP BE Pri !#2 N4241 P1259 MEMBAR !#2 N4242 P1260 REPLACEMENT 9 Int BE Nuc !#2 N4243 P1261 REPLACEMENT 23 Int BE Pri !#2 N4244 P1262 MEMBAR !#2 N4245 P1263 BLD 0 -1 FP BE Pri !#2 N4246 P1263 BLD 1 -1 FP BE Pri !#A N4245 N4246 !#2 N4247 P1263 BLD 2 -1 FP BE Pri !#2 N4248 P1263 BLD 3 -1 FP BE Pri !#2 N4249 P1263 BLD 4 -1 FP BE Pri !#2 N4250 P1264 MEMBAR !#2 N4251 P1265 REPLACEMENT 12 Int BE Pri !#2 N4252 P1266 REPLACEMENT 5 Int BE Sec !#2 N4253 P1267 LD 16 -1 FP BE Pri !#2 N4254 P1268 MEMBAR !#2 N4255 P1269 BSTC 30 0x408000a0 FP BE Pri !#2 N4256 P1270 MEMBAR !#2 N4257 P1271 BST 30 0x408000a1 FP BE Sec !#2 N4258 P1272 MEMBAR !#2 N4259 P1273 BLD 7 -1 FP BE Pri !#2 N4260 P1274 MEMBAR !#2 N4261 P1275 PREFETCH 6 Int BE Pri !#2 N4262 P1276 MEMBAR !#2 N4263 P1277 BSTC 14 0x408000a2 FP BE Pri !#2 N4264 P1278 MEMBAR !#2 N4265 P1279 BST 21 0x408000a3 FP BE Pri !#2 N4266 P1279 BST 22 0x408000a4 FP BE Pri !#A N4265 N4266 !#2 N4267 P1279 BST 23 0x408000a5 FP BE Pri !#2 N4268 P1280 MEMBAR !#2 N4269 P1281 BST 21 0x408000a6 FP BE Pri !#2 N4270 P1281 BST 22 0x408000a7 FP BE Pri !#A N4269 N4270 !#2 N4271 P1281 BST 23 0x408000a8 FP BE Pri !#2 N4272 P1282 MEMBAR !#2 N4273 P1283 REPLACEMENT 27 Int BE Sec !#2 N4274 P1284 ST 21 0x408000a9 FP BE Sec !#2 N4275 P1285 MEMBAR !#2 N4276 P1286 BST 33 0x408000aa FP BE Sec !#2 N4277 P1287 MEMBAR !#2 N4278 P1288 BLD 10 -1 FP BE Pri !#2 N4279 P1289 MEMBAR !#2 N4280 P1290 LD 18 -1 Int BE Sec Loop_exit !#2 N4281 P714 MEMBAR !#2 N4282 P715 BST 33 0x408000ab FP BE Pri !#2 N4283 P716 MEMBAR !#2 N4284 P717 REPLACEMENT 12 Int BE Pri !#2 N4285 P718 REPLACEMENT 13 Int BE Sec !#2 N4286 P719 ST 6 0x408000ac FP BE Pri !#2 N4287 P720 REPLACEMENT 5 Int BE Nuc !#2 N4288 P721 MEMBAR !#2 N4289 P722 BSTC 5 0x408000ad FP BE Pri !#2 N4290 P722 BSTC 6 0x408000ae FP BE Pri !#2 N4291 P723 MEMBAR !#2 N4292 P724 BLD 0 -1 FP BE Pri !#2 N4293 P724 BLD 1 -1 FP BE Pri !#A N4292 N4293 !#2 N4294 P724 BLD 2 -1 FP BE Pri !#2 N4295 P724 BLD 3 -1 FP BE Pri !#2 N4296 P724 BLD 4 -1 FP BE Pri !#2 N4297 P725 MEMBAR !#2 N4298 P726 BLD 24 -1 FP BE Sec !#2 N4299 P726 BLD 25 -1 FP BE Sec !#2 N4300 P727 MEMBAR !#2 N4301 P728 REPLACEMENT 9 Int BE Pri !#2 N4302 P729 MEMBAR !#2 N4303 P730 BST 0 0x408000af FP BE Pri !#2 N4304 P730 BST 1 0x408000b0 FP BE Pri !#A N4303 N4304 !#2 N4305 P730 BST 2 0x408000b1 FP BE Pri !#2 N4306 P730 BST 3 0x408000b2 FP BE Pri !#2 N4307 P730 BST 4 0x408000b3 FP BE Pri !#2 N4308 P731 MEMBAR !#2 N4309 P732 ST 9 0x408000b4 FP BE Sec !#2 N4310 P733 LD 26 -1 Int BE Pri !#2 N4311 P734 LD 21 -1 FP BE Sec !#2 N4312 P735 LD 11 -1 FP BE Sec !#2 N4313 P736 MEMBAR !#2 N4314 P737 BST 10 0x408000b5 FP BE Pri !#2 N4315 P738 MEMBAR !#2 N4316 P739 REPLACEMENT 7 Int BE Pri !#2 N4317 P740 ST 29 0x408000b6 FP BE Pri !#2 N4318 P741 LD 22 -1 Int BE Pri !#2 N4319 P742 REPLACEMENT 21 Int BE Pri !#2 N4320 P743 MEMBAR !#2 N4321 P744 BSTC 30 0x408000b7 FP BE Pri !#2 N4322 P745 MEMBAR !#2 N4323 P746 PREFETCH 24 Int BE Sec !#2 N4324 P747 REPLACEMENT 14 Int BE Nuc !#2 N4325 P748 PREFETCH 8 Int BE Nuc !#2 N4326 P749 MEMBAR !#2 N4327 P750 BLD 0 -1 FP BE Pri !#2 N4328 P750 BLD 1 -1 FP BE Pri !#A N4327 N4328 !#2 N4329 P750 BLD 2 -1 FP BE Pri !#2 N4330 P750 BLD 3 -1 FP BE Pri !#2 N4331 P750 BLD 4 -1 FP BE Pri !#2 N4332 P751 MEMBAR !#2 N4333 P752 PREFETCH 1 Int BE Pri !#2 N4334 P753 ST 30 0x1000015 Int BE Sec !#2 N4335 P754 PREFETCH 20 Int BE Nuc !#2 N4336 P755 MEMBAR !#2 N4337 P756 BLD 0 -1 FP BE Pri !#2 N4338 P756 BLD 1 -1 FP BE Pri !#A N4337 N4338 !#2 N4339 P756 BLD 2 -1 FP BE Pri !#2 N4340 P756 BLD 3 -1 FP BE Pri !#2 N4341 P756 BLD 4 -1 FP BE Pri !#2 N4342 P757 MEMBAR !#2 N4343 P758 BLD 11 -1 FP BE Pri !#2 N4344 P758 BLD 12 -1 FP BE Pri !#A N4343 N4344 !#2 N4345 P758 BLD 13 -1 FP BE Pri !#2 N4346 P759 MEMBAR !#2 N4347 P760 LD 24 -1 FP BE Pri !#2 N4348 P761 LD 23 -1 Int BE Pri !#2 N4349 P762 LD 16 -1 FP BE Pri !#2 N4350 P763 MEMBAR !#2 N4351 P764 BLD 0 -1 FP BE Pri !#2 N4352 P764 BLD 1 -1 FP BE Pri !#A N4351 N4352 !#2 N4353 P764 BLD 2 -1 FP BE Pri !#2 N4354 P764 BLD 3 -1 FP BE Pri !#2 N4355 P764 BLD 4 -1 FP BE Pri !#2 N4356 P765 MEMBAR !#2 N4357 P766 BST 17 0x408000b8 FP BE Sec !#2 N4358 P767 MEMBAR !#2 N4359 P768 BLD 5 -1 FP BE Pri !#2 N4360 P768 BLD 6 -1 FP BE Pri !#2 N4361 P769 MEMBAR !#2 N4362 P770 PREFETCH 19 Int BE Pri !#2 N4363 P771 LD 7 -1 FP BE Pri !#2 N4364 P772 IDC_FLIP 12 Int BE Pri !#2 N4365 P773 MEMBAR !#2 N4366 P774 BSTC 0 0x408000b9 FP BE Pri !#2 N4367 P774 BSTC 1 0x408000ba FP BE Pri !#A N4366 N4367 !#2 N4368 P774 BSTC 2 0x408000bb FP BE Pri !#2 N4369 P774 BSTC 3 0x408000bc FP BE Pri !#2 N4370 P774 BSTC 4 0x408000bd FP BE Pri !#2 N4371 P775 MEMBAR !#2 N4372 P776 BSTC 8 0x408000be FP BE Pri !#2 N4373 P776 BSTC 9 0x408000bf FP BE Pri !#2 N4374 P777 MEMBAR !#2 N4375 P778 IDC_FLIP 24 Int BE Pri !#2 N4376 P779 MEMBAR !#2 N4377 P780 BSTC 14 0x408000c0 FP BE Pri !#2 N4378 P781 MEMBAR !#2 N4379 P782 LD 11 -1 Int BE Pri !#2 N4380 P783 ST 0 0x408000c1 FP BE Nuc !#2 N4381 P784 ST 31 0x408000c2 FP BE Pri !#2 N4382 P785 REPLACEMENT 24 Int BE Pri !#2 N4383 P786 REPLACEMENT 27 Int BE Sec !#2 N4384 P787 MEMBAR !#2 N4385 P788 BST 21 0x408000c3 FP BE Pri !#2 N4386 P788 BST 22 0x408000c4 FP BE Pri !#A N4385 N4386 !#2 N4387 P788 BST 23 0x408000c5 FP BE Pri !#2 N4388 P789 MEMBAR !#2 N4389 P790 BLD 0 -1 FP BE Pri !#2 N4390 P790 BLD 1 -1 FP BE Pri !#A N4389 N4390 !#2 N4391 P790 BLD 2 -1 FP BE Pri !#2 N4392 P790 BLD 3 -1 FP BE Pri !#2 N4393 P790 BLD 4 -1 FP BE Pri !#2 N4394 P791 MEMBAR !#2 N4395 P792 LD 28 -1 FP BE Pri !#2 N4396 P793 LD 29 -1 FP BE Nuc !#2 N4397 P794 PREFETCH 0 Int BE Pri !#2 N4398 P795 MEMBAR !#2 N4399 P796 BST 32 0x408000c6 FP BE Pri !#2 N4400 P797 MEMBAR !#2 N4401 P798 BLD 5 -1 FP BE Pri !#2 N4402 P798 BLD 6 -1 FP BE Pri !#2 N4403 P799 MEMBAR !#2 N4404 P800 BSTC 33 0x408000c7 FP BE Pri !#2 N4405 P801 MEMBAR !#2 N4406 P802 BLD 16 -1 FP BE Pri !#2 N4407 P803 MEMBAR !#2 N4408 P804 ST 25 0x408000c8 FP BE Sec !#2 N4409 P805 LD 16 -1 FP BE Pri !#2 N4410 P806 MEMBAR !#2 N4411 P807 BLD 17 -1 FP BE Sec !#2 N4412 P808 MEMBAR !#2 N4413 P809 BLD 21 -1 FP BE Pri !#2 N4414 P809 BLD 22 -1 FP BE Pri !#A N4413 N4414 !#2 N4415 P809 BLD 23 -1 FP BE Pri !#2 N4416 P810 MEMBAR !#2 N4417 P811 BST 0 0x408000c9 FP BE Pri !#2 N4418 P811 BST 1 0x408000ca FP BE Pri !#A N4417 N4418 !#2 N4419 P811 BST 2 0x408000cb FP BE Pri !#2 N4420 P811 BST 3 0x408000cc FP BE Pri !#2 N4421 P811 BST 4 0x408000cd FP BE Pri !#2 N4422 P812 MEMBAR !#2 N4423 P813 BLD 0 -1 FP BE Pri !#2 N4424 P813 BLD 1 -1 FP BE Pri !#A N4423 N4424 !#2 N4425 P813 BLD 2 -1 FP BE Pri !#2 N4426 P813 BLD 3 -1 FP BE Pri !#2 N4427 P813 BLD 4 -1 FP BE Pri !#2 N4428 P814 MEMBAR !#2 N4429 P815 BLD 33 -1 FP BE Sec !#2 N4430 P816 MEMBAR !#2 N4431 P817 BSTC 11 0x408000ce FP BE Sec !#2 N4432 P817 BSTC 12 0x408000cf FP BE Sec !#A N4431 N4432 !#2 N4433 P817 BSTC 13 0x408000d0 FP BE Sec !#2 N4434 P818 MEMBAR !#2 N4435 P819 LD 10 -1 Int BE Pri !#2 N4436 P820 REPLACEMENT 27 Int BE Pri !#2 N4437 P821 PREFETCH 8 Int BE Pri !#2 N4438 P822 MEMBAR !#2 N4439 P823 BLD 14 -1 FP BE Pri !#2 N4440 P824 MEMBAR !#2 N4441 P825 BST 11 0x408000d1 FP BE Pri !#2 N4442 P825 BST 12 0x408000d2 FP BE Pri !#A N4441 N4442 !#2 N4443 P825 BST 13 0x408000d3 FP BE Pri !#2 N4444 P826 MEMBAR !#2 N4445 P827 BLD 21 -1 FP BE Pri !#2 N4446 P827 BLD 22 -1 FP BE Pri !#A N4445 N4446 !#2 N4447 P827 BLD 23 -1 FP BE Pri !#2 N4448 P828 MEMBAR !#2 N4449 P829 IDC_FLIP 23 Int BE Pri !#2 N4450 P830 MEMBAR !#2 N4451 P831 BLD 21 -1 FP BE Pri !#2 N4452 P831 BLD 22 -1 FP BE Pri !#A N4451 N4452 !#2 N4453 P831 BLD 23 -1 FP BE Pri !#2 N4454 P832 MEMBAR !#2 N4455 P833 BSTC 19 0x408000d4 FP BE Pri !#2 N4456 P834 MEMBAR !#2 N4457 P835 BLD 16 -1 FP BE Pri !#2 N4458 P836 MEMBAR !#2 N4459 P837 REPLACEMENT 33 Int BE Pri !#2 N4460 P838 REPLACEMENT 26 Int BE Nuc !#2 N4461 P839 IDC_FLIP 5 Int BE Pri !#2 N4462 P840 MEMBAR !#2 N4463 P841 BSTC 10 0x408000d5 FP BE Pri !#2 N4464 P842 MEMBAR !#2 N4465 P843 BSTC 11 0x408000d6 FP BE Pri !#2 N4466 P843 BSTC 12 0x408000d7 FP BE Pri !#A N4465 N4466 !#2 N4467 P843 BSTC 13 0x408000d8 FP BE Pri !#2 N4468 P844 MEMBAR !#2 N4469 P845 BLD 5 -1 FP BE Pri !#2 N4470 P845 BLD 6 -1 FP BE Pri !#2 N4471 P846 MEMBAR !#2 N4472 P847 BLD 24 -1 FP BE Pri !#2 N4473 P847 BLD 25 -1 FP BE Pri !#2 N4474 P848 MEMBAR !#2 N4475 P849 LD 7 -1 FP BE Pri !#2 N4476 P850 MEMBAR !#2 N4477 P851 BLD 17 -1 FP BE Sec !#2 N4478 P852 MEMBAR !#2 N4479 P853 BLD 19 -1 FP BE Pri !#2 N4480 P854 MEMBAR !#2 N4481 P855 REPLACEMENT 31 Int BE Pri !#2 N4482 P856 ST 26 0x408000d9 FP BE Sec !#2 N4483 P857 PREFETCH 9 Int BE Nuc !#2 N4484 P858 MEMBAR !#2 N4485 P859 BST 33 0x408000da FP BE Pri !#2 N4486 P860 MEMBAR !#2 N4487 P861 REPLACEMENT 10 Int BE Sec !#2 N4488 P862 MEMBAR !#2 N4489 P863 BLD 15 -1 FP BE Pri !#2 N4490 P864 MEMBAR !#2 N4491 P865 LD 31 -1 FP BE Pri !#2 N4492 P866 REPLACEMENT 25 Int BE Pri !#2 N4493 P867 ST 27 0x1000016 Int BE Pri !#2 N4494 P868 PREFETCH 27 Int LE Pri !#2 N4495 P869 MEMBAR !#2 N4496 P870 BLD 8 -1 FP BE Pri !#2 N4497 P870 BLD 9 -1 FP BE Pri !#2 N4498 P871 MEMBAR !#2 N4499 P872 BST 8 0x408000db FP BE Pri !#2 N4500 P872 BST 9 0x408000dc FP BE Pri !#2 N4501 P873 MEMBAR !#2 N4502 P874 BLD 14 -1 FP BE Pri !#2 N4503 P875 MEMBAR !#2 N4504 P876 REPLACEMENT 14 Int BE Pri !#2 N4505 P877 LD 8 -1 Int LE Pri !#2 N4506 P878 REPLACEMENT 17 Int BE Pri !#2 N4507 P879 MEMBAR !#2 N4508 P880 BLD 5 -1 FP BE Pri !#2 N4509 P880 BLD 6 -1 FP BE Pri !#2 N4510 P881 MEMBAR !#2 N4511 P882 ST 28 0x1000017 Int BE Pri !#2 N4512 P883 MEMBAR !#2 N4513 P884 BSTC 0 0x408000dd FP BE Pri !#2 N4514 P884 BSTC 1 0x408000de FP BE Pri !#A N4513 N4514 !#2 N4515 P884 BSTC 2 0x408000df FP BE Pri !#2 N4516 P884 BSTC 3 0x408000e0 FP BE Pri !#2 N4517 P884 BSTC 4 0x408000e1 FP BE Pri !#2 N4518 P885 MEMBAR !#2 N4519 P886 BLD 7 -1 FP BE Pri !#2 N4520 P887 MEMBAR !#2 N4521 P888 LD 18 -1 Int BE Sec !#2 N4522 P889 REPLACEMENT 13 Int BE Pri !#2 N4523 P890 ST 19 0x1000018 Int BE Pri !#2 N4524 P891 MEMBAR !#2 N4525 P892 BST 24 0x408000e2 FP BE Pri !#2 N4526 P892 BST 25 0x408000e3 FP BE Pri !#2 N4527 P893 MEMBAR !#2 N4528 P894 BLD 0 -1 FP BE Pri !#2 N4529 P894 BLD 1 -1 FP BE Pri !#A N4528 N4529 !#2 N4530 P894 BLD 2 -1 FP BE Pri !#2 N4531 P894 BLD 3 -1 FP BE Pri !#2 N4532 P894 BLD 4 -1 FP BE Pri !#2 N4533 P895 MEMBAR !#2 N4534 P896 ST 33 0x1000019 Int BE Sec !#2 N4535 P897 MEMBAR !#2 N4536 P898 BST 19 0x408000e4 FP BE Sec !#2 N4537 P899 MEMBAR !#2 N4538 P900 BLD 24 -1 FP BE Pri !#2 N4539 P900 BLD 25 -1 FP BE Pri !#2 N4540 P901 MEMBAR !#2 N4541 P902 BSTC 26 0x408000e5 FP BE Pri !#2 N4542 P902 BSTC 27 0x408000e6 FP BE Pri !#2 N4543 P903 MEMBAR !#2 N4544 P904 BLD 0 -1 FP BE Pri !#2 N4545 P904 BLD 1 -1 FP BE Pri !#A N4544 N4545 !#2 N4546 P904 BLD 2 -1 FP BE Pri !#2 N4547 P904 BLD 3 -1 FP BE Pri !#2 N4548 P904 BLD 4 -1 FP BE Pri !#2 N4549 P905 MEMBAR !#2 N4550 P906 REPLACEMENT 16 Int BE Pri !#2 N4551 P907 LD 33 -1 Int BE Pri !#2 N4552 P908 MEMBAR !#2 N4553 P909 BLD 19 -1 FP BE Pri !#2 N4554 P910 MEMBAR !#2 N4555 P911 BST 33 0x408000e7 FP BE Pri !#2 N4556 P912 MEMBAR !#2 N4557 P913 REPLACEMENT 25 Int BE Pri !#2 N4558 P914 PREFETCH 11 Int BE Pri !#2 N4559 P915 ST 16 0x408000e8 FP BE Sec !#2 N4560 P916 ST 32 0x100001a Int BE Pri !#2 N4561 P917 MEMBAR !#2 N4562 P918 BST 0 0x408000e9 FP BE Pri !#2 N4563 P918 BST 1 0x408000ea FP BE Pri !#A N4562 N4563 !#2 N4564 P918 BST 2 0x408000eb FP BE Pri !#2 N4565 P918 BST 3 0x408000ec FP BE Pri !#2 N4566 P918 BST 4 0x408000ed FP BE Pri !#2 N4567 P919 MEMBAR !#2 N4568 P920 REPLACEMENT 29 Int BE Pri !#2 N4569 P921 ST 15 0x100001b Int BE Pri !#2 N4570 P922 MEMBAR !#2 N4571 P923 BSTC 10 0x408000ee FP BE Pri !#2 N4572 P924 MEMBAR !#2 N4573 P925 BLD 18 -1 FP BE Pri !#2 N4574 P926 MEMBAR !#2 N4575 P927 BSTC 15 0x408000ef FP BE Sec !#2 N4576 P928 MEMBAR !#2 N4577 P929 BSTC 16 0x408000f0 FP BE Pri !#2 N4578 P930 MEMBAR !#2 N4579 P931 REPLACEMENT 2 Int BE Pri !#2 N4580 P932 PREFETCH 25 Int BE Sec !#2 N4581 P933 MEMBAR !#2 N4582 P934 BST 24 0x408000f1 FP BE Sec !#2 N4583 P934 BST 25 0x408000f2 FP BE Sec !#2 N4584 P935 MEMBAR !#2 N4585 P936 ST 14 0x100001c Int BE Pri !#2 N4586 P937 REPLACEMENT 8 Int BE Nuc !#2 N4587 P938 MEMBAR !#2 N4588 P939 BLD 28 -1 FP BE Pri !#2 N4589 P940 MEMBAR !#2 N4590 P941 REPLACEMENT 26 Int BE Pri !#2 N4591 P942 MEMBAR !#2 N4592 P943 BST 21 0x408000f3 FP BE Pri !#2 N4593 P943 BST 22 0x408000f4 FP BE Pri !#A N4592 N4593 !#2 N4594 P943 BST 23 0x408000f5 FP BE Pri !#2 N4595 P944 MEMBAR !#2 N4596 P945 ST 18 0x100001d Int BE Pri !#2 N4597 P946 LD 1 -1 Int BE Pri !#2 N4598 P947 ST 14 0x408000f6 FP BE Pri !#2 N4599 P948 MEMBAR !#2 N4600 P949 BLD 26 -1 FP BE Pri !#2 N4601 P949 BLD 27 -1 FP BE Pri !#2 N4602 P950 MEMBAR !#2 N4603 P951 BST 15 0x408000f7 FP BE Pri !#2 N4604 P952 MEMBAR !#2 N4605 P953 LD 33 -1 FP BE Pri !#2 N4606 P954 MEMBAR !#2 N4607 P955 BLD 0 -1 FP BE Pri !#2 N4608 P955 BLD 1 -1 FP BE Pri !#A N4607 N4608 !#2 N4609 P955 BLD 2 -1 FP BE Pri !#2 N4610 P955 BLD 3 -1 FP BE Pri !#2 N4611 P955 BLD 4 -1 FP BE Pri !#2 N4612 P956 MEMBAR !#2 N4613 P957 LD 5 -1 Int BE Pri !#2 N4614 P958 LD 10 -1 FP BE Pri !#2 N4615 P959 IDC_FLIP 8 Int BE Pri !#2 N4616 P960 LD 12 -1 FP BE Sec !#2 N4617 P961 ST 5 0x408000f8 FP BE Sec !#2 N4618 P962 LD 14 -1 FP BE Pri !#2 N4619 P963 MEMBAR !#2 N4620 P964 BSTC 14 0x408000f9 FP BE Pri !#2 N4621 P965 MEMBAR !#2 N4622 P966 LD 0 -1 FP BE Pri !#2 N4623 P967 MEMBAR !#2 N4624 P968 BLD 0 -1 FP BE Sec !#2 N4625 P968 BLD 1 -1 FP BE Sec !#A N4624 N4625 !#2 N4626 P968 BLD 2 -1 FP BE Sec !#2 N4627 P968 BLD 3 -1 FP BE Sec !#2 N4628 P968 BLD 4 -1 FP BE Sec !#2 N4629 P969 MEMBAR !#2 N4630 P970 REPLACEMENT 16 Int BE Pri !#2 N4631 P971 MEMBAR !#2 N4632 P972 BST 19 0x408000fa FP BE Pri !#2 N4633 P973 MEMBAR !#2 N4634 P974 BST 19 0x408000fb FP BE Pri !#2 N4635 P975 MEMBAR !#2 N4636 P976 ST 23 0x408000fc FP BE Pri !#2 N4637 P977 ST 1 0x408000fd FP BE Pri !#2 N4638 P978 PREFETCH 11 Int BE Pri !#2 N4639 P979 MEMBAR !#2 N4640 P980 BST 11 0x408000fe FP BE Pri !#2 N4641 P980 BST 12 0x408000ff FP BE Pri !#A N4640 N4641 !#2 N4642 P980 BST 13 0x40800100 FP BE Pri !#2 N4643 P981 MEMBAR !#2 N4644 P982 REPLACEMENT 9 Int BE Pri !#2 N4645 P983 ST 13 0x40800101 FP BE Pri !#2 N4646 P984 REPLACEMENT 20 Int BE Pri !#2 N4647 P985 ST 12 0x100001e Int BE Pri !#2 N4648 P986 LD 3 -1 Int BE Sec !#2 N4649 P987 ST 12 0x100001f Int BE Nuc !#2 N4650 P988 MEMBAR !#2 N4651 P989 BST 28 0x40800102 FP BE Sec !#2 N4652 P990 MEMBAR !#2 N4653 P991 LD 25 -1 Int BE Pri !#2 N4654 P992 LD 33 -1 FP BE Pri !#2 N4655 P993 MEMBAR !#2 N4656 P994 BLD 8 -1 FP BE Pri !#2 N4657 P994 BLD 9 -1 FP BE Pri !#2 N4658 P995 MEMBAR !#2 N4659 P996 BLD 5 -1 FP BE Pri !#2 N4660 P996 BLD 6 -1 FP BE Pri !#2 N4661 P997 MEMBAR !#2 N4662 P998 REPLACEMENT 18 Int BE Nuc !#2 N4663 P999 MEMBAR !#2 N4664 P1000 BLD 16 -1 FP BE Pri !#2 N4665 P1001 MEMBAR !#2 N4666 P1002 BLD 28 -1 FP BE Pri !#2 N4667 P1003 MEMBAR !#2 N4668 P1004 REPLACEMENT 16 Int BE Sec !#2 N4669 P1005 LD 4 -1 FP BE Pri !#2 N4670 P1006 MEMBAR !#2 N4671 P1007 BLD 28 -1 FP BE Pri !#2 N4672 P1008 MEMBAR !#2 N4673 P1009 LD 33 -1 Int BE Pri !#2 N4674 P1010 ST 1 0x1000020 Int BE Pri !#2 N4675 P1011 MEMBAR !#2 N4676 P1012 BST 0 0x40800103 FP BE Pri !#2 N4677 P1012 BST 1 0x40800104 FP BE Pri !#A N4676 N4677 !#2 N4678 P1012 BST 2 0x40800105 FP BE Pri !#2 N4679 P1012 BST 3 0x40800106 FP BE Pri !#2 N4680 P1012 BST 4 0x40800107 FP BE Pri !#2 N4681 P1013 MEMBAR !#2 N4682 P1014 BST 20 0x40800108 FP BE Sec !#2 N4683 P1015 MEMBAR !#2 N4684 P1016 ST 8 0x1000021 Int BE Pri !#2 N4685 P1017 PREFETCH 2 Int BE Pri !#2 N4686 P1018 ST 23 0x1000022 Int BE Pri !#2 N4687 P1019 MEMBAR !#2 N4688 P1020 BSTC 21 0x40800109 FP BE Pri !#2 N4689 P1020 BSTC 22 0x4080010a FP BE Pri !#A N4688 N4689 !#2 N4690 P1020 BSTC 23 0x4080010b FP BE Pri !#2 N4691 P1021 MEMBAR !#2 N4692 P1022 ST 29 0x4080010c FP BE Pri !#2 N4693 P1023 MEMBAR !#2 N4694 P1024 BSTC 21 0x4080010d FP BE Pri !#2 N4695 P1024 BSTC 22 0x4080010e FP BE Pri !#A N4694 N4695 !#2 N4696 P1024 BSTC 23 0x4080010f FP BE Pri !#2 N4697 P1025 MEMBAR !#2 N4698 P1026 REPLACEMENT 1 Int BE Pri !#2 N4699 P1027 REPLACEMENT 30 Int BE Nuc !#2 N4700 P1028 REPLACEMENT 28 Int BE Pri !#2 N4701 P1029 REPLACEMENT 8 Int BE Pri !#2 N4702 P1030 LD 32 -1 FP BE Pri !#2 N4703 P1031 REPLACEMENT 2 Int BE Pri !#2 N4704 P1032 ST 21 0x40800110 FP BE Pri !#2 N4705 P1033 REPLACEMENT 25 Int BE Pri !#2 N4706 P1034 MEMBAR !#2 N4707 P1035 BLD 15 -1 FP BE Pri !#2 N4708 P1036 MEMBAR !#2 N4709 P1037 BSTC 5 0x40800111 FP BE Pri !#2 N4710 P1037 BSTC 6 0x40800112 FP BE Pri !#2 N4711 P1038 MEMBAR !#2 N4712 P1039 BSTC 21 0x40800113 FP BE Pri !#2 N4713 P1039 BSTC 22 0x40800114 FP BE Pri !#A N4712 N4713 !#2 N4714 P1039 BSTC 23 0x40800115 FP BE Pri !#2 N4715 P1040 MEMBAR !#2 N4716 P1041 ST 0 0x40800116 FP BE Pri !#2 N4717 P1042 ST 11 0x40800117 FP BE Pri !#2 N4718 P1043 MEMBAR !#2 N4719 P1044 BSTC 7 0x40800118 FP BE Pri !#2 N4720 P1045 MEMBAR !#2 N4721 P1046 REPLACEMENT 28 Int BE Pri !#2 N4722 P1047 LD 3 -1 FP BE Pri !#2 N4723 P1048 LD 19 -1 Int BE Pri !#2 N4724 P1049 PREFETCH 19 Int BE Nuc !#2 N4725 P1050 PREFETCH 6 Int BE Sec !#2 N4726 P1051 IDC_FLIP 9 Int BE Pri !#2 N4727 P1052 MEMBAR !#2 N4728 P1053 BST 14 0x40800119 FP BE Pri !#2 N4729 P1054 MEMBAR !#2 N4730 P1055 ST 3 0x4080011a FP BE Pri !#2 N4731 P1056 MEMBAR !#2 N4732 P1057 BLD 32 -1 FP BE Sec !#2 N4733 P1058 MEMBAR !#2 N4734 P1059 BSTC 0 0x4080011b FP BE Pri !#2 N4735 P1059 BSTC 1 0x4080011c FP BE Pri !#A N4734 N4735 !#2 N4736 P1059 BSTC 2 0x4080011d FP BE Pri !#2 N4737 P1059 BSTC 3 0x4080011e FP BE Pri !#2 N4738 P1059 BSTC 4 0x4080011f FP BE Pri !#2 N4739 P1060 MEMBAR !#2 N4740 P1061 BSTC 26 0x40800120 FP BE Pri !#2 N4741 P1061 BSTC 27 0x40800121 FP BE Pri !#2 N4742 P1062 MEMBAR !#2 N4743 P1063 BSTC 29 0x40800122 FP BE Pri !#2 N4744 P1064 MEMBAR !#2 N4745 P1065 BST 29 0x40800123 FP BE Pri !#2 N4746 P1066 MEMBAR !#2 N4747 P1067 IDC_FLIP 0 Int BE Pri !#2 N4748 P1068 MEMBAR !#2 N4749 P1069 BLD 8 -1 FP BE Pri !#2 N4750 P1069 BLD 9 -1 FP BE Pri !#2 N4751 P1070 MEMBAR !#2 N4752 P1071 BLD 26 -1 FP BE Pri !#2 N4753 P1071 BLD 27 -1 FP BE Pri !#2 N4754 P1072 MEMBAR !#2 N4755 P1073 PREFETCH 18 Int LE Pri !#2 N4756 P1074 PREFETCH 3 Int BE Pri !#2 N4757 P1075 MEMBAR !#2 N4758 P1076 BSTC 0 0x40800124 FP BE Pri !#2 N4759 P1076 BSTC 1 0x40800125 FP BE Pri !#A N4758 N4759 !#2 N4760 P1076 BSTC 2 0x40800126 FP BE Pri !#2 N4761 P1076 BSTC 3 0x40800127 FP BE Pri !#2 N4762 P1076 BSTC 4 0x40800128 FP BE Pri !#2 N4763 P1077 MEMBAR !#2 N4764 P1078 ST 30 0x40800129 FP BE Pri !#2 N4765 P1079 MEMBAR !#2 N4766 P1080 BLD 29 -1 FP BE Sec !#2 N4767 P1081 MEMBAR !#2 N4768 P1082 BLD 0 -1 FP BE Pri !#2 N4769 P1082 BLD 1 -1 FP BE Pri !#A N4768 N4769 !#2 N4770 P1082 BLD 2 -1 FP BE Pri !#2 N4771 P1082 BLD 3 -1 FP BE Pri !#2 N4772 P1082 BLD 4 -1 FP BE Pri !#2 N4773 P1083 MEMBAR !#2 N4774 P1084 BST 21 0x4080012a FP BE Sec !#2 N4775 P1084 BST 22 0x4080012b FP BE Sec !#A N4774 N4775 !#2 N4776 P1084 BST 23 0x4080012c FP BE Sec !#2 N4777 P1085 MEMBAR !#2 N4778 P1086 BST 26 0x4080012d FP BE Pri !#2 N4779 P1086 BST 27 0x4080012e FP BE Pri !#2 N4780 P1087 MEMBAR !#2 N4781 P1088 BSTC 32 0x4080012f FP BE Pri !#2 N4782 P1089 MEMBAR !#2 N4783 P1090 BSTC 10 0x40800130 FP BE Pri !#2 N4784 P1091 MEMBAR !#2 N4785 P1092 PREFETCH 27 Int BE Pri !#2 N4786 P1093 REPLACEMENT 18 Int BE Pri !#2 N4787 P1094 PREFETCH 25 Int BE Pri !#2 N4788 P1095 REPLACEMENT 24 Int BE Pri !#2 N4789 P1096 MEMBAR !#2 N4790 P1097 BSTC 31 0x40800131 FP BE Pri !#2 N4791 P1098 MEMBAR !#2 N4792 P1099 REPLACEMENT 27 Int BE Pri !#2 N4793 P1100 MEMBAR !#2 N4794 P1101 BLD 7 -1 FP BE Pri !#2 N4795 P1102 MEMBAR !#2 N4796 P1103 REPLACEMENT 21 Int BE Pri !#2 N4797 P1104 REPLACEMENT 33 Int BE Pri !#2 N4798 P1105 MEMBAR !#2 N4799 P1106 BLD 19 -1 FP BE Pri !#2 N4800 P1107 MEMBAR !#2 N4801 P1108 BST 28 0x40800132 FP BE Sec !#2 N4802 P1109 MEMBAR !#2 N4803 P1110 BSTC 18 0x40800133 FP BE Sec !#2 N4804 P1111 MEMBAR !#2 N4805 P1112 BST 8 0x40800134 FP BE Pri !#2 N4806 P1112 BST 9 0x40800135 FP BE Pri !#2 N4807 P1113 MEMBAR !#2 N4808 P1114 BLD 29 -1 FP BE Pri !#2 N4809 P1115 MEMBAR !#2 N4810 P1116 ST 13 0x40800136 FP BE Nuc !#2 N4811 P1117 REPLACEMENT 10 Int BE Nuc !#2 N4812 P1118 MEMBAR !#2 N4813 P1119 BLD 7 -1 FP BE Pri !#2 N4814 P1120 MEMBAR !#2 N4815 P1121 BLD 21 -1 FP BE Pri !#2 N4816 P1121 BLD 22 -1 FP BE Pri !#A N4815 N4816 !#2 N4817 P1121 BLD 23 -1 FP BE Pri !#2 N4818 P1122 MEMBAR !#2 N4819 P1123 BLD 21 -1 FP BE Pri !#2 N4820 P1123 BLD 22 -1 FP BE Pri !#A N4819 N4820 !#2 N4821 P1123 BLD 23 -1 FP BE Pri !#2 N4822 P1124 MEMBAR !#2 N4823 P1125 REPLACEMENT 23 Int BE Pri !#2 N4824 P1126 MEMBAR !#2 N4825 P1127 BLD 8 -1 FP BE Pri !#2 N4826 P1127 BLD 9 -1 FP BE Pri !#2 N4827 P1128 MEMBAR !#2 N4828 P1129 REPLACEMENT 14 Int BE Pri !#2 N4829 P1130 MEMBAR !#2 N4830 P1131 BLD 0 -1 FP BE Pri !#2 N4831 P1131 BLD 1 -1 FP BE Pri !#A N4830 N4831 !#2 N4832 P1131 BLD 2 -1 FP BE Pri !#2 N4833 P1131 BLD 3 -1 FP BE Pri !#2 N4834 P1131 BLD 4 -1 FP BE Pri !#2 N4835 P1132 MEMBAR !#2 N4836 P1133 BLD 19 -1 FP BE Sec !#2 N4837 P1134 MEMBAR !#2 N4838 P1135 LD 24 -1 Int BE Sec !#2 N4839 P1136 REPLACEMENT 2 Int BE Pri !#2 N4840 P1137 REPLACEMENT 23 Int BE Sec !#2 N4841 P1138 MEMBAR !#2 N4842 P1139 BLD 33 -1 FP BE Pri !#2 N4843 P1140 MEMBAR !#2 N4844 P1141 LD 22 -1 Int BE Sec !#2 N4845 P1142 REPLACEMENT 18 Int BE Pri !#2 N4846 P1143 MEMBAR !#2 N4847 P1144 BLD 21 -1 FP BE Pri !#2 N4848 P1144 BLD 22 -1 FP BE Pri !#A N4847 N4848 !#2 N4849 P1144 BLD 23 -1 FP BE Pri !#2 N4850 P1145 MEMBAR !#2 N4851 P1146 BLD 21 -1 FP BE Pri !#2 N4852 P1146 BLD 22 -1 FP BE Pri !#A N4851 N4852 !#2 N4853 P1146 BLD 23 -1 FP BE Pri !#2 N4854 P1147 MEMBAR !#2 N4855 P1148 REPLACEMENT 19 Int BE Pri !#2 N4856 P1149 MEMBAR !#2 N4857 P1150 BSTC 33 0x40800137 FP BE Pri !#2 N4858 P1151 MEMBAR !#2 N4859 P1152 BLD 19 -1 FP BE Pri !#2 N4860 P1153 MEMBAR !#2 N4861 P1154 BST 11 0x40800138 FP BE Pri !#2 N4862 P1154 BST 12 0x40800139 FP BE Pri !#A N4861 N4862 !#2 N4863 P1154 BST 13 0x4080013a FP BE Pri !#2 N4864 P1155 MEMBAR !#2 N4865 P1156 BLD 16 -1 FP BE Pri !#2 N4866 P1157 MEMBAR !#2 N4867 P1158 REPLACEMENT 31 Int BE Nuc !#2 N4868 P1159 MEMBAR !#2 N4869 P1160 BLD 11 -1 FP BE Sec !#2 N4870 P1160 BLD 12 -1 FP BE Sec !#A N4869 N4870 !#2 N4871 P1160 BLD 13 -1 FP BE Sec !#2 N4872 P1161 MEMBAR !#2 N4873 P1162 REPLACEMENT 4 Int BE Nuc !#2 N4874 P1163 REPLACEMENT 24 Int BE Sec !#2 N4875 P1164 PREFETCH 13 Int BE Pri !#2 N4876 P1165 ST 29 0x4080013b FP BE Sec !#2 N4877 P1166 ST 32 0x1000023 Int BE Pri !#2 N4878 P1167 REPLACEMENT 1 Int BE Pri !#2 N4879 P1168 MEMBAR !#2 N4880 P1169 BSTC 33 0x4080013c FP BE Pri !#2 N4881 P1170 MEMBAR !#2 N4882 P1171 BST 18 0x4080013d FP BE Pri !#2 N4883 P1172 MEMBAR !#2 N4884 P1173 REPLACEMENT 1 Int BE Nuc !#2 N4885 P1174 MEMBAR !#2 N4886 P1175 BLD 0 -1 FP BE Pri !#2 N4887 P1175 BLD 1 -1 FP BE Pri !#A N4886 N4887 !#2 N4888 P1175 BLD 2 -1 FP BE Pri !#2 N4889 P1175 BLD 3 -1 FP BE Pri !#2 N4890 P1175 BLD 4 -1 FP BE Pri !#2 N4891 P1176 MEMBAR !#2 N4892 P1177 IDC_FLIP 13 Int BE Pri !#2 N4893 P1178 MEMBAR !#2 N4894 P1179 BST 11 0x4080013e FP BE Pri !#2 N4895 P1179 BST 12 0x4080013f FP BE Pri !#A N4894 N4895 !#2 N4896 P1179 BST 13 0x40800140 FP BE Pri !#2 N4897 P1180 MEMBAR !#2 N4898 P1181 ST 25 0x1000024 Int BE Nuc !#2 N4899 P1182 ST 5 0x1000025 Int BE Pri !#2 N4900 P1183 MEMBAR !#2 N4901 P1184 BLD 8 -1 FP BE Pri !#2 N4902 P1184 BLD 9 -1 FP BE Pri !#2 N4903 P1185 MEMBAR !#2 N4904 P1186 BLD 21 -1 FP BE Pri !#2 N4905 P1186 BLD 22 -1 FP BE Pri !#A N4904 N4905 !#2 N4906 P1186 BLD 23 -1 FP BE Pri !#2 N4907 P1187 MEMBAR !#2 N4908 P1188 BSTC 24 0x40800141 FP BE Pri !#2 N4909 P1188 BSTC 25 0x40800142 FP BE Pri !#2 N4910 P1189 MEMBAR !#2 N4911 P1190 REPLACEMENT 21 Int BE Sec !#2 N4912 P1191 REPLACEMENT 16 Int BE Pri !#2 N4913 P1192 REPLACEMENT 32 Int BE Pri !#2 N4914 P1193 MEMBAR !#2 N4915 P1194 BSTC 20 0x40800143 FP BE Pri !#2 N4916 P1195 MEMBAR !#2 N4917 P1196 LD 2 -1 FP BE Nuc !#2 N4918 P1197 PREFETCH 23 Int BE Pri !#2 N4919 P1198 MEMBAR !#2 N4920 P1199 BLD 19 -1 FP BE Pri !#2 N4921 P1200 MEMBAR !#2 N4922 P1201 BLD 11 -1 FP BE Pri !#2 N4923 P1201 BLD 12 -1 FP BE Pri !#A N4922 N4923 !#2 N4924 P1201 BLD 13 -1 FP BE Pri !#2 N4925 P1202 MEMBAR !#2 N4926 P1203 BLD 0 -1 FP BE Pri !#2 N4927 P1203 BLD 1 -1 FP BE Pri !#A N4926 N4927 !#2 N4928 P1203 BLD 2 -1 FP BE Pri !#2 N4929 P1203 BLD 3 -1 FP BE Pri !#2 N4930 P1203 BLD 4 -1 FP BE Pri !#2 N4931 P1204 MEMBAR !#2 N4932 P1205 LD 30 -1 Int BE Pri !#2 N4933 P1206 IDC_FLIP 3 Int BE Pri !#2 N4934 P1207 MEMBAR !#2 N4935 P1208 BLD 11 -1 FP BE Pri !#2 N4936 P1208 BLD 12 -1 FP BE Pri !#A N4935 N4936 !#2 N4937 P1208 BLD 13 -1 FP BE Pri !#2 N4938 P1209 MEMBAR !#2 N4939 P1210 BLD 7 -1 FP BE Pri !#2 N4940 P1211 MEMBAR !#2 N4941 P1212 BST 26 0x40800144 FP BE Pri !#2 N4942 P1212 BST 27 0x40800145 FP BE Pri !#2 N4943 P1213 MEMBAR !#2 N4944 P1214 BSTC 7 0x40800146 FP BE Pri !#2 N4945 P1215 MEMBAR !#2 N4946 P1216 BLD 21 -1 FP BE Sec !#2 N4947 P1216 BLD 22 -1 FP BE Sec !#A N4946 N4947 !#2 N4948 P1216 BLD 23 -1 FP BE Sec !#2 N4949 P1217 MEMBAR !#2 N4950 P1218 BST 30 0x40800147 FP BE Pri !#2 N4951 P1219 MEMBAR !#2 N4952 P1220 LD 21 -1 FP BE Pri !#2 N4953 P1221 MEMBAR !#2 N4954 P1222 BLD 0 -1 FP BE Pri !#2 N4955 P1222 BLD 1 -1 FP BE Pri !#A N4954 N4955 !#2 N4956 P1222 BLD 2 -1 FP BE Pri !#2 N4957 P1222 BLD 3 -1 FP BE Pri !#2 N4958 P1222 BLD 4 -1 FP BE Pri !#2 N4959 P1223 MEMBAR !#2 N4960 P1224 REPLACEMENT 2 Int BE Sec !#2 N4961 P1225 ST 5 0x1000026 Int BE Sec !#2 N4962 P1226 MEMBAR !#2 N4963 P1227 BLD 16 -1 FP BE Pri !#2 N4964 P1228 MEMBAR !#2 N4965 P1229 REPLACEMENT 24 Int BE Pri !#2 N4966 P1230 REPLACEMENT 29 Int BE Pri !#2 N4967 P1231 PREFETCH 15 Int BE Pri !#2 N4968 P1232 MEMBAR !#2 N4969 P1233 BLD 24 -1 FP BE Pri !#2 N4970 P1233 BLD 25 -1 FP BE Pri !#2 N4971 P1234 MEMBAR !#2 N4972 P1235 REPLACEMENT 7 Int BE Pri !#2 N4973 P1236 REPLACEMENT 26 Int BE Pri !#2 N4974 P1237 ST 10 0x1000027 Int BE Pri !#2 N4975 P1238 MEMBAR !#2 N4976 P1239 BSTC 28 0x40800148 FP BE Pri !#2 N4977 P1240 MEMBAR !#2 N4978 P1241 BLD 21 -1 FP BE Pri !#2 N4979 P1241 BLD 22 -1 FP BE Pri !#A N4978 N4979 !#2 N4980 P1241 BLD 23 -1 FP BE Pri !#2 N4981 P1242 MEMBAR !#2 N4982 P1243 LD 32 -1 Int BE Pri !#2 N4983 P1244 MEMBAR !#2 N4984 P1245 BLD 0 -1 FP BE Pri !#2 N4985 P1245 BLD 1 -1 FP BE Pri !#A N4984 N4985 !#2 N4986 P1245 BLD 2 -1 FP BE Pri !#2 N4987 P1245 BLD 3 -1 FP BE Pri !#2 N4988 P1245 BLD 4 -1 FP BE Pri !#2 N4989 P1246 MEMBAR !#2 N4990 P1247 LD 1 -1 Int BE Pri !#2 N4991 P1248 MEMBAR !#2 N4992 P1249 BLD 0 -1 FP BE Pri !#2 N4993 P1249 BLD 1 -1 FP BE Pri !#A N4992 N4993 !#2 N4994 P1249 BLD 2 -1 FP BE Pri !#2 N4995 P1249 BLD 3 -1 FP BE Pri !#2 N4996 P1249 BLD 4 -1 FP BE Pri !#2 N4997 P1250 MEMBAR !#2 N4998 P1251 ST 33 0x1000028 Int BE Sec !#2 N4999 P1252 LD 29 -1 FP BE Pri !#2 N5000 P1253 ST 17 0x40800149 FP BE Pri !#2 N5001 P1254 PREFETCH 23 Int BE Pri !#2 N5002 P1255 MEMBAR !#2 N5003 P1256 BLD 16 -1 FP BE Pri !#2 N5004 P1257 MEMBAR !#2 N5005 P1258 BLD 29 -1 FP BE Pri !#2 N5006 P1259 MEMBAR !#2 N5007 P1260 REPLACEMENT 9 Int BE Nuc !#2 N5008 P1261 REPLACEMENT 23 Int BE Pri !#2 N5009 P1262 MEMBAR !#2 N5010 P1263 BLD 0 -1 FP BE Pri !#2 N5011 P1263 BLD 1 -1 FP BE Pri !#A N5010 N5011 !#2 N5012 P1263 BLD 2 -1 FP BE Pri !#2 N5013 P1263 BLD 3 -1 FP BE Pri !#2 N5014 P1263 BLD 4 -1 FP BE Pri !#2 N5015 P1264 MEMBAR !#2 N5016 P1265 REPLACEMENT 12 Int BE Pri !#2 N5017 P1266 REPLACEMENT 5 Int BE Sec !#2 N5018 P1267 LD 16 -1 FP BE Pri !#2 N5019 P1268 MEMBAR !#2 N5020 P1269 BSTC 30 0x4080014a FP BE Pri !#2 N5021 P1270 MEMBAR !#2 N5022 P1271 BST 30 0x4080014b FP BE Sec !#2 N5023 P1272 MEMBAR !#2 N5024 P1273 BLD 7 -1 FP BE Pri !#2 N5025 P1274 MEMBAR !#2 N5026 P1275 PREFETCH 6 Int BE Pri !#2 N5027 P1276 MEMBAR !#2 N5028 P1277 BSTC 14 0x4080014c FP BE Pri !#2 N5029 P1278 MEMBAR !#2 N5030 P1279 BST 21 0x4080014d FP BE Pri !#2 N5031 P1279 BST 22 0x4080014e FP BE Pri !#A N5030 N5031 !#2 N5032 P1279 BST 23 0x4080014f FP BE Pri !#2 N5033 P1280 MEMBAR !#2 N5034 P1281 BST 21 0x40800150 FP BE Pri !#2 N5035 P1281 BST 22 0x40800151 FP BE Pri !#A N5034 N5035 !#2 N5036 P1281 BST 23 0x40800152 FP BE Pri !#2 N5037 P1282 MEMBAR !#2 N5038 P1283 REPLACEMENT 27 Int BE Sec !#2 N5039 P1284 ST 21 0x40800153 FP BE Sec !#2 N5040 P1285 MEMBAR !#2 N5041 P1286 BST 33 0x40800154 FP BE Sec !#2 N5042 P1287 MEMBAR !#2 N5043 P1288 BLD 10 -1 FP BE Pri !#2 N5044 P1289 MEMBAR !#2 N5045 P1290 LD 18 -1 Int BE Sec Loop_exit !#2 N5046 P1291 MEMBAR !#3 N5047 P1292 MEMBAR !#3 N5048 P1293 BLD 10 -1 FP BE Pri !#3 N5049 P1294 MEMBAR !#3 N5050 P1295 BSTC 33 0x41000001 FP BE Pri !#3 N5051 P1296 MEMBAR !#3 N5052 P1297 BLD 28 -1 FP BE Sec !#3 N5053 P1298 MEMBAR !#3 N5054 P1299 ST 31 0x1800001 Int BE Pri !#3 N5055 P1300 LD 12 -1 Int BE Pri !#3 N5056 P1301 REPLACEMENT 9 Int BE Nuc !#3 N5057 P1302 MEMBAR !#3 N5058 P1303 BSTC 24 0x41000002 FP BE Pri !#3 N5059 P1303 BSTC 25 0x41000003 FP BE Pri !#3 N5060 P1304 MEMBAR !#3 N5061 P1305 BLD 29 -1 FP BE Pri !#3 N5062 P1306 MEMBAR !#3 N5063 P1307 PREFETCH 15 Int BE Sec !#3 N5064 P1308 PREFETCH 16 Int BE Sec !#3 N5065 P1309 LD 18 -1 Int BE Pri !#3 N5066 P1310 ST 3 0x1800002 Int BE Pri !#3 N5067 P1311 LD 12 -1 Int BE Pri !#3 N5068 P1312 REPLACEMENT 12 Int BE Nuc !#3 N5069 P1313 PREFETCH 6 Int BE Pri !#3 N5070 P1314 MEMBAR !#3 N5071 P1315 BLD 20 -1 FP BE Pri !#3 N5072 P1316 MEMBAR !#3 N5073 P1317 LD 28 -1 Int BE Pri !#3 N5074 P1318 REPLACEMENT 31 Int BE Pri !#3 N5075 P1319 REPLACEMENT 11 Int BE Pri !#3 N5076 P1320 IDC_FLIP 20 Int BE Pri !#3 N5077 P1321 REPLACEMENT 12 Int BE Pri !#3 N5078 P1322 REPLACEMENT 6 Int BE Sec !#3 N5079 P1323 LD 24 -1 FP BE Pri !#3 N5080 P1324 REPLACEMENT 23 Int BE Pri !#3 N5081 P1325 MEMBAR !#3 N5082 P1326 BST 26 0x41000004 FP BE Pri !#3 N5083 P1326 BST 27 0x41000005 FP BE Pri !#3 N5084 P1327 MEMBAR !#3 N5085 P1328 LD 5 -1 Int BE Pri !#3 N5086 P1329 MEMBAR !#3 N5087 P1330 BLD 17 -1 FP BE Pri !#3 N5088 P1331 MEMBAR !#3 N5089 P1332 LD 28 -1 FP BE Nuc !#3 N5090 P1333 MEMBAR !#3 N5091 P1334 BST 17 0x41000006 FP BE Pri !#3 N5092 P1335 MEMBAR !#3 N5093 P1336 IDC_FLIP 28 Int BE Pri !#3 N5094 P1337 PREFETCH 24 Int BE Pri !#3 N5095 P1338 PREFETCH 29 Int BE Sec !#3 N5096 P1339 PREFETCH 33 Int BE Pri !#3 N5097 P1340 MEMBAR !#3 N5098 P1341 BLD 5 -1 FP BE Pri !#3 N5099 P1341 BLD 6 -1 FP BE Pri !#3 N5100 P1342 MEMBAR !#3 N5101 P1343 BSTC 21 0x41000007 FP BE Pri !#3 N5102 P1343 BSTC 22 0x41000008 FP BE Pri !#A N5101 N5102 !#3 N5103 P1343 BSTC 23 0x41000009 FP BE Pri !#3 N5104 P1344 MEMBAR !#3 N5105 P1345 BST 8 0x4100000a FP BE Pri !#3 N5106 P1345 BST 9 0x4100000b FP BE Pri !#3 N5107 P1346 MEMBAR !#3 N5108 P1347 ST 6 0x4100000c FP BE Pri !#3 N5109 P1348 MEMBAR !#3 N5110 P1349 BLD 21 -1 FP BE Pri !#3 N5111 P1349 BLD 22 -1 FP BE Pri !#A N5110 N5111 !#3 N5112 P1349 BLD 23 -1 FP BE Pri !#3 N5113 P1350 MEMBAR !#3 N5114 P1351 BSTC 14 0x4100000d FP BE Sec !#3 N5115 P1352 MEMBAR !#3 N5116 P1353 REPLACEMENT 19 Int BE Nuc !#3 N5117 P1354 REPLACEMENT 0 Int BE Pri !#3 N5118 P1355 MEMBAR !#3 N5119 P1356 BLD 7 -1 FP BE Pri !#3 N5120 P1357 MEMBAR !#3 N5121 P1358 BLD 14 -1 FP BE Pri !#3 N5122 P1359 MEMBAR !#3 N5123 P1360 PREFETCH 11 Int BE Pri !#3 N5124 P1361 PREFETCH 21 Int BE Nuc !#3 N5125 P1362 MEMBAR !#3 N5126 P1363 BLD 29 -1 FP BE Pri !#3 N5127 P1364 MEMBAR !#3 N5128 P1365 REPLACEMENT 11 Int BE Pri !#3 N5129 P1366 LD 8 -1 FP BE Pri !#3 N5130 P1367 PREFETCH 3 Int LE Pri !#3 N5131 P1368 MEMBAR !#3 N5132 P1369 BLD 11 -1 FP BE Pri !#3 N5133 P1369 BLD 12 -1 FP BE Pri !#A N5132 N5133 !#3 N5134 P1369 BLD 13 -1 FP BE Pri !#3 N5135 P1370 MEMBAR !#3 N5136 P1371 PREFETCH 24 Int BE Pri !#3 N5137 P1372 ST 28 0x1800003 Int BE Nuc !#3 N5138 P1373 ST 17 0x4100000e FP BE Pri !#3 N5139 P1374 MEMBAR !#3 N5140 P1375 BLD 21 -1 FP BE Sec !#3 N5141 P1375 BLD 22 -1 FP BE Sec !#A N5140 N5141 !#3 N5142 P1375 BLD 23 -1 FP BE Sec !#3 N5143 P1376 MEMBAR !#3 N5144 P1377 BLD 24 -1 FP BE Pri !#3 N5145 P1377 BLD 25 -1 FP BE Pri !#3 N5146 P1378 MEMBAR !#3 N5147 P1379 BSTC 17 0x4100000f FP BE Pri !#3 N5148 P1380 MEMBAR !#3 N5149 P1381 BST 10 0x41000010 FP BE Sec !#3 N5150 P1382 MEMBAR !#3 N5151 P1383 ST 33 0x41000011 FP BE Pri !#3 N5152 P1384 MEMBAR !#3 N5153 P1385 BLD 19 -1 FP BE Pri !#3 N5154 P1386 MEMBAR !#3 N5155 P1387 BST 0 0x41000012 FP BE Pri !#3 N5156 P1387 BST 1 0x41000013 FP BE Pri !#A N5155 N5156 !#3 N5157 P1387 BST 2 0x41000014 FP BE Pri !#3 N5158 P1387 BST 3 0x41000015 FP BE Pri !#3 N5159 P1387 BST 4 0x41000016 FP BE Pri !#3 N5160 P1388 MEMBAR !#3 N5161 P1389 BSTC 24 0x41000017 FP BE Pri !#3 N5162 P1389 BSTC 25 0x41000018 FP BE Pri !#3 N5163 P1390 MEMBAR !#3 N5164 P1391 BLD 14 -1 FP BE Pri !#3 N5165 P1392 MEMBAR !#3 N5166 P1393 BLD 5 -1 FP BE Pri !#3 N5167 P1393 BLD 6 -1 FP BE Pri !#3 N5168 P1394 MEMBAR !#3 N5169 P1395 BLD 5 -1 FP BE Pri !#3 N5170 P1395 BLD 6 -1 FP BE Pri !#3 N5171 P1396 MEMBAR !#3 N5172 P1397 BLD 21 -1 FP BE Pri !#3 N5173 P1397 BLD 22 -1 FP BE Pri !#A N5172 N5173 !#3 N5174 P1397 BLD 23 -1 FP BE Pri !#3 N5175 P1398 MEMBAR !#3 N5176 P1399 BLD 26 -1 FP BE Pri !#3 N5177 P1399 BLD 27 -1 FP BE Pri !#3 N5178 P1400 MEMBAR !#3 N5179 P1401 ST 31 0x41000019 FP BE Sec !#3 N5180 P1402 MEMBAR !#3 N5181 P1403 BLD 5 -1 FP BE Sec !#3 N5182 P1403 BLD 6 -1 FP BE Sec !#3 N5183 P1404 MEMBAR !#3 N5184 P1405 PREFETCH 19 Int BE Pri !#3 N5185 P1406 LD 7 -1 Int BE Pri !#3 N5186 P1407 MEMBAR !#3 N5187 P1408 BSTC 17 0x4100001a FP BE Pri !#3 N5188 P1409 MEMBAR !#3 N5189 P1410 BLD 10 -1 FP BE Pri !#3 N5190 P1411 MEMBAR !#3 N5191 P1412 BSTC 33 0x4100001b FP BE Pri !#3 N5192 P1413 MEMBAR !#3 N5193 P1414 IDC_FLIP 25 Int BE Pri !#3 N5194 P1415 ST 19 0x4100001c FP BE Pri !#3 N5195 P1416 ST 7 0x1800004 Int BE Pri !#3 N5196 P1417 REPLACEMENT 3 Int BE Pri !#3 N5197 P1418 ST 18 0x4100001d FP BE Pri !#3 N5198 P1419 LD 13 -1 Int BE Pri !#3 N5199 P1420 REPLACEMENT 4 Int BE Pri !#3 N5200 P1421 MEMBAR !#3 N5201 P1422 BLD 21 -1 FP BE Pri !#3 N5202 P1422 BLD 22 -1 FP BE Pri !#A N5201 N5202 !#3 N5203 P1422 BLD 23 -1 FP BE Pri !#3 N5204 P1423 MEMBAR !#3 N5205 P1424 BLD 21 -1 FP BE Pri !#3 N5206 P1424 BLD 22 -1 FP BE Pri !#A N5205 N5206 !#3 N5207 P1424 BLD 23 -1 FP BE Pri !#3 N5208 P1425 MEMBAR !#3 N5209 P1426 BSTC 21 0x4100001e FP BE Sec !#3 N5210 P1426 BSTC 22 0x4100001f FP BE Sec !#A N5209 N5210 !#3 N5211 P1426 BSTC 23 0x41000020 FP BE Sec !#3 N5212 P1427 MEMBAR !#3 N5213 P1428 BSTC 0 0x41000021 FP BE Pri !#3 N5214 P1428 BSTC 1 0x41000022 FP BE Pri !#A N5213 N5214 !#3 N5215 P1428 BSTC 2 0x41000023 FP BE Pri !#3 N5216 P1428 BSTC 3 0x41000024 FP BE Pri !#3 N5217 P1428 BSTC 4 0x41000025 FP BE Pri !#3 N5218 P1429 MEMBAR !#3 N5219 P1430 LD 17 -1 Int BE Pri !#3 N5220 P1431 LD 21 -1 FP BE Pri !#3 N5221 P1432 MEMBAR !#3 N5222 P1433 BLD 0 -1 FP BE Pri !#3 N5223 P1433 BLD 1 -1 FP BE Pri !#A N5222 N5223 !#3 N5224 P1433 BLD 2 -1 FP BE Pri !#3 N5225 P1433 BLD 3 -1 FP BE Pri !#3 N5226 P1433 BLD 4 -1 FP BE Pri !#3 N5227 P1434 MEMBAR !#3 N5228 P1435 PREFETCH 13 Int BE Nuc !#3 N5229 P1436 LD 16 -1 Int BE Sec !#3 N5230 P1437 LD 1 -1 FP BE Sec !#3 N5231 P1438 MEMBAR !#3 N5232 P1439 BSTC 26 0x41000026 FP BE Pri !#3 N5233 P1439 BSTC 27 0x41000027 FP BE Pri !#3 N5234 P1440 MEMBAR !#3 N5235 P1441 PREFETCH 23 Int BE Pri !#3 N5236 P1442 PREFETCH 2 Int BE Pri !#3 N5237 P1443 LD 0 -1 Int BE Pri !#3 N5238 P1444 MEMBAR !#3 N5239 P1445 BSTC 21 0x41000028 FP BE Sec !#3 N5240 P1445 BSTC 22 0x41000029 FP BE Sec !#A N5239 N5240 !#3 N5241 P1445 BSTC 23 0x4100002a FP BE Sec !#3 N5242 P1446 MEMBAR !#3 N5243 P1447 BSTC 21 0x4100002b FP BE Sec !#3 N5244 P1447 BSTC 22 0x4100002c FP BE Sec !#A N5243 N5244 !#3 N5245 P1447 BSTC 23 0x4100002d FP BE Sec !#3 N5246 P1448 MEMBAR !#3 N5247 P1449 BLD 0 -1 FP BE Pri !#3 N5248 P1449 BLD 1 -1 FP BE Pri !#A N5247 N5248 !#3 N5249 P1449 BLD 2 -1 FP BE Pri !#3 N5250 P1449 BLD 3 -1 FP BE Pri !#3 N5251 P1449 BLD 4 -1 FP BE Pri !#3 N5252 P1450 MEMBAR !#3 N5253 P1451 REPLACEMENT 25 Int BE Pri !#3 N5254 P1452 LD 15 -1 Int BE Sec !#3 N5255 P1453 REPLACEMENT 20 Int BE Pri !#3 N5256 P1454 LD 2 -1 Int BE Pri !#3 N5257 P1455 REPLACEMENT 6 Int BE Pri !#3 N5258 P1456 MEMBAR !#3 N5259 P1457 BSTC 24 0x4100002e FP BE Pri !#3 N5260 P1457 BSTC 25 0x4100002f FP BE Pri !#3 N5261 P1458 MEMBAR !#3 N5262 P1459 BSTC 8 0x41000030 FP BE Pri !#3 N5263 P1459 BSTC 9 0x41000031 FP BE Pri !#3 N5264 P1460 MEMBAR !#3 N5265 P1461 REPLACEMENT 18 Int BE Pri !#3 N5266 P1462 MEMBAR !#3 N5267 P1463 BST 19 0x41000032 FP BE Pri !#3 N5268 P1464 MEMBAR !#3 N5269 P1465 BLD 21 -1 FP BE Pri !#3 N5270 P1465 BLD 22 -1 FP BE Pri !#A N5269 N5270 !#3 N5271 P1465 BLD 23 -1 FP BE Pri !#3 N5272 P1466 MEMBAR !#3 N5273 P1467 ST 6 0x1800005 Int BE Pri !#3 N5274 P1468 MEMBAR !#3 N5275 P1469 BLD 18 -1 FP BE Pri !#3 N5276 P1470 MEMBAR !#3 N5277 P1471 REPLACEMENT 28 Int BE Pri !#3 N5278 P1472 ST 18 0x41000033 FP BE Sec !#3 N5279 P1473 MEMBAR !#3 N5280 P1474 BLD 32 -1 FP BE Sec !#3 N5281 P1475 MEMBAR !#3 N5282 P1476 MEMBAR !#3 N5283 P1477 BLD 11 -1 FP BE Pri !#3 N5284 P1477 BLD 12 -1 FP BE Pri !#A N5283 N5284 !#3 N5285 P1477 BLD 13 -1 FP BE Pri !#3 N5286 P1478 MEMBAR !#3 N5287 P1479 BLD 29 -1 FP BE Pri !#3 N5288 P1480 MEMBAR !#3 N5289 P1481 BSTC 10 0x41000034 FP BE Sec !#3 N5290 P1482 MEMBAR !#3 N5291 P1483 REPLACEMENT 9 Int BE Nuc !#3 N5292 P1484 REPLACEMENT 20 Int BE Pri !#3 N5293 P1485 ST 21 0x41000035 FP BE Sec !#3 N5294 P1486 REPLACEMENT 21 Int BE Nuc !#3 N5295 P1487 PREFETCH 8 Int BE Pri !#3 N5296 P1488 REPLACEMENT 25 Int BE Pri !#3 N5297 P1489 REPLACEMENT 24 Int BE Pri !#3 N5298 P1490 PREFETCH 33 Int BE Pri !#3 N5299 P1491 REPLACEMENT 4 Int BE Pri !#3 N5300 P1492 LD 8 -1 Int BE Pri !#3 N5301 P1493 MEMBAR !#3 N5302 P1494 BLD 26 -1 FP BE Pri !#3 N5303 P1494 BLD 27 -1 FP BE Pri !#3 N5304 P1495 MEMBAR !#3 N5305 P1496 ST 15 0x41000036 FP BE Pri !#3 N5306 P1497 REPLACEMENT 14 Int BE Sec !#3 N5307 P1498 MEMBAR !#3 N5308 P1499 BST 11 0x41000037 FP BE Pri !#3 N5309 P1499 BST 12 0x41000038 FP BE Pri !#A N5308 N5309 !#3 N5310 P1499 BST 13 0x41000039 FP BE Pri !#3 N5311 P1500 MEMBAR !#3 N5312 P1501 BLD 11 -1 FP BE Pri !#3 N5313 P1501 BLD 12 -1 FP BE Pri !#A N5312 N5313 !#3 N5314 P1501 BLD 13 -1 FP BE Pri !#3 N5315 P1502 MEMBAR !#3 N5316 P1503 LD 3 -1 FP BE Pri !#3 N5317 P1504 REPLACEMENT 30 Int BE Pri !#3 N5318 P1505 REPLACEMENT 19 Int BE Pri !#3 N5319 P1506 REPLACEMENT 17 Int BE Pri !#3 N5320 P1507 PREFETCH 26 Int BE Sec !#3 N5321 P1508 MEMBAR !#3 N5322 P1509 BST 0 0x4100003a FP BE Pri !#3 N5323 P1509 BST 1 0x4100003b FP BE Pri !#A N5322 N5323 !#3 N5324 P1509 BST 2 0x4100003c FP BE Pri !#3 N5325 P1509 BST 3 0x4100003d FP BE Pri !#3 N5326 P1509 BST 4 0x4100003e FP BE Pri !#3 N5327 P1510 MEMBAR !#3 N5328 P1511 ST 2 0x4100003f FP BE Pri !#3 N5329 P1512 ST 30 0x41000040 FP BE Pri !#3 N5330 P1513 MEMBAR !#3 N5331 P1514 BST 0 0x41000041 FP BE Pri !#3 N5332 P1514 BST 1 0x41000042 FP BE Pri !#A N5331 N5332 !#3 N5333 P1514 BST 2 0x41000043 FP BE Pri !#3 N5334 P1514 BST 3 0x41000044 FP BE Pri !#3 N5335 P1514 BST 4 0x41000045 FP BE Pri !#3 N5336 P1515 MEMBAR !#3 N5337 P1516 BLD 19 -1 FP BE Pri !#3 N5338 P1517 MEMBAR !#3 N5339 P1518 BST 0 0x41000046 FP BE Pri !#3 N5340 P1518 BST 1 0x41000047 FP BE Pri !#A N5339 N5340 !#3 N5341 P1518 BST 2 0x41000048 FP BE Pri !#3 N5342 P1518 BST 3 0x41000049 FP BE Pri !#3 N5343 P1518 BST 4 0x4100004a FP BE Pri !#3 N5344 P1519 MEMBAR !#3 N5345 P1520 ST 14 0x4100004b FP BE Pri !#3 N5346 P1521 PREFETCH 14 Int BE Pri !#3 N5347 P1522 LD 23 -1 FP BE Pri !#3 N5348 P1523 PREFETCH 13 Int BE Nuc !#3 N5349 P1524 REPLACEMENT 22 Int BE Pri !#3 N5350 P1525 MEMBAR !#3 N5351 P1526 BSTC 10 0x4100004c FP BE Pri !#3 N5352 P1527 MEMBAR !#3 N5353 P1528 PREFETCH 24 Int BE Pri !#3 N5354 P1529 MEMBAR !#3 N5355 P1530 BLD 8 -1 FP BE Pri !#3 N5356 P1530 BLD 9 -1 FP BE Pri !#3 N5357 P1531 MEMBAR !#3 N5358 P1532 REPLACEMENT 23 Int BE Pri !#3 N5359 P1533 MEMBAR !#3 N5360 P1534 BSTC 0 0x4100004d FP BE Pri !#3 N5361 P1534 BSTC 1 0x4100004e FP BE Pri !#A N5360 N5361 !#3 N5362 P1534 BSTC 2 0x4100004f FP BE Pri !#3 N5363 P1534 BSTC 3 0x41000050 FP BE Pri !#3 N5364 P1534 BSTC 4 0x41000051 FP BE Pri !#3 N5365 P1535 MEMBAR !#3 N5366 P1536 BLD 5 -1 FP BE Pri !#3 N5367 P1536 BLD 6 -1 FP BE Pri !#3 N5368 P1537 MEMBAR !#3 N5369 P1538 BSTC 0 0x41000052 FP BE Pri !#3 N5370 P1538 BSTC 1 0x41000053 FP BE Pri !#A N5369 N5370 !#3 N5371 P1538 BSTC 2 0x41000054 FP BE Pri !#3 N5372 P1538 BSTC 3 0x41000055 FP BE Pri !#3 N5373 P1538 BSTC 4 0x41000056 FP BE Pri !#3 N5374 P1539 MEMBAR !#3 N5375 P1540 ST 14 0x1800006 Int BE Pri !#3 N5376 P1541 ST 5 0x41000057 FP BE Pri !#3 N5377 P1542 MEMBAR !#3 N5378 P1543 BLD 21 -1 FP BE Pri !#3 N5379 P1543 BLD 22 -1 FP BE Pri !#A N5378 N5379 !#3 N5380 P1543 BLD 23 -1 FP BE Pri !#3 N5381 P1544 MEMBAR !#3 N5382 P1545 IDC_FLIP 20 Int BE Pri !#3 N5383 P1546 MEMBAR !#3 N5384 P1547 BST 21 0x41000058 FP BE Pri !#3 N5385 P1547 BST 22 0x41000059 FP BE Pri !#A N5384 N5385 !#3 N5386 P1547 BST 23 0x4100005a FP BE Pri !#3 N5387 P1548 MEMBAR !#3 N5388 P1549 LD 28 -1 FP BE Pri !#3 N5389 P1550 REPLACEMENT 5 Int BE Sec !#3 N5390 P1551 PREFETCH 14 Int BE Pri !#3 N5391 P1552 MEMBAR !#3 N5392 P1553 BSTC 21 0x4100005b FP BE Pri !#3 N5393 P1553 BSTC 22 0x4100005c FP BE Pri !#A N5392 N5393 !#3 N5394 P1553 BSTC 23 0x4100005d FP BE Pri !#3 N5395 P1554 MEMBAR !#3 N5396 P1555 PREFETCH 27 Int BE Pri !#3 N5397 P1556 MEMBAR !#3 N5398 P1557 BLD 30 -1 FP BE Pri !#3 N5399 P1558 MEMBAR !#3 N5400 P1559 BLD 5 -1 FP BE Pri !#3 N5401 P1559 BLD 6 -1 FP BE Pri !#3 N5402 P1560 MEMBAR !#3 N5403 P1561 REPLACEMENT 9 Int BE Nuc !#3 N5404 P1562 LD 28 -1 FP BE Sec !#3 N5405 P1563 MEMBAR !#3 N5406 P1564 BLD 18 -1 FP BE Pri !#3 N5407 P1565 MEMBAR !#3 N5408 P1566 BLD 16 -1 FP BE Pri !#3 N5409 P1567 MEMBAR !#3 N5410 P1568 LD 13 -1 FP BE Pri !#3 N5411 P1569 MEMBAR !#3 N5412 P1570 BSTC 5 0x4100005e FP BE Pri !#3 N5413 P1570 BSTC 6 0x4100005f FP BE Pri !#3 N5414 P1571 MEMBAR !#3 N5415 P1572 REPLACEMENT 31 Int BE Sec !#3 N5416 P1573 MEMBAR !#3 N5417 P1574 BLD 5 -1 FP BE Pri !#3 N5418 P1574 BLD 6 -1 FP BE Pri !#3 N5419 P1575 MEMBAR !#3 N5420 P1576 PREFETCH 19 Int BE Nuc !#3 N5421 P1577 MEMBAR !#3 N5422 P1578 BST 21 0x41000060 FP BE Pri !#3 N5423 P1578 BST 22 0x41000061 FP BE Pri !#A N5422 N5423 !#3 N5424 P1578 BST 23 0x41000062 FP BE Pri !#3 N5425 P1579 MEMBAR !#3 N5426 P1580 IDC_FLIP 13 Int BE Pri !#3 N5427 P1581 MEMBAR !#3 N5428 P1582 BSTC 16 0x41000063 FP BE Pri !#3 N5429 P1583 MEMBAR !#3 N5430 P1584 ST 13 0x41000064 FP BE Pri !#3 N5431 P1585 MEMBAR !#3 N5432 P1586 BLD 21 -1 FP BE Pri !#3 N5433 P1586 BLD 22 -1 FP BE Pri !#A N5432 N5433 !#3 N5434 P1586 BLD 23 -1 FP BE Pri !#3 N5435 P1587 MEMBAR !#3 N5436 P1588 BSTC 29 0x41000065 FP BE Pri !#3 N5437 P1589 MEMBAR !#3 N5438 P1590 IDC_FLIP 15 Int BE Pri !#3 N5439 P1591 MEMBAR !#3 N5440 P1592 BSTC 33 0x41000066 FP BE Sec !#3 N5441 P1593 MEMBAR !#3 N5442 P1594 BST 24 0x41000067 FP BE Pri !#3 N5443 P1594 BST 25 0x41000068 FP BE Pri !#3 N5444 P1595 MEMBAR !#3 N5445 P1596 LD 30 -1 FP BE Pri !#3 N5446 P1597 LD 26 -1 FP BE Sec !#3 N5447 P1598 ST 1 0x41000069 FP BE Pri !#3 N5448 P1599 LD 31 -1 Int BE Pri !#3 N5449 P1600 MEMBAR !#3 N5450 P1601 BLD 11 -1 FP BE Pri !#3 N5451 P1601 BLD 12 -1 FP BE Pri !#A N5450 N5451 !#3 N5452 P1601 BLD 13 -1 FP BE Pri !#3 N5453 P1602 MEMBAR !#3 N5454 P1603 REPLACEMENT 33 Int BE Nuc !#3 N5455 P1604 PREFETCH 12 Int BE Pri !#3 N5456 P1605 MEMBAR !#3 N5457 P1606 BST 18 0x4100006a FP BE Pri !#3 N5458 P1607 MEMBAR !#3 N5459 P1608 BLD 7 -1 FP BE Pri !#3 N5460 P1609 MEMBAR !#3 N5461 P1610 BSTC 0 0x4100006b FP BE Pri !#3 N5462 P1610 BSTC 1 0x4100006c FP BE Pri !#A N5461 N5462 !#3 N5463 P1610 BSTC 2 0x4100006d FP BE Pri !#3 N5464 P1610 BSTC 3 0x4100006e FP BE Pri !#3 N5465 P1610 BSTC 4 0x4100006f FP BE Pri !#3 N5466 P1611 MEMBAR !#3 N5467 P1612 REPLACEMENT 11 Int BE Sec !#3 N5468 P1613 REPLACEMENT 5 Int BE Pri !#3 N5469 P1614 PREFETCH 4 Int BE Nuc !#3 N5470 P1615 ST 22 0x1800007 Int BE Pri !#3 N5471 P1616 REPLACEMENT 5 Int BE Pri !#3 N5472 P1617 MEMBAR !#3 N5473 P1618 BSTC 5 0x41000070 FP BE Sec !#3 N5474 P1618 BSTC 6 0x41000071 FP BE Sec !#3 N5475 P1619 MEMBAR !#3 N5476 P1620 ST 26 0x41000072 FP BE Pri !#3 N5477 P1621 ST 30 0x1800008 Int BE Pri !#3 N5478 P1622 ST 6 0x1800009 Int BE Pri !#3 N5479 P1623 LD 31 -1 FP BE Pri !#3 N5480 P1624 MEMBAR !#3 N5481 P1625 BST 5 0x41000073 FP BE Pri !#3 N5482 P1625 BST 6 0x41000074 FP BE Pri !#3 N5483 P1626 MEMBAR !#3 N5484 P1627 LD 11 -1 FP BE Sec !#3 N5485 P1628 MEMBAR !#3 N5486 P1629 BSTC 20 0x41000075 FP BE Sec !#3 N5487 P1630 MEMBAR !#3 N5488 P1631 BST 18 0x41000076 FP BE Pri !#3 N5489 P1632 MEMBAR !#3 N5490 P1633 BST 11 0x41000077 FP BE Sec !#3 N5491 P1633 BST 12 0x41000078 FP BE Sec !#A N5490 N5491 !#3 N5492 P1633 BST 13 0x41000079 FP BE Sec !#3 N5493 P1634 MEMBAR !#3 N5494 P1635 BLD 11 -1 FP BE Pri !#3 N5495 P1635 BLD 12 -1 FP BE Pri !#A N5494 N5495 !#3 N5496 P1635 BLD 13 -1 FP BE Pri !#3 N5497 P1636 MEMBAR !#3 N5498 P1637 PREFETCH 29 Int BE Pri !#3 N5499 P1638 MEMBAR !#3 N5500 P1639 BLD 11 -1 FP BE Pri !#3 N5501 P1639 BLD 12 -1 FP BE Pri !#A N5500 N5501 !#3 N5502 P1639 BLD 13 -1 FP BE Pri !#3 N5503 P1640 MEMBAR !#3 N5504 P1641 ST 10 0x180000a Int BE Sec !#3 N5505 P1642 LD 10 -1 Int BE Pri !#3 N5506 P1643 ST 16 0x4100007a FP BE Pri !#3 N5507 P1644 LD 26 -1 Int BE Nuc !#3 N5508 P1645 MEMBAR !#3 N5509 P1646 BLD 29 -1 FP BE Pri !#3 N5510 P1647 MEMBAR !#3 N5511 P1648 ST 24 0x4100007b FP BE Pri !#3 N5512 P1649 ST 9 0x180000b Int BE Pri !#3 N5513 P1650 ST 28 0x4100007c FP BE Pri !#3 N5514 P1651 MEMBAR !#3 N5515 P1652 BSTC 21 0x4100007d FP BE Sec !#3 N5516 P1652 BSTC 22 0x4100007e FP BE Sec !#A N5515 N5516 !#3 N5517 P1652 BSTC 23 0x4100007f FP BE Sec !#3 N5518 P1653 MEMBAR !#3 N5519 P1654 BLD 0 -1 FP BE Sec !#3 N5520 P1654 BLD 1 -1 FP BE Sec !#A N5519 N5520 !#3 N5521 P1654 BLD 2 -1 FP BE Sec !#3 N5522 P1654 BLD 3 -1 FP BE Sec !#3 N5523 P1654 BLD 4 -1 FP BE Sec !#3 N5524 P1655 MEMBAR !#3 N5525 P1656 BSTC 32 0x41000080 FP BE Pri !#3 N5526 P1657 MEMBAR !#3 N5527 P1658 IDC_FLIP 16 Int BE Pri !#3 N5528 P1659 MEMBAR !#3 N5529 P1660 BLD 0 -1 FP BE Sec !#3 N5530 P1660 BLD 1 -1 FP BE Sec !#A N5529 N5530 !#3 N5531 P1660 BLD 2 -1 FP BE Sec !#3 N5532 P1660 BLD 3 -1 FP BE Sec !#3 N5533 P1660 BLD 4 -1 FP BE Sec !#3 N5534 P1661 MEMBAR !#3 N5535 P1662 BLD 21 -1 FP BE Pri !#3 N5536 P1662 BLD 22 -1 FP BE Pri !#A N5535 N5536 !#3 N5537 P1662 BLD 23 -1 FP BE Pri !#3 N5538 P1663 MEMBAR !#3 N5539 P1664 ST 4 0x41000081 FP BE Pri !#3 N5540 P1665 IDC_FLIP 8 Int BE Pri !#3 N5541 P1666 MEMBAR !#3 N5542 P1667 BSTC 29 0x41000082 FP BE Pri !#3 N5543 P1668 MEMBAR !#3 N5544 P1669 BLD 33 -1 FP BE Pri !#3 N5545 P1670 MEMBAR !#3 N5546 P1671 BLD 0 -1 FP BE Pri !#3 N5547 P1671 BLD 1 -1 FP BE Pri !#A N5546 N5547 !#3 N5548 P1671 BLD 2 -1 FP BE Pri !#3 N5549 P1671 BLD 3 -1 FP BE Pri !#3 N5550 P1671 BLD 4 -1 FP BE Pri !#3 N5551 P1672 MEMBAR !#3 N5552 P1673 ST 9 0x41000083 FP BE Pri !#3 N5553 P1674 MEMBAR !#3 N5554 P1675 BSTC 20 0x41000084 FP BE Pri !#3 N5555 P1676 MEMBAR !#3 N5556 P1677 BLD 32 -1 FP BE Pri !#3 N5557 P1678 MEMBAR !#3 N5558 P1679 BSTC 30 0x41000085 FP BE Sec !#3 N5559 P1680 MEMBAR !#3 N5560 P1681 ST 4 0x180000c Int BE Pri !#3 N5561 P1682 MEMBAR !#3 N5562 P1683 BSTC 24 0x41000086 FP BE Pri !#3 N5563 P1683 BSTC 25 0x41000087 FP BE Pri !#3 N5564 P1684 MEMBAR !#3 N5565 P1685 BST 31 0x41000088 FP BE Pri !#3 N5566 P1686 MEMBAR !#3 N5567 P1687 BLD 0 -1 FP BE Pri !#3 N5568 P1687 BLD 1 -1 FP BE Pri !#A N5567 N5568 !#3 N5569 P1687 BLD 2 -1 FP BE Pri !#3 N5570 P1687 BLD 3 -1 FP BE Pri !#3 N5571 P1687 BLD 4 -1 FP BE Pri !#3 N5572 P1688 MEMBAR !#3 N5573 P1689 LD 14 -1 FP BE Sec !#3 N5574 P1690 MEMBAR !#3 N5575 P1691 BST 33 0x41000089 FP BE Sec !#3 N5576 P1692 MEMBAR !#3 N5577 P1693 LD 5 -1 Int BE Pri !#3 N5578 P1694 MEMBAR !#3 N5579 P1695 BST 24 0x4100008a FP BE Pri !#3 N5580 P1695 BST 25 0x4100008b FP BE Pri !#3 N5581 P1696 MEMBAR !#3 N5582 P1697 BSTC 11 0x4100008c FP BE Pri !#3 N5583 P1697 BSTC 12 0x4100008d FP BE Pri !#A N5582 N5583 !#3 N5584 P1697 BSTC 13 0x4100008e FP BE Pri !#3 N5585 P1698 MEMBAR !#3 N5586 P1699 LD 13 -1 FP BE Pri !#3 N5587 P1700 MEMBAR !#3 N5588 P1701 BLD 15 -1 FP BE Pri !#3 N5589 P1702 MEMBAR !#3 N5590 P1703 BSTC 11 0x4100008f FP BE Pri !#3 N5591 P1703 BSTC 12 0x41000090 FP BE Pri !#A N5590 N5591 !#3 N5592 P1703 BSTC 13 0x41000091 FP BE Pri !#3 N5593 P1704 MEMBAR !#3 N5594 P1705 LD 14 -1 FP BE Sec !#3 N5595 P1706 MEMBAR !#3 N5596 P1707 BLD 5 -1 FP BE Pri !#3 N5597 P1707 BLD 6 -1 FP BE Pri !#3 N5598 P1708 MEMBAR !#3 N5599 P1709 BLD 0 -1 FP BE Pri !#3 N5600 P1709 BLD 1 -1 FP BE Pri !#A N5599 N5600 !#3 N5601 P1709 BLD 2 -1 FP BE Pri !#3 N5602 P1709 BLD 3 -1 FP BE Pri !#3 N5603 P1709 BLD 4 -1 FP BE Pri !#3 N5604 P1710 MEMBAR !#3 N5605 P1711 BLD 18 -1 FP BE Pri !#3 N5606 P1712 MEMBAR !#3 N5607 P1713 BLD 26 -1 FP BE Pri !#3 N5608 P1713 BLD 27 -1 FP BE Pri !#3 N5609 P1714 MEMBAR !#3 N5610 P1715 BLD 29 -1 FP BE Pri !#3 N5611 P1716 MEMBAR !#3 N5612 P1717 LD 5 -1 FP BE Pri !#3 N5613 P1718 MEMBAR !#3 N5614 P1719 BST 21 0x41000092 FP BE Sec !#3 N5615 P1719 BST 22 0x41000093 FP BE Sec !#A N5614 N5615 !#3 N5616 P1719 BST 23 0x41000094 FP BE Sec !#3 N5617 P1720 MEMBAR !#3 N5618 P1721 BLD 5 -1 FP BE Sec !#3 N5619 P1721 BLD 6 -1 FP BE Sec !#3 N5620 P1722 MEMBAR !#3 N5621 P1723 REPLACEMENT 20 Int BE Pri !#3 N5622 P1724 MEMBAR !#3 N5623 P1725 BSTC 11 0x41000095 FP BE Pri !#3 N5624 P1725 BSTC 12 0x41000096 FP BE Pri !#A N5623 N5624 !#3 N5625 P1725 BSTC 13 0x41000097 FP BE Pri !#3 N5626 P1726 MEMBAR !#3 N5627 P1727 PREFETCH 22 Int BE Pri !#3 N5628 P1728 LD 7 -1 FP BE Pri !#3 N5629 P1729 MEMBAR !#3 N5630 P1730 BLD 26 -1 FP BE Pri !#3 N5631 P1730 BLD 27 -1 FP BE Pri !#3 N5632 P1731 MEMBAR !#3 N5633 P1732 BSTC 24 0x41000098 FP BE Sec !#3 N5634 P1732 BSTC 25 0x41000099 FP BE Sec !#3 N5635 P1733 MEMBAR !#3 N5636 P1734 BLD 0 -1 FP BE Pri !#3 N5637 P1734 BLD 1 -1 FP BE Pri !#A N5636 N5637 !#3 N5638 P1734 BLD 2 -1 FP BE Pri !#3 N5639 P1734 BLD 3 -1 FP BE Pri !#3 N5640 P1734 BLD 4 -1 FP BE Pri !#3 N5641 P1735 MEMBAR !#3 N5642 P1736 PREFETCH 15 Int BE Pri !#3 N5643 P1737 MEMBAR !#3 N5644 P1738 BST 20 0x4100009a FP BE Sec !#3 N5645 P1739 MEMBAR !#3 N5646 P1740 REPLACEMENT 4 Int BE Pri !#3 N5647 P1741 IDC_FLIP 12 Int BE Pri !#3 N5648 P1742 REPLACEMENT 31 Int BE Pri !#3 N5649 P1743 MEMBAR !#3 N5650 P1744 BST 21 0x4100009b FP BE Pri !#3 N5651 P1744 BST 22 0x4100009c FP BE Pri !#A N5650 N5651 !#3 N5652 P1744 BST 23 0x4100009d FP BE Pri !#3 N5653 P1745 MEMBAR !#3 N5654 P1746 BLD 0 -1 FP BE Pri !#3 N5655 P1746 BLD 1 -1 FP BE Pri !#A N5654 N5655 !#3 N5656 P1746 BLD 2 -1 FP BE Pri !#3 N5657 P1746 BLD 3 -1 FP BE Pri !#3 N5658 P1746 BLD 4 -1 FP BE Pri !#3 N5659 P1747 MEMBAR !#3 N5660 P1748 REPLACEMENT 25 Int BE Pri !#3 N5661 P1749 MEMBAR !#3 N5662 P1750 BLD 29 -1 FP BE Pri !#3 N5663 P1751 MEMBAR !#3 N5664 P1752 REPLACEMENT 14 Int BE Pri !#3 N5665 P1753 ST 3 0x180000d Int BE Pri !#3 N5666 P1754 MEMBAR !#3 N5667 P1755 BST 21 0x4100009e FP BE Pri !#3 N5668 P1755 BST 22 0x4100009f FP BE Pri !#A N5667 N5668 !#3 N5669 P1755 BST 23 0x410000a0 FP BE Pri !#3 N5670 P1756 MEMBAR !#3 N5671 P1757 REPLACEMENT 14 Int BE Nuc !#3 N5672 P1758 MEMBAR !#3 N5673 P1759 BSTC 14 0x410000a1 FP BE Pri !#3 N5674 P1760 MEMBAR !#3 N5675 P1761 BST 32 0x410000a2 FP BE Pri !#3 N5676 P1762 MEMBAR !#3 N5677 P1763 BLD 18 -1 FP BE Sec !#3 N5678 P1764 MEMBAR !#3 N5679 P1765 PREFETCH 9 Int BE Nuc !#3 N5680 P1766 MEMBAR !#3 N5681 P1767 BLD 21 -1 FP BE Pri !#3 N5682 P1767 BLD 22 -1 FP BE Pri !#A N5681 N5682 !#3 N5683 P1767 BLD 23 -1 FP BE Pri !#3 N5684 P1768 MEMBAR !#3 N5685 P1769 LD 12 -1 FP BE Pri !#3 N5686 P1770 REPLACEMENT 1 Int BE Pri !#3 N5687 P1771 MEMBAR !#3 N5688 P1772 BSTC 30 0x410000a3 FP BE Pri !#3 N5689 P1773 MEMBAR !#3 N5690 P1774 LD 9 -1 FP BE Pri !#3 N5691 P1775 MEMBAR !#3 N5692 P1776 BLD 33 -1 FP BE Sec !#3 N5693 P1777 MEMBAR !#3 N5694 P1778 BST 21 0x410000a4 FP BE Pri !#3 N5695 P1778 BST 22 0x410000a5 FP BE Pri !#A N5694 N5695 !#3 N5696 P1778 BST 23 0x410000a6 FP BE Pri !#3 N5697 P1779 MEMBAR !#3 N5698 P1780 PREFETCH 13 Int LE Pri !#3 N5699 P1781 ST 6 0x410000a7 FP BE Pri !#3 N5700 P1782 LD 4 -1 Int BE Pri !#3 N5701 P1783 MEMBAR !#3 N5702 P1784 BLD 0 -1 FP BE Pri !#3 N5703 P1784 BLD 1 -1 FP BE Pri !#A N5702 N5703 !#3 N5704 P1784 BLD 2 -1 FP BE Pri !#3 N5705 P1784 BLD 3 -1 FP BE Pri !#3 N5706 P1784 BLD 4 -1 FP BE Pri !#3 N5707 P1785 MEMBAR !#3 N5708 P1786 BST 8 0x410000a8 FP BE Pri !#3 N5709 P1786 BST 9 0x410000a9 FP BE Pri !#3 N5710 P1787 MEMBAR !#3 N5711 P1788 PREFETCH 15 Int BE Pri !#3 N5712 P1789 MEMBAR !#3 N5713 P1790 BLD 11 -1 FP BE Pri !#3 N5714 P1790 BLD 12 -1 FP BE Pri !#A N5713 N5714 !#3 N5715 P1790 BLD 13 -1 FP BE Pri !#3 N5716 P1791 MEMBAR !#3 N5717 P1792 PREFETCH 10 Int BE Pri !#3 N5718 P1793 MEMBAR !#3 N5719 P1794 BLD 8 -1 FP BE Sec !#3 N5720 P1794 BLD 9 -1 FP BE Sec !#3 N5721 P1795 MEMBAR !#3 N5722 P1796 REPLACEMENT 28 Int BE Pri !#3 N5723 P1797 MEMBAR !#3 N5724 P1798 BSTC 21 0x410000aa FP BE Pri !#3 N5725 P1798 BSTC 22 0x410000ab FP BE Pri !#A N5724 N5725 !#3 N5726 P1798 BSTC 23 0x410000ac FP BE Pri !#3 N5727 P1799 MEMBAR !#3 N5728 P1800 ST 0 0x180000e Int BE Pri !#3 N5729 P1801 MEMBAR !#3 N5730 P1802 BLD 11 -1 FP BE Pri !#3 N5731 P1802 BLD 12 -1 FP BE Pri !#A N5730 N5731 !#3 N5732 P1802 BLD 13 -1 FP BE Pri !#3 N5733 P1803 MEMBAR !#3 N5734 P1804 PREFETCH 16 Int BE Pri !#3 N5735 P1805 REPLACEMENT 15 Int BE Pri !#3 N5736 P1806 LD 8 -1 Int BE Pri !#3 N5737 P1807 PREFETCH 6 Int BE Pri !#3 N5738 P1808 MEMBAR !#3 N5739 P1809 BLD 17 -1 FP BE Pri !#3 N5740 P1810 MEMBAR !#3 N5741 P1811 BLD 26 -1 FP BE Pri !#3 N5742 P1811 BLD 27 -1 FP BE Pri !#3 N5743 P1812 MEMBAR !#3 N5744 P1813 ST 10 0x180000f Int BE Pri !#3 N5745 P1814 REPLACEMENT 30 Int BE Nuc !#3 N5746 P1815 PREFETCH 17 Int BE Pri !#3 N5747 P1816 MEMBAR !#3 N5748 P1817 BST 8 0x410000ad FP BE Pri !#3 N5749 P1817 BST 9 0x410000ae FP BE Pri !#3 N5750 P1818 MEMBAR !#3 N5751 P1819 PREFETCH 12 Int BE Sec !#3 N5752 P1820 REPLACEMENT 26 Int BE Sec !#3 N5753 P1821 LD 7 -1 Int BE Pri !#3 N5754 P1822 PREFETCH 8 Int BE Pri !#3 N5755 P1823 ST 14 0x1800010 Int LE Pri !#3 N5756 P1824 LD 25 -1 Int BE Nuc !#3 N5757 P1825 LD 0 -1 FP BE Pri !#3 N5758 P1826 REPLACEMENT 5 Int BE Pri !#3 N5759 P1827 REPLACEMENT 25 Int BE Nuc !#3 N5760 P1828 MEMBAR !#3 N5761 P1829 BLD 31 -1 FP BE Pri !#3 N5762 P1830 MEMBAR !#3 N5763 P1831 BLD 24 -1 FP BE Pri !#3 N5764 P1831 BLD 25 -1 FP BE Pri !#3 N5765 P1832 MEMBAR !#3 N5766 P1833 ST 27 0x410000af FP BE Pri !#3 N5767 P1834 REPLACEMENT 9 Int BE Pri !#3 N5768 P1835 FLUSHI 24 Int BE Pri !#3 N5769 P1836 MEMBAR !#3 N5770 P1837 BLD 26 -1 FP BE Pri !#3 N5771 P1837 BLD 27 -1 FP BE Pri !#3 N5772 P1838 MEMBAR !#3 N5773 P1839 BST 11 0x410000b0 FP BE Pri !#3 N5774 P1839 BST 12 0x410000b1 FP BE Pri !#A N5773 N5774 !#3 N5775 P1839 BST 13 0x410000b2 FP BE Pri !#3 N5776 P1840 MEMBAR !#3 N5777 P1841 BSTC 30 0x410000b3 FP BE Pri !#3 N5778 P1842 MEMBAR !#3 N5779 P1843 LD 23 -1 Int BE Sec !#3 N5780 P1844 REPLACEMENT 9 Int BE Sec !#3 N5781 P1845 REPLACEMENT 33 Int BE Pri !#3 N5782 P1846 MEMBAR !#3 N5783 P1847 BLD 11 -1 FP BE Pri !#3 N5784 P1847 BLD 12 -1 FP BE Pri !#A N5783 N5784 !#3 N5785 P1847 BLD 13 -1 FP BE Pri !#3 N5786 P1848 MEMBAR !#3 N5787 P1849 BST 0 0x410000b4 FP BE Pri !#3 N5788 P1849 BST 1 0x410000b5 FP BE Pri !#A N5787 N5788 !#3 N5789 P1849 BST 2 0x410000b6 FP BE Pri !#3 N5790 P1849 BST 3 0x410000b7 FP BE Pri !#3 N5791 P1849 BST 4 0x410000b8 FP BE Pri !#3 N5792 P1850 MEMBAR !#3 N5793 P1851 BSTC 15 0x410000b9 FP BE Pri !#3 N5794 P1852 MEMBAR !#3 N5795 P1853 BST 0 0x410000ba FP BE Pri !#3 N5796 P1853 BST 1 0x410000bb FP BE Pri !#A N5795 N5796 !#3 N5797 P1853 BST 2 0x410000bc FP BE Pri !#3 N5798 P1853 BST 3 0x410000bd FP BE Pri !#3 N5799 P1853 BST 4 0x410000be FP BE Pri !#3 N5800 P1854 MEMBAR !#3 N5801 P1855 REPLACEMENT 7 Int BE Pri !#3 N5802 P1856 REPLACEMENT 10 Int BE Sec !#3 N5803 P1857 REPLACEMENT 9 Int BE Pri !#3 N5804 P1858 REPLACEMENT 32 Int BE Nuc !#3 N5805 P1859 REPLACEMENT 8 Int BE Pri !#3 N5806 P1860 MEMBAR !#3 N5807 P1861 BSTC 28 0x410000bf FP BE Sec !#3 N5808 P1862 MEMBAR !#3 N5809 P1863 BLD 21 -1 FP BE Sec !#3 N5810 P1863 BLD 22 -1 FP BE Sec !#A N5809 N5810 !#3 N5811 P1863 BLD 23 -1 FP BE Sec !#3 N5812 P1864 MEMBAR !#3 N5813 P1865 BLD 8 -1 FP BE Pri !#3 N5814 P1865 BLD 9 -1 FP BE Pri !#3 N5815 P1866 MEMBAR !#3 N5816 P1867 BLD 0 -1 FP BE Sec !#3 N5817 P1867 BLD 1 -1 FP BE Sec !#A N5816 N5817 !#3 N5818 P1867 BLD 2 -1 FP BE Sec !#3 N5819 P1867 BLD 3 -1 FP BE Sec !#3 N5820 P1867 BLD 4 -1 FP BE Sec !#3 N5821 P1868 MEMBAR !#3 N5822 P1869 BLD 18 -1 FP BE Pri !#3 N5823 P1870 MEMBAR !#3 N5824 P1871 BSTC 20 0x410000c0 FP BE Pri !#3 N5825 P1872 MEMBAR !#3 N5826 P1873 BLD 18 -1 FP BE Pri !#3 N5827 P1874 MEMBAR !#3 N5828 P1875 ST 9 0x1800011 Int BE Pri !#3 N5829 P1876 MEMBAR !#3 N5830 P1877 BLD 5 -1 FP BE Pri !#3 N5831 P1877 BLD 6 -1 FP BE Pri !#3 N5832 P1878 MEMBAR !#3 N5833 P1879 LD 9 -1 Int BE Pri !#3 N5834 P1880 MEMBAR !#3 N5835 P1881 BSTC 21 0x410000c1 FP BE Sec !#3 N5836 P1881 BSTC 22 0x410000c2 FP BE Sec !#A N5835 N5836 !#3 N5837 P1881 BSTC 23 0x410000c3 FP BE Sec !#3 N5838 P1882 MEMBAR !#3 N5839 P1883 BSTC 28 0x410000c4 FP BE Pri !#3 N5840 P1884 MEMBAR !#3 N5841 P1885 BLD 14 -1 FP BE Pri !#3 N5842 P1886 MEMBAR !#3 N5843 P1887 LD 25 -1 FP BE Sec !#3 N5844 P1888 PREFETCH 25 Int BE Pri !#3 N5845 P1889 MEMBAR !#3 N5846 P1890 BSTC 11 0x410000c5 FP BE Sec !#3 N5847 P1890 BSTC 12 0x410000c6 FP BE Sec !#A N5846 N5847 !#3 N5848 P1890 BSTC 13 0x410000c7 FP BE Sec !#3 N5849 P1891 MEMBAR !#3 N5850 P1892 PREFETCH 32 Int BE Nuc !#3 N5851 P1893 ST 7 0x1800012 Int BE Pri !#3 N5852 P1894 REPLACEMENT 32 Int BE Pri !#3 N5853 P1895 ST 1 0x1800013 Int BE Pri !#3 N5854 P1896 ST 10 0x410000c8 FP BE Sec !#3 N5855 P1897 PREFETCH 3 Int BE Pri !#3 N5856 P1898 REPLACEMENT 31 Int BE Pri !#3 N5857 P1899 MEMBAR !#3 N5858 P1900 BST 21 0x410000c9 FP BE Pri !#3 N5859 P1900 BST 22 0x410000ca FP BE Pri !#A N5858 N5859 !#3 N5860 P1900 BST 23 0x410000cb FP BE Pri !#3 N5861 P1901 MEMBAR !#3 N5862 P1902 BLD 5 -1 FP BE Pri !#3 N5863 P1902 BLD 6 -1 FP BE Pri !#3 N5864 P1903 MEMBAR !#3 N5865 P1904 PREFETCH 5 Int BE Pri !#3 N5866 P1905 PREFETCH 10 Int BE Pri !#3 N5867 P1906 REPLACEMENT 5 Int BE Pri !#3 N5868 P1907 MEMBAR !#3 N5869 P1908 BLD 21 -1 FP BE Pri !#3 N5870 P1908 BLD 22 -1 FP BE Pri !#A N5869 N5870 !#3 N5871 P1908 BLD 23 -1 FP BE Pri !#3 N5872 P1909 MEMBAR !#3 N5873 P1910 BLD 24 -1 FP BE Pri !#3 N5874 P1910 BLD 25 -1 FP BE Pri !#3 N5875 P1911 MEMBAR !#3 N5876 P1912 LD 23 -1 FP BE Pri !#3 N5877 P1913 MEMBAR !#3 N5878 P1914 BLD 10 -1 FP BE Pri !#3 N5879 P1915 MEMBAR !#3 N5880 P1916 BST 14 0x410000cc FP BE Pri !#3 N5881 P1917 MEMBAR !#3 N5882 P1918 BLD 32 -1 FP BE Pri !#3 N5883 P1919 MEMBAR !#3 N5884 P1920 PREFETCH 27 Int BE Pri !#3 N5885 P1921 MEMBAR !#3 N5886 P1922 BLD 0 -1 FP BE Pri !#3 N5887 P1922 BLD 1 -1 FP BE Pri !#A N5886 N5887 !#3 N5888 P1922 BLD 2 -1 FP BE Pri !#3 N5889 P1922 BLD 3 -1 FP BE Pri !#3 N5890 P1922 BLD 4 -1 FP BE Pri !#3 N5891 P1923 MEMBAR !#3 N5892 P1924 BSTC 5 0x410000cd FP BE Sec !#3 N5893 P1924 BSTC 6 0x410000ce FP BE Sec !#3 N5894 P1925 MEMBAR !#3 N5895 P1926 BLD 8 -1 FP BE Pri !#3 N5896 P1926 BLD 9 -1 FP BE Pri !#3 N5897 P1927 MEMBAR !#3 N5898 P1928 LD 25 -1 Int BE Pri !#3 N5899 P1929 MEMBAR !#3 N5900 P1930 BLD 10 -1 FP BE Pri !#3 N5901 P1931 MEMBAR !#3 N5902 P1932 ST 33 0x1800014 Int BE Sec !#3 N5903 P1933 PREFETCH 30 Int BE Pri !#3 N5904 P1934 MEMBAR !#3 N5905 P1935 BST 32 0x410000cf FP BE Pri !#3 N5906 P1936 MEMBAR !#3 N5907 P1937 LD 3 -1 Int BE Nuc !#3 N5908 P1938 MEMBAR !#3 N5909 P1939 BLD 33 -1 FP BE Pri !#3 N5910 P1940 MEMBAR !#3 N5911 P1941 LD 14 -1 Int BE Pri Loop_exit !#3 N5912 P1292 MEMBAR !#3 N5913 P1293 BLD 10 -1 FP BE Pri !#3 N5914 P1294 MEMBAR !#3 N5915 P1295 BSTC 33 0x410000d0 FP BE Pri !#3 N5916 P1296 MEMBAR !#3 N5917 P1297 BLD 28 -1 FP BE Sec !#3 N5918 P1298 MEMBAR !#3 N5919 P1299 ST 31 0x1800015 Int BE Pri !#3 N5920 P1300 LD 12 -1 Int BE Pri !#3 N5921 P1301 REPLACEMENT 9 Int BE Nuc !#3 N5922 P1302 MEMBAR !#3 N5923 P1303 BSTC 24 0x410000d1 FP BE Pri !#3 N5924 P1303 BSTC 25 0x410000d2 FP BE Pri !#3 N5925 P1304 MEMBAR !#3 N5926 P1305 BLD 29 -1 FP BE Pri !#3 N5927 P1306 MEMBAR !#3 N5928 P1307 PREFETCH 15 Int BE Sec !#3 N5929 P1308 PREFETCH 16 Int BE Sec !#3 N5930 P1309 LD 18 -1 Int BE Pri !#3 N5931 P1310 ST 3 0x1800016 Int BE Pri !#3 N5932 P1311 LD 12 -1 Int BE Pri !#3 N5933 P1312 REPLACEMENT 12 Int BE Nuc !#3 N5934 P1313 PREFETCH 6 Int BE Pri !#3 N5935 P1314 MEMBAR !#3 N5936 P1315 BLD 20 -1 FP BE Pri !#3 N5937 P1316 MEMBAR !#3 N5938 P1317 LD 28 -1 Int BE Pri !#3 N5939 P1318 REPLACEMENT 31 Int BE Pri !#3 N5940 P1319 REPLACEMENT 11 Int BE Pri !#3 N5941 P1320 IDC_FLIP 20 Int BE Pri !#3 N5942 P1321 REPLACEMENT 12 Int BE Pri !#3 N5943 P1322 REPLACEMENT 6 Int BE Sec !#3 N5944 P1323 LD 24 -1 FP BE Pri !#3 N5945 P1324 REPLACEMENT 23 Int BE Pri !#3 N5946 P1325 MEMBAR !#3 N5947 P1326 BST 26 0x410000d3 FP BE Pri !#3 N5948 P1326 BST 27 0x410000d4 FP BE Pri !#3 N5949 P1327 MEMBAR !#3 N5950 P1328 LD 5 -1 Int BE Pri !#3 N5951 P1329 MEMBAR !#3 N5952 P1330 BLD 17 -1 FP BE Pri !#3 N5953 P1331 MEMBAR !#3 N5954 P1332 LD 28 -1 FP BE Nuc !#3 N5955 P1333 MEMBAR !#3 N5956 P1334 BST 17 0x410000d5 FP BE Pri !#3 N5957 P1335 MEMBAR !#3 N5958 P1336 IDC_FLIP 28 Int BE Pri !#3 N5959 P1337 PREFETCH 24 Int BE Pri !#3 N5960 P1338 PREFETCH 29 Int BE Sec !#3 N5961 P1339 PREFETCH 33 Int BE Pri !#3 N5962 P1340 MEMBAR !#3 N5963 P1341 BLD 5 -1 FP BE Pri !#3 N5964 P1341 BLD 6 -1 FP BE Pri !#3 N5965 P1342 MEMBAR !#3 N5966 P1343 BSTC 21 0x410000d6 FP BE Pri !#3 N5967 P1343 BSTC 22 0x410000d7 FP BE Pri !#A N5966 N5967 !#3 N5968 P1343 BSTC 23 0x410000d8 FP BE Pri !#3 N5969 P1344 MEMBAR !#3 N5970 P1345 BST 8 0x410000d9 FP BE Pri !#3 N5971 P1345 BST 9 0x410000da FP BE Pri !#3 N5972 P1346 MEMBAR !#3 N5973 P1347 ST 6 0x410000db FP BE Pri !#3 N5974 P1348 MEMBAR !#3 N5975 P1349 BLD 21 -1 FP BE Pri !#3 N5976 P1349 BLD 22 -1 FP BE Pri !#A N5975 N5976 !#3 N5977 P1349 BLD 23 -1 FP BE Pri !#3 N5978 P1350 MEMBAR !#3 N5979 P1351 BSTC 14 0x410000dc FP BE Sec !#3 N5980 P1352 MEMBAR !#3 N5981 P1353 REPLACEMENT 19 Int BE Nuc !#3 N5982 P1354 REPLACEMENT 0 Int BE Pri !#3 N5983 P1355 MEMBAR !#3 N5984 P1356 BLD 7 -1 FP BE Pri !#3 N5985 P1357 MEMBAR !#3 N5986 P1358 BLD 14 -1 FP BE Pri !#3 N5987 P1359 MEMBAR !#3 N5988 P1360 PREFETCH 11 Int BE Pri !#3 N5989 P1361 PREFETCH 21 Int BE Nuc !#3 N5990 P1362 MEMBAR !#3 N5991 P1363 BLD 29 -1 FP BE Pri !#3 N5992 P1364 MEMBAR !#3 N5993 P1365 REPLACEMENT 11 Int BE Pri !#3 N5994 P1366 LD 8 -1 FP BE Pri !#3 N5995 P1367 PREFETCH 3 Int LE Pri !#3 N5996 P1368 MEMBAR !#3 N5997 P1369 BLD 11 -1 FP BE Pri !#3 N5998 P1369 BLD 12 -1 FP BE Pri !#A N5997 N5998 !#3 N5999 P1369 BLD 13 -1 FP BE Pri !#3 N6000 P1370 MEMBAR !#3 N6001 P1371 PREFETCH 24 Int BE Pri !#3 N6002 P1372 ST 28 0x1800017 Int BE Nuc !#3 N6003 P1373 ST 17 0x410000dd FP BE Pri !#3 N6004 P1374 MEMBAR !#3 N6005 P1375 BLD 21 -1 FP BE Sec !#3 N6006 P1375 BLD 22 -1 FP BE Sec !#A N6005 N6006 !#3 N6007 P1375 BLD 23 -1 FP BE Sec !#3 N6008 P1376 MEMBAR !#3 N6009 P1377 BLD 24 -1 FP BE Pri !#3 N6010 P1377 BLD 25 -1 FP BE Pri !#3 N6011 P1378 MEMBAR !#3 N6012 P1379 BSTC 17 0x410000de FP BE Pri !#3 N6013 P1380 MEMBAR !#3 N6014 P1381 BST 10 0x410000df FP BE Sec !#3 N6015 P1382 MEMBAR !#3 N6016 P1383 ST 33 0x410000e0 FP BE Pri !#3 N6017 P1384 MEMBAR !#3 N6018 P1385 BLD 19 -1 FP BE Pri !#3 N6019 P1386 MEMBAR !#3 N6020 P1387 BST 0 0x410000e1 FP BE Pri !#3 N6021 P1387 BST 1 0x410000e2 FP BE Pri !#A N6020 N6021 !#3 N6022 P1387 BST 2 0x410000e3 FP BE Pri !#3 N6023 P1387 BST 3 0x410000e4 FP BE Pri !#3 N6024 P1387 BST 4 0x410000e5 FP BE Pri !#3 N6025 P1388 MEMBAR !#3 N6026 P1389 BSTC 24 0x410000e6 FP BE Pri !#3 N6027 P1389 BSTC 25 0x410000e7 FP BE Pri !#3 N6028 P1390 MEMBAR !#3 N6029 P1391 BLD 14 -1 FP BE Pri !#3 N6030 P1392 MEMBAR !#3 N6031 P1393 BLD 5 -1 FP BE Pri !#3 N6032 P1393 BLD 6 -1 FP BE Pri !#3 N6033 P1394 MEMBAR !#3 N6034 P1395 BLD 5 -1 FP BE Pri !#3 N6035 P1395 BLD 6 -1 FP BE Pri !#3 N6036 P1396 MEMBAR !#3 N6037 P1397 BLD 21 -1 FP BE Pri !#3 N6038 P1397 BLD 22 -1 FP BE Pri !#A N6037 N6038 !#3 N6039 P1397 BLD 23 -1 FP BE Pri !#3 N6040 P1398 MEMBAR !#3 N6041 P1399 BLD 26 -1 FP BE Pri !#3 N6042 P1399 BLD 27 -1 FP BE Pri !#3 N6043 P1400 MEMBAR !#3 N6044 P1401 ST 31 0x410000e8 FP BE Sec !#3 N6045 P1402 MEMBAR !#3 N6046 P1403 BLD 5 -1 FP BE Sec !#3 N6047 P1403 BLD 6 -1 FP BE Sec !#3 N6048 P1404 MEMBAR !#3 N6049 P1405 PREFETCH 19 Int BE Pri !#3 N6050 P1406 LD 7 -1 Int BE Pri !#3 N6051 P1407 MEMBAR !#3 N6052 P1408 BSTC 17 0x410000e9 FP BE Pri !#3 N6053 P1409 MEMBAR !#3 N6054 P1410 BLD 10 -1 FP BE Pri !#3 N6055 P1411 MEMBAR !#3 N6056 P1412 BSTC 33 0x410000ea FP BE Pri !#3 N6057 P1413 MEMBAR !#3 N6058 P1414 IDC_FLIP 25 Int BE Pri !#3 N6059 P1415 ST 19 0x410000eb FP BE Pri !#3 N6060 P1416 ST 7 0x1800018 Int BE Pri !#3 N6061 P1417 REPLACEMENT 3 Int BE Pri !#3 N6062 P1418 ST 18 0x410000ec FP BE Pri !#3 N6063 P1419 LD 13 -1 Int BE Pri !#3 N6064 P1420 REPLACEMENT 4 Int BE Pri !#3 N6065 P1421 MEMBAR !#3 N6066 P1422 BLD 21 -1 FP BE Pri !#3 N6067 P1422 BLD 22 -1 FP BE Pri !#A N6066 N6067 !#3 N6068 P1422 BLD 23 -1 FP BE Pri !#3 N6069 P1423 MEMBAR !#3 N6070 P1424 BLD 21 -1 FP BE Pri !#3 N6071 P1424 BLD 22 -1 FP BE Pri !#A N6070 N6071 !#3 N6072 P1424 BLD 23 -1 FP BE Pri !#3 N6073 P1425 MEMBAR !#3 N6074 P1426 BSTC 21 0x410000ed FP BE Sec !#3 N6075 P1426 BSTC 22 0x410000ee FP BE Sec !#A N6074 N6075 !#3 N6076 P1426 BSTC 23 0x410000ef FP BE Sec !#3 N6077 P1427 MEMBAR !#3 N6078 P1428 BSTC 0 0x410000f0 FP BE Pri !#3 N6079 P1428 BSTC 1 0x410000f1 FP BE Pri !#A N6078 N6079 !#3 N6080 P1428 BSTC 2 0x410000f2 FP BE Pri !#3 N6081 P1428 BSTC 3 0x410000f3 FP BE Pri !#3 N6082 P1428 BSTC 4 0x410000f4 FP BE Pri !#3 N6083 P1429 MEMBAR !#3 N6084 P1430 LD 17 -1 Int BE Pri !#3 N6085 P1431 LD 21 -1 FP BE Pri !#3 N6086 P1432 MEMBAR !#3 N6087 P1433 BLD 0 -1 FP BE Pri !#3 N6088 P1433 BLD 1 -1 FP BE Pri !#A N6087 N6088 !#3 N6089 P1433 BLD 2 -1 FP BE Pri !#3 N6090 P1433 BLD 3 -1 FP BE Pri !#3 N6091 P1433 BLD 4 -1 FP BE Pri !#3 N6092 P1434 MEMBAR !#3 N6093 P1435 PREFETCH 13 Int BE Nuc !#3 N6094 P1436 LD 16 -1 Int BE Sec !#3 N6095 P1437 LD 1 -1 FP BE Sec !#3 N6096 P1438 MEMBAR !#3 N6097 P1439 BSTC 26 0x410000f5 FP BE Pri !#3 N6098 P1439 BSTC 27 0x410000f6 FP BE Pri !#3 N6099 P1440 MEMBAR !#3 N6100 P1441 PREFETCH 23 Int BE Pri !#3 N6101 P1442 PREFETCH 2 Int BE Pri !#3 N6102 P1443 LD 0 -1 Int BE Pri !#3 N6103 P1444 MEMBAR !#3 N6104 P1445 BSTC 21 0x410000f7 FP BE Sec !#3 N6105 P1445 BSTC 22 0x410000f8 FP BE Sec !#A N6104 N6105 !#3 N6106 P1445 BSTC 23 0x410000f9 FP BE Sec !#3 N6107 P1446 MEMBAR !#3 N6108 P1447 BSTC 21 0x410000fa FP BE Sec !#3 N6109 P1447 BSTC 22 0x410000fb FP BE Sec !#A N6108 N6109 !#3 N6110 P1447 BSTC 23 0x410000fc FP BE Sec !#3 N6111 P1448 MEMBAR !#3 N6112 P1449 BLD 0 -1 FP BE Pri !#3 N6113 P1449 BLD 1 -1 FP BE Pri !#A N6112 N6113 !#3 N6114 P1449 BLD 2 -1 FP BE Pri !#3 N6115 P1449 BLD 3 -1 FP BE Pri !#3 N6116 P1449 BLD 4 -1 FP BE Pri !#3 N6117 P1450 MEMBAR !#3 N6118 P1451 REPLACEMENT 25 Int BE Pri !#3 N6119 P1452 LD 15 -1 Int BE Sec !#3 N6120 P1453 REPLACEMENT 20 Int BE Pri !#3 N6121 P1454 LD 2 -1 Int BE Pri !#3 N6122 P1455 REPLACEMENT 6 Int BE Pri !#3 N6123 P1456 MEMBAR !#3 N6124 P1457 BSTC 24 0x410000fd FP BE Pri !#3 N6125 P1457 BSTC 25 0x410000fe FP BE Pri !#3 N6126 P1458 MEMBAR !#3 N6127 P1459 BSTC 8 0x410000ff FP BE Pri !#3 N6128 P1459 BSTC 9 0x41000100 FP BE Pri !#3 N6129 P1460 MEMBAR !#3 N6130 P1461 REPLACEMENT 18 Int BE Pri !#3 N6131 P1462 MEMBAR !#3 N6132 P1463 BST 19 0x41000101 FP BE Pri !#3 N6133 P1464 MEMBAR !#3 N6134 P1465 BLD 21 -1 FP BE Pri !#3 N6135 P1465 BLD 22 -1 FP BE Pri !#A N6134 N6135 !#3 N6136 P1465 BLD 23 -1 FP BE Pri !#3 N6137 P1466 MEMBAR !#3 N6138 P1467 ST 6 0x1800019 Int BE Pri !#3 N6139 P1468 MEMBAR !#3 N6140 P1469 BLD 18 -1 FP BE Pri !#3 N6141 P1470 MEMBAR !#3 N6142 P1471 REPLACEMENT 28 Int BE Pri !#3 N6143 P1472 ST 18 0x41000102 FP BE Sec !#3 N6144 P1473 MEMBAR !#3 N6145 P1474 BLD 32 -1 FP BE Sec !#3 N6146 P1475 MEMBAR !#3 N6147 P1476 MEMBAR !#3 N6148 P1477 BLD 11 -1 FP BE Pri !#3 N6149 P1477 BLD 12 -1 FP BE Pri !#A N6148 N6149 !#3 N6150 P1477 BLD 13 -1 FP BE Pri !#3 N6151 P1478 MEMBAR !#3 N6152 P1479 BLD 29 -1 FP BE Pri !#3 N6153 P1480 MEMBAR !#3 N6154 P1481 BSTC 10 0x41000103 FP BE Sec !#3 N6155 P1482 MEMBAR !#3 N6156 P1483 REPLACEMENT 9 Int BE Nuc !#3 N6157 P1484 REPLACEMENT 20 Int BE Pri !#3 N6158 P1485 ST 21 0x41000104 FP BE Sec !#3 N6159 P1486 REPLACEMENT 21 Int BE Nuc !#3 N6160 P1487 PREFETCH 8 Int BE Pri !#3 N6161 P1488 REPLACEMENT 25 Int BE Pri !#3 N6162 P1489 REPLACEMENT 24 Int BE Pri !#3 N6163 P1490 PREFETCH 33 Int BE Pri !#3 N6164 P1491 REPLACEMENT 4 Int BE Pri !#3 N6165 P1492 LD 8 -1 Int BE Pri !#3 N6166 P1493 MEMBAR !#3 N6167 P1494 BLD 26 -1 FP BE Pri !#3 N6168 P1494 BLD 27 -1 FP BE Pri !#3 N6169 P1495 MEMBAR !#3 N6170 P1496 ST 15 0x41000105 FP BE Pri !#3 N6171 P1497 REPLACEMENT 14 Int BE Sec !#3 N6172 P1498 MEMBAR !#3 N6173 P1499 BST 11 0x41000106 FP BE Pri !#3 N6174 P1499 BST 12 0x41000107 FP BE Pri !#A N6173 N6174 !#3 N6175 P1499 BST 13 0x41000108 FP BE Pri !#3 N6176 P1500 MEMBAR !#3 N6177 P1501 BLD 11 -1 FP BE Pri !#3 N6178 P1501 BLD 12 -1 FP BE Pri !#A N6177 N6178 !#3 N6179 P1501 BLD 13 -1 FP BE Pri !#3 N6180 P1502 MEMBAR !#3 N6181 P1503 LD 3 -1 FP BE Pri !#3 N6182 P1504 REPLACEMENT 30 Int BE Pri !#3 N6183 P1505 REPLACEMENT 19 Int BE Pri !#3 N6184 P1506 REPLACEMENT 17 Int BE Pri !#3 N6185 P1507 PREFETCH 26 Int BE Sec !#3 N6186 P1508 MEMBAR !#3 N6187 P1509 BST 0 0x41000109 FP BE Pri !#3 N6188 P1509 BST 1 0x4100010a FP BE Pri !#A N6187 N6188 !#3 N6189 P1509 BST 2 0x4100010b FP BE Pri !#3 N6190 P1509 BST 3 0x4100010c FP BE Pri !#3 N6191 P1509 BST 4 0x4100010d FP BE Pri !#3 N6192 P1510 MEMBAR !#3 N6193 P1511 ST 2 0x4100010e FP BE Pri !#3 N6194 P1512 ST 30 0x4100010f FP BE Pri !#3 N6195 P1513 MEMBAR !#3 N6196 P1514 BST 0 0x41000110 FP BE Pri !#3 N6197 P1514 BST 1 0x41000111 FP BE Pri !#A N6196 N6197 !#3 N6198 P1514 BST 2 0x41000112 FP BE Pri !#3 N6199 P1514 BST 3 0x41000113 FP BE Pri !#3 N6200 P1514 BST 4 0x41000114 FP BE Pri !#3 N6201 P1515 MEMBAR !#3 N6202 P1516 BLD 19 -1 FP BE Pri !#3 N6203 P1517 MEMBAR !#3 N6204 P1518 BST 0 0x41000115 FP BE Pri !#3 N6205 P1518 BST 1 0x41000116 FP BE Pri !#A N6204 N6205 !#3 N6206 P1518 BST 2 0x41000117 FP BE Pri !#3 N6207 P1518 BST 3 0x41000118 FP BE Pri !#3 N6208 P1518 BST 4 0x41000119 FP BE Pri !#3 N6209 P1519 MEMBAR !#3 N6210 P1520 ST 14 0x4100011a FP BE Pri !#3 N6211 P1521 PREFETCH 14 Int BE Pri !#3 N6212 P1522 LD 23 -1 FP BE Pri !#3 N6213 P1523 PREFETCH 13 Int BE Nuc !#3 N6214 P1524 REPLACEMENT 22 Int BE Pri !#3 N6215 P1525 MEMBAR !#3 N6216 P1526 BSTC 10 0x4100011b FP BE Pri !#3 N6217 P1527 MEMBAR !#3 N6218 P1528 PREFETCH 24 Int BE Pri !#3 N6219 P1529 MEMBAR !#3 N6220 P1530 BLD 8 -1 FP BE Pri !#3 N6221 P1530 BLD 9 -1 FP BE Pri !#3 N6222 P1531 MEMBAR !#3 N6223 P1532 REPLACEMENT 23 Int BE Pri !#3 N6224 P1533 MEMBAR !#3 N6225 P1534 BSTC 0 0x4100011c FP BE Pri !#3 N6226 P1534 BSTC 1 0x4100011d FP BE Pri !#A N6225 N6226 !#3 N6227 P1534 BSTC 2 0x4100011e FP BE Pri !#3 N6228 P1534 BSTC 3 0x4100011f FP BE Pri !#3 N6229 P1534 BSTC 4 0x41000120 FP BE Pri !#3 N6230 P1535 MEMBAR !#3 N6231 P1536 BLD 5 -1 FP BE Pri !#3 N6232 P1536 BLD 6 -1 FP BE Pri !#3 N6233 P1537 MEMBAR !#3 N6234 P1538 BSTC 0 0x41000121 FP BE Pri !#3 N6235 P1538 BSTC 1 0x41000122 FP BE Pri !#A N6234 N6235 !#3 N6236 P1538 BSTC 2 0x41000123 FP BE Pri !#3 N6237 P1538 BSTC 3 0x41000124 FP BE Pri !#3 N6238 P1538 BSTC 4 0x41000125 FP BE Pri !#3 N6239 P1539 MEMBAR !#3 N6240 P1540 ST 14 0x180001a Int BE Pri !#3 N6241 P1541 ST 5 0x41000126 FP BE Pri !#3 N6242 P1542 MEMBAR !#3 N6243 P1543 BLD 21 -1 FP BE Pri !#3 N6244 P1543 BLD 22 -1 FP BE Pri !#A N6243 N6244 !#3 N6245 P1543 BLD 23 -1 FP BE Pri !#3 N6246 P1544 MEMBAR !#3 N6247 P1545 IDC_FLIP 20 Int BE Pri !#3 N6248 P1546 MEMBAR !#3 N6249 P1547 BST 21 0x41000127 FP BE Pri !#3 N6250 P1547 BST 22 0x41000128 FP BE Pri !#A N6249 N6250 !#3 N6251 P1547 BST 23 0x41000129 FP BE Pri !#3 N6252 P1548 MEMBAR !#3 N6253 P1549 LD 28 -1 FP BE Pri !#3 N6254 P1550 REPLACEMENT 5 Int BE Sec !#3 N6255 P1551 PREFETCH 14 Int BE Pri !#3 N6256 P1552 MEMBAR !#3 N6257 P1553 BSTC 21 0x4100012a FP BE Pri !#3 N6258 P1553 BSTC 22 0x4100012b FP BE Pri !#A N6257 N6258 !#3 N6259 P1553 BSTC 23 0x4100012c FP BE Pri !#3 N6260 P1554 MEMBAR !#3 N6261 P1555 PREFETCH 27 Int BE Pri !#3 N6262 P1556 MEMBAR !#3 N6263 P1557 BLD 30 -1 FP BE Pri !#3 N6264 P1558 MEMBAR !#3 N6265 P1559 BLD 5 -1 FP BE Pri !#3 N6266 P1559 BLD 6 -1 FP BE Pri !#3 N6267 P1560 MEMBAR !#3 N6268 P1561 REPLACEMENT 9 Int BE Nuc !#3 N6269 P1562 LD 28 -1 FP BE Sec !#3 N6270 P1563 MEMBAR !#3 N6271 P1564 BLD 18 -1 FP BE Pri !#3 N6272 P1565 MEMBAR !#3 N6273 P1566 BLD 16 -1 FP BE Pri !#3 N6274 P1567 MEMBAR !#3 N6275 P1568 LD 13 -1 FP BE Pri !#3 N6276 P1569 MEMBAR !#3 N6277 P1570 BSTC 5 0x4100012d FP BE Pri !#3 N6278 P1570 BSTC 6 0x4100012e FP BE Pri !#3 N6279 P1571 MEMBAR !#3 N6280 P1572 REPLACEMENT 31 Int BE Sec !#3 N6281 P1573 MEMBAR !#3 N6282 P1574 BLD 5 -1 FP BE Pri !#3 N6283 P1574 BLD 6 -1 FP BE Pri !#3 N6284 P1575 MEMBAR !#3 N6285 P1576 PREFETCH 19 Int BE Nuc !#3 N6286 P1577 MEMBAR !#3 N6287 P1578 BST 21 0x4100012f FP BE Pri !#3 N6288 P1578 BST 22 0x41000130 FP BE Pri !#A N6287 N6288 !#3 N6289 P1578 BST 23 0x41000131 FP BE Pri !#3 N6290 P1579 MEMBAR !#3 N6291 P1580 IDC_FLIP 13 Int BE Pri !#3 N6292 P1581 MEMBAR !#3 N6293 P1582 BSTC 16 0x41000132 FP BE Pri !#3 N6294 P1583 MEMBAR !#3 N6295 P1584 ST 13 0x41000133 FP BE Pri !#3 N6296 P1585 MEMBAR !#3 N6297 P1586 BLD 21 -1 FP BE Pri !#3 N6298 P1586 BLD 22 -1 FP BE Pri !#A N6297 N6298 !#3 N6299 P1586 BLD 23 -1 FP BE Pri !#3 N6300 P1587 MEMBAR !#3 N6301 P1588 BSTC 29 0x41000134 FP BE Pri !#3 N6302 P1589 MEMBAR !#3 N6303 P1590 IDC_FLIP 15 Int BE Pri !#3 N6304 P1591 MEMBAR !#3 N6305 P1592 BSTC 33 0x41000135 FP BE Sec !#3 N6306 P1593 MEMBAR !#3 N6307 P1594 BST 24 0x41000136 FP BE Pri !#3 N6308 P1594 BST 25 0x41000137 FP BE Pri !#3 N6309 P1595 MEMBAR !#3 N6310 P1596 LD 30 -1 FP BE Pri !#3 N6311 P1597 LD 26 -1 FP BE Sec !#3 N6312 P1598 ST 1 0x41000138 FP BE Pri !#3 N6313 P1599 LD 31 -1 Int BE Pri !#3 N6314 P1600 MEMBAR !#3 N6315 P1601 BLD 11 -1 FP BE Pri !#3 N6316 P1601 BLD 12 -1 FP BE Pri !#A N6315 N6316 !#3 N6317 P1601 BLD 13 -1 FP BE Pri !#3 N6318 P1602 MEMBAR !#3 N6319 P1603 REPLACEMENT 33 Int BE Nuc !#3 N6320 P1604 PREFETCH 12 Int BE Pri !#3 N6321 P1605 MEMBAR !#3 N6322 P1606 BST 18 0x41000139 FP BE Pri !#3 N6323 P1607 MEMBAR !#3 N6324 P1608 BLD 7 -1 FP BE Pri !#3 N6325 P1609 MEMBAR !#3 N6326 P1610 BSTC 0 0x4100013a FP BE Pri !#3 N6327 P1610 BSTC 1 0x4100013b FP BE Pri !#A N6326 N6327 !#3 N6328 P1610 BSTC 2 0x4100013c FP BE Pri !#3 N6329 P1610 BSTC 3 0x4100013d FP BE Pri !#3 N6330 P1610 BSTC 4 0x4100013e FP BE Pri !#3 N6331 P1611 MEMBAR !#3 N6332 P1612 REPLACEMENT 11 Int BE Sec !#3 N6333 P1613 REPLACEMENT 5 Int BE Pri !#3 N6334 P1614 PREFETCH 4 Int BE Nuc !#3 N6335 P1615 ST 22 0x180001b Int BE Pri !#3 N6336 P1616 REPLACEMENT 5 Int BE Pri !#3 N6337 P1617 MEMBAR !#3 N6338 P1618 BSTC 5 0x4100013f FP BE Sec !#3 N6339 P1618 BSTC 6 0x41000140 FP BE Sec !#3 N6340 P1619 MEMBAR !#3 N6341 P1620 ST 26 0x41000141 FP BE Pri !#3 N6342 P1621 ST 30 0x180001c Int BE Pri !#3 N6343 P1622 ST 6 0x180001d Int BE Pri !#3 N6344 P1623 LD 31 -1 FP BE Pri !#3 N6345 P1624 MEMBAR !#3 N6346 P1625 BST 5 0x41000142 FP BE Pri !#3 N6347 P1625 BST 6 0x41000143 FP BE Pri !#3 N6348 P1626 MEMBAR !#3 N6349 P1627 LD 11 -1 FP BE Sec !#3 N6350 P1628 MEMBAR !#3 N6351 P1629 BSTC 20 0x41000144 FP BE Sec !#3 N6352 P1630 MEMBAR !#3 N6353 P1631 BST 18 0x41000145 FP BE Pri !#3 N6354 P1632 MEMBAR !#3 N6355 P1633 BST 11 0x41000146 FP BE Sec !#3 N6356 P1633 BST 12 0x41000147 FP BE Sec !#A N6355 N6356 !#3 N6357 P1633 BST 13 0x41000148 FP BE Sec !#3 N6358 P1634 MEMBAR !#3 N6359 P1635 BLD 11 -1 FP BE Pri !#3 N6360 P1635 BLD 12 -1 FP BE Pri !#A N6359 N6360 !#3 N6361 P1635 BLD 13 -1 FP BE Pri !#3 N6362 P1636 MEMBAR !#3 N6363 P1637 PREFETCH 29 Int BE Pri !#3 N6364 P1638 MEMBAR !#3 N6365 P1639 BLD 11 -1 FP BE Pri !#3 N6366 P1639 BLD 12 -1 FP BE Pri !#A N6365 N6366 !#3 N6367 P1639 BLD 13 -1 FP BE Pri !#3 N6368 P1640 MEMBAR !#3 N6369 P1641 ST 10 0x180001e Int BE Sec !#3 N6370 P1642 LD 10 -1 Int BE Pri !#3 N6371 P1643 ST 16 0x41000149 FP BE Pri !#3 N6372 P1644 LD 26 -1 Int BE Nuc !#3 N6373 P1645 MEMBAR !#3 N6374 P1646 BLD 29 -1 FP BE Pri !#3 N6375 P1647 MEMBAR !#3 N6376 P1648 ST 24 0x4100014a FP BE Pri !#3 N6377 P1649 ST 9 0x180001f Int BE Pri !#3 N6378 P1650 ST 28 0x4100014b FP BE Pri !#3 N6379 P1651 MEMBAR !#3 N6380 P1652 BSTC 21 0x4100014c FP BE Sec !#3 N6381 P1652 BSTC 22 0x4100014d FP BE Sec !#A N6380 N6381 !#3 N6382 P1652 BSTC 23 0x4100014e FP BE Sec !#3 N6383 P1653 MEMBAR !#3 N6384 P1654 BLD 0 -1 FP BE Sec !#3 N6385 P1654 BLD 1 -1 FP BE Sec !#A N6384 N6385 !#3 N6386 P1654 BLD 2 -1 FP BE Sec !#3 N6387 P1654 BLD 3 -1 FP BE Sec !#3 N6388 P1654 BLD 4 -1 FP BE Sec !#3 N6389 P1655 MEMBAR !#3 N6390 P1656 BSTC 32 0x4100014f FP BE Pri !#3 N6391 P1657 MEMBAR !#3 N6392 P1658 IDC_FLIP 16 Int BE Pri !#3 N6393 P1659 MEMBAR !#3 N6394 P1660 BLD 0 -1 FP BE Sec !#3 N6395 P1660 BLD 1 -1 FP BE Sec !#A N6394 N6395 !#3 N6396 P1660 BLD 2 -1 FP BE Sec !#3 N6397 P1660 BLD 3 -1 FP BE Sec !#3 N6398 P1660 BLD 4 -1 FP BE Sec !#3 N6399 P1661 MEMBAR !#3 N6400 P1662 BLD 21 -1 FP BE Pri !#3 N6401 P1662 BLD 22 -1 FP BE Pri !#A N6400 N6401 !#3 N6402 P1662 BLD 23 -1 FP BE Pri !#3 N6403 P1663 MEMBAR !#3 N6404 P1664 ST 4 0x41000150 FP BE Pri !#3 N6405 P1665 IDC_FLIP 8 Int BE Pri !#3 N6406 P1666 MEMBAR !#3 N6407 P1667 BSTC 29 0x41000151 FP BE Pri !#3 N6408 P1668 MEMBAR !#3 N6409 P1669 BLD 33 -1 FP BE Pri !#3 N6410 P1670 MEMBAR !#3 N6411 P1671 BLD 0 -1 FP BE Pri !#3 N6412 P1671 BLD 1 -1 FP BE Pri !#A N6411 N6412 !#3 N6413 P1671 BLD 2 -1 FP BE Pri !#3 N6414 P1671 BLD 3 -1 FP BE Pri !#3 N6415 P1671 BLD 4 -1 FP BE Pri !#3 N6416 P1672 MEMBAR !#3 N6417 P1673 ST 9 0x41000152 FP BE Pri !#3 N6418 P1674 MEMBAR !#3 N6419 P1675 BSTC 20 0x41000153 FP BE Pri !#3 N6420 P1676 MEMBAR !#3 N6421 P1677 BLD 32 -1 FP BE Pri !#3 N6422 P1678 MEMBAR !#3 N6423 P1679 BSTC 30 0x41000154 FP BE Sec !#3 N6424 P1680 MEMBAR !#3 N6425 P1681 ST 4 0x1800020 Int BE Pri !#3 N6426 P1682 MEMBAR !#3 N6427 P1683 BSTC 24 0x41000155 FP BE Pri !#3 N6428 P1683 BSTC 25 0x41000156 FP BE Pri !#3 N6429 P1684 MEMBAR !#3 N6430 P1685 BST 31 0x41000157 FP BE Pri !#3 N6431 P1686 MEMBAR !#3 N6432 P1687 BLD 0 -1 FP BE Pri !#3 N6433 P1687 BLD 1 -1 FP BE Pri !#A N6432 N6433 !#3 N6434 P1687 BLD 2 -1 FP BE Pri !#3 N6435 P1687 BLD 3 -1 FP BE Pri !#3 N6436 P1687 BLD 4 -1 FP BE Pri !#3 N6437 P1688 MEMBAR !#3 N6438 P1689 LD 14 -1 FP BE Sec !#3 N6439 P1690 MEMBAR !#3 N6440 P1691 BST 33 0x41000158 FP BE Sec !#3 N6441 P1692 MEMBAR !#3 N6442 P1693 LD 5 -1 Int BE Pri !#3 N6443 P1694 MEMBAR !#3 N6444 P1695 BST 24 0x41000159 FP BE Pri !#3 N6445 P1695 BST 25 0x4100015a FP BE Pri !#3 N6446 P1696 MEMBAR !#3 N6447 P1697 BSTC 11 0x4100015b FP BE Pri !#3 N6448 P1697 BSTC 12 0x4100015c FP BE Pri !#A N6447 N6448 !#3 N6449 P1697 BSTC 13 0x4100015d FP BE Pri !#3 N6450 P1698 MEMBAR !#3 N6451 P1699 LD 13 -1 FP BE Pri !#3 N6452 P1700 MEMBAR !#3 N6453 P1701 BLD 15 -1 FP BE Pri !#3 N6454 P1702 MEMBAR !#3 N6455 P1703 BSTC 11 0x4100015e FP BE Pri !#3 N6456 P1703 BSTC 12 0x4100015f FP BE Pri !#A N6455 N6456 !#3 N6457 P1703 BSTC 13 0x41000160 FP BE Pri !#3 N6458 P1704 MEMBAR !#3 N6459 P1705 LD 14 -1 FP BE Sec !#3 N6460 P1706 MEMBAR !#3 N6461 P1707 BLD 5 -1 FP BE Pri !#3 N6462 P1707 BLD 6 -1 FP BE Pri !#3 N6463 P1708 MEMBAR !#3 N6464 P1709 BLD 0 -1 FP BE Pri !#3 N6465 P1709 BLD 1 -1 FP BE Pri !#A N6464 N6465 !#3 N6466 P1709 BLD 2 -1 FP BE Pri !#3 N6467 P1709 BLD 3 -1 FP BE Pri !#3 N6468 P1709 BLD 4 -1 FP BE Pri !#3 N6469 P1710 MEMBAR !#3 N6470 P1711 BLD 18 -1 FP BE Pri !#3 N6471 P1712 MEMBAR !#3 N6472 P1713 BLD 26 -1 FP BE Pri !#3 N6473 P1713 BLD 27 -1 FP BE Pri !#3 N6474 P1714 MEMBAR !#3 N6475 P1715 BLD 29 -1 FP BE Pri !#3 N6476 P1716 MEMBAR !#3 N6477 P1717 LD 5 -1 FP BE Pri !#3 N6478 P1718 MEMBAR !#3 N6479 P1719 BST 21 0x41000161 FP BE Sec !#3 N6480 P1719 BST 22 0x41000162 FP BE Sec !#A N6479 N6480 !#3 N6481 P1719 BST 23 0x41000163 FP BE Sec !#3 N6482 P1720 MEMBAR !#3 N6483 P1721 BLD 5 -1 FP BE Sec !#3 N6484 P1721 BLD 6 -1 FP BE Sec !#3 N6485 P1722 MEMBAR !#3 N6486 P1723 REPLACEMENT 20 Int BE Pri !#3 N6487 P1724 MEMBAR !#3 N6488 P1725 BSTC 11 0x41000164 FP BE Pri !#3 N6489 P1725 BSTC 12 0x41000165 FP BE Pri !#A N6488 N6489 !#3 N6490 P1725 BSTC 13 0x41000166 FP BE Pri !#3 N6491 P1726 MEMBAR !#3 N6492 P1727 PREFETCH 22 Int BE Pri !#3 N6493 P1728 LD 7 -1 FP BE Pri !#3 N6494 P1729 MEMBAR !#3 N6495 P1730 BLD 26 -1 FP BE Pri !#3 N6496 P1730 BLD 27 -1 FP BE Pri !#3 N6497 P1731 MEMBAR !#3 N6498 P1732 BSTC 24 0x41000167 FP BE Sec !#3 N6499 P1732 BSTC 25 0x41000168 FP BE Sec !#3 N6500 P1733 MEMBAR !#3 N6501 P1734 BLD 0 -1 FP BE Pri !#3 N6502 P1734 BLD 1 -1 FP BE Pri !#A N6501 N6502 !#3 N6503 P1734 BLD 2 -1 FP BE Pri !#3 N6504 P1734 BLD 3 -1 FP BE Pri !#3 N6505 P1734 BLD 4 -1 FP BE Pri !#3 N6506 P1735 MEMBAR !#3 N6507 P1736 PREFETCH 15 Int BE Pri !#3 N6508 P1737 MEMBAR !#3 N6509 P1738 BST 20 0x41000169 FP BE Sec !#3 N6510 P1739 MEMBAR !#3 N6511 P1740 REPLACEMENT 4 Int BE Pri !#3 N6512 P1741 IDC_FLIP 12 Int BE Pri !#3 N6513 P1742 REPLACEMENT 31 Int BE Pri !#3 N6514 P1743 MEMBAR !#3 N6515 P1744 BST 21 0x4100016a FP BE Pri !#3 N6516 P1744 BST 22 0x4100016b FP BE Pri !#A N6515 N6516 !#3 N6517 P1744 BST 23 0x4100016c FP BE Pri !#3 N6518 P1745 MEMBAR !#3 N6519 P1746 BLD 0 -1 FP BE Pri !#3 N6520 P1746 BLD 1 -1 FP BE Pri !#A N6519 N6520 !#3 N6521 P1746 BLD 2 -1 FP BE Pri !#3 N6522 P1746 BLD 3 -1 FP BE Pri !#3 N6523 P1746 BLD 4 -1 FP BE Pri !#3 N6524 P1747 MEMBAR !#3 N6525 P1748 REPLACEMENT 25 Int BE Pri !#3 N6526 P1749 MEMBAR !#3 N6527 P1750 BLD 29 -1 FP BE Pri !#3 N6528 P1751 MEMBAR !#3 N6529 P1752 REPLACEMENT 14 Int BE Pri !#3 N6530 P1753 ST 3 0x1800021 Int BE Pri !#3 N6531 P1754 MEMBAR !#3 N6532 P1755 BST 21 0x4100016d FP BE Pri !#3 N6533 P1755 BST 22 0x4100016e FP BE Pri !#A N6532 N6533 !#3 N6534 P1755 BST 23 0x4100016f FP BE Pri !#3 N6535 P1756 MEMBAR !#3 N6536 P1757 REPLACEMENT 14 Int BE Nuc !#3 N6537 P1758 MEMBAR !#3 N6538 P1759 BSTC 14 0x41000170 FP BE Pri !#3 N6539 P1760 MEMBAR !#3 N6540 P1761 BST 32 0x41000171 FP BE Pri !#3 N6541 P1762 MEMBAR !#3 N6542 P1763 BLD 18 -1 FP BE Sec !#3 N6543 P1764 MEMBAR !#3 N6544 P1765 PREFETCH 9 Int BE Nuc !#3 N6545 P1766 MEMBAR !#3 N6546 P1767 BLD 21 -1 FP BE Pri !#3 N6547 P1767 BLD 22 -1 FP BE Pri !#A N6546 N6547 !#3 N6548 P1767 BLD 23 -1 FP BE Pri !#3 N6549 P1768 MEMBAR !#3 N6550 P1769 LD 12 -1 FP BE Pri !#3 N6551 P1770 REPLACEMENT 1 Int BE Pri !#3 N6552 P1771 MEMBAR !#3 N6553 P1772 BSTC 30 0x41000172 FP BE Pri !#3 N6554 P1773 MEMBAR !#3 N6555 P1774 LD 9 -1 FP BE Pri !#3 N6556 P1775 MEMBAR !#3 N6557 P1776 BLD 33 -1 FP BE Sec !#3 N6558 P1777 MEMBAR !#3 N6559 P1778 BST 21 0x41000173 FP BE Pri !#3 N6560 P1778 BST 22 0x41000174 FP BE Pri !#A N6559 N6560 !#3 N6561 P1778 BST 23 0x41000175 FP BE Pri !#3 N6562 P1779 MEMBAR !#3 N6563 P1780 PREFETCH 13 Int LE Pri !#3 N6564 P1781 ST 6 0x41000176 FP BE Pri !#3 N6565 P1782 LD 4 -1 Int BE Pri !#3 N6566 P1783 MEMBAR !#3 N6567 P1784 BLD 0 -1 FP BE Pri !#3 N6568 P1784 BLD 1 -1 FP BE Pri !#A N6567 N6568 !#3 N6569 P1784 BLD 2 -1 FP BE Pri !#3 N6570 P1784 BLD 3 -1 FP BE Pri !#3 N6571 P1784 BLD 4 -1 FP BE Pri !#3 N6572 P1785 MEMBAR !#3 N6573 P1786 BST 8 0x41000177 FP BE Pri !#3 N6574 P1786 BST 9 0x41000178 FP BE Pri !#3 N6575 P1787 MEMBAR !#3 N6576 P1788 PREFETCH 15 Int BE Pri !#3 N6577 P1789 MEMBAR !#3 N6578 P1790 BLD 11 -1 FP BE Pri !#3 N6579 P1790 BLD 12 -1 FP BE Pri !#A N6578 N6579 !#3 N6580 P1790 BLD 13 -1 FP BE Pri !#3 N6581 P1791 MEMBAR !#3 N6582 P1792 PREFETCH 10 Int BE Pri !#3 N6583 P1793 MEMBAR !#3 N6584 P1794 BLD 8 -1 FP BE Sec !#3 N6585 P1794 BLD 9 -1 FP BE Sec !#3 N6586 P1795 MEMBAR !#3 N6587 P1796 REPLACEMENT 28 Int BE Pri !#3 N6588 P1797 MEMBAR !#3 N6589 P1798 BSTC 21 0x41000179 FP BE Pri !#3 N6590 P1798 BSTC 22 0x4100017a FP BE Pri !#A N6589 N6590 !#3 N6591 P1798 BSTC 23 0x4100017b FP BE Pri !#3 N6592 P1799 MEMBAR !#3 N6593 P1800 ST 0 0x1800022 Int BE Pri !#3 N6594 P1801 MEMBAR !#3 N6595 P1802 BLD 11 -1 FP BE Pri !#3 N6596 P1802 BLD 12 -1 FP BE Pri !#A N6595 N6596 !#3 N6597 P1802 BLD 13 -1 FP BE Pri !#3 N6598 P1803 MEMBAR !#3 N6599 P1804 PREFETCH 16 Int BE Pri !#3 N6600 P1805 REPLACEMENT 15 Int BE Pri !#3 N6601 P1806 LD 8 -1 Int BE Pri !#3 N6602 P1807 PREFETCH 6 Int BE Pri !#3 N6603 P1808 MEMBAR !#3 N6604 P1809 BLD 17 -1 FP BE Pri !#3 N6605 P1810 MEMBAR !#3 N6606 P1811 BLD 26 -1 FP BE Pri !#3 N6607 P1811 BLD 27 -1 FP BE Pri !#3 N6608 P1812 MEMBAR !#3 N6609 P1813 ST 10 0x1800023 Int BE Pri !#3 N6610 P1814 REPLACEMENT 30 Int BE Nuc !#3 N6611 P1815 PREFETCH 17 Int BE Pri !#3 N6612 P1816 MEMBAR !#3 N6613 P1817 BST 8 0x4100017c FP BE Pri !#3 N6614 P1817 BST 9 0x4100017d FP BE Pri !#3 N6615 P1818 MEMBAR !#3 N6616 P1819 PREFETCH 12 Int BE Sec !#3 N6617 P1820 REPLACEMENT 26 Int BE Sec !#3 N6618 P1821 LD 7 -1 Int BE Pri !#3 N6619 P1822 PREFETCH 8 Int BE Pri !#3 N6620 P1823 ST 14 0x1800024 Int LE Pri !#3 N6621 P1824 LD 25 -1 Int BE Nuc !#3 N6622 P1825 LD 0 -1 FP BE Pri !#3 N6623 P1826 REPLACEMENT 5 Int BE Pri !#3 N6624 P1827 REPLACEMENT 25 Int BE Nuc !#3 N6625 P1828 MEMBAR !#3 N6626 P1829 BLD 31 -1 FP BE Pri !#3 N6627 P1830 MEMBAR !#3 N6628 P1831 BLD 24 -1 FP BE Pri !#3 N6629 P1831 BLD 25 -1 FP BE Pri !#3 N6630 P1832 MEMBAR !#3 N6631 P1833 ST 27 0x4100017e FP BE Pri !#3 N6632 P1834 REPLACEMENT 9 Int BE Pri !#3 N6633 P1835 FLUSHI 24 Int BE Pri !#3 N6634 P1836 MEMBAR !#3 N6635 P1837 BLD 26 -1 FP BE Pri !#3 N6636 P1837 BLD 27 -1 FP BE Pri !#3 N6637 P1838 MEMBAR !#3 N6638 P1839 BST 11 0x4100017f FP BE Pri !#3 N6639 P1839 BST 12 0x41000180 FP BE Pri !#A N6638 N6639 !#3 N6640 P1839 BST 13 0x41000181 FP BE Pri !#3 N6641 P1840 MEMBAR !#3 N6642 P1841 BSTC 30 0x41000182 FP BE Pri !#3 N6643 P1842 MEMBAR !#3 N6644 P1843 LD 23 -1 Int BE Sec !#3 N6645 P1844 REPLACEMENT 9 Int BE Sec !#3 N6646 P1845 REPLACEMENT 33 Int BE Pri !#3 N6647 P1846 MEMBAR !#3 N6648 P1847 BLD 11 -1 FP BE Pri !#3 N6649 P1847 BLD 12 -1 FP BE Pri !#A N6648 N6649 !#3 N6650 P1847 BLD 13 -1 FP BE Pri !#3 N6651 P1848 MEMBAR !#3 N6652 P1849 BST 0 0x41000183 FP BE Pri !#3 N6653 P1849 BST 1 0x41000184 FP BE Pri !#A N6652 N6653 !#3 N6654 P1849 BST 2 0x41000185 FP BE Pri !#3 N6655 P1849 BST 3 0x41000186 FP BE Pri !#3 N6656 P1849 BST 4 0x41000187 FP BE Pri !#3 N6657 P1850 MEMBAR !#3 N6658 P1851 BSTC 15 0x41000188 FP BE Pri !#3 N6659 P1852 MEMBAR !#3 N6660 P1853 BST 0 0x41000189 FP BE Pri !#3 N6661 P1853 BST 1 0x4100018a FP BE Pri !#A N6660 N6661 !#3 N6662 P1853 BST 2 0x4100018b FP BE Pri !#3 N6663 P1853 BST 3 0x4100018c FP BE Pri !#3 N6664 P1853 BST 4 0x4100018d FP BE Pri !#3 N6665 P1854 MEMBAR !#3 N6666 P1855 REPLACEMENT 7 Int BE Pri !#3 N6667 P1856 REPLACEMENT 10 Int BE Sec !#3 N6668 P1857 REPLACEMENT 9 Int BE Pri !#3 N6669 P1858 REPLACEMENT 32 Int BE Nuc !#3 N6670 P1859 REPLACEMENT 8 Int BE Pri !#3 N6671 P1860 MEMBAR !#3 N6672 P1861 BSTC 28 0x4100018e FP BE Sec !#3 N6673 P1862 MEMBAR !#3 N6674 P1863 BLD 21 -1 FP BE Sec !#3 N6675 P1863 BLD 22 -1 FP BE Sec !#A N6674 N6675 !#3 N6676 P1863 BLD 23 -1 FP BE Sec !#3 N6677 P1864 MEMBAR !#3 N6678 P1865 BLD 8 -1 FP BE Pri !#3 N6679 P1865 BLD 9 -1 FP BE Pri !#3 N6680 P1866 MEMBAR !#3 N6681 P1867 BLD 0 -1 FP BE Sec !#3 N6682 P1867 BLD 1 -1 FP BE Sec !#A N6681 N6682 !#3 N6683 P1867 BLD 2 -1 FP BE Sec !#3 N6684 P1867 BLD 3 -1 FP BE Sec !#3 N6685 P1867 BLD 4 -1 FP BE Sec !#3 N6686 P1868 MEMBAR !#3 N6687 P1869 BLD 18 -1 FP BE Pri !#3 N6688 P1870 MEMBAR !#3 N6689 P1871 BSTC 20 0x4100018f FP BE Pri !#3 N6690 P1872 MEMBAR !#3 N6691 P1873 BLD 18 -1 FP BE Pri !#3 N6692 P1874 MEMBAR !#3 N6693 P1875 ST 9 0x1800025 Int BE Pri !#3 N6694 P1876 MEMBAR !#3 N6695 P1877 BLD 5 -1 FP BE Pri !#3 N6696 P1877 BLD 6 -1 FP BE Pri !#3 N6697 P1878 MEMBAR !#3 N6698 P1879 LD 9 -1 Int BE Pri !#3 N6699 P1880 MEMBAR !#3 N6700 P1881 BSTC 21 0x41000190 FP BE Sec !#3 N6701 P1881 BSTC 22 0x41000191 FP BE Sec !#A N6700 N6701 !#3 N6702 P1881 BSTC 23 0x41000192 FP BE Sec !#3 N6703 P1882 MEMBAR !#3 N6704 P1883 BSTC 28 0x41000193 FP BE Pri !#3 N6705 P1884 MEMBAR !#3 N6706 P1885 BLD 14 -1 FP BE Pri !#3 N6707 P1886 MEMBAR !#3 N6708 P1887 LD 25 -1 FP BE Sec !#3 N6709 P1888 PREFETCH 25 Int BE Pri !#3 N6710 P1889 MEMBAR !#3 N6711 P1890 BSTC 11 0x41000194 FP BE Sec !#3 N6712 P1890 BSTC 12 0x41000195 FP BE Sec !#A N6711 N6712 !#3 N6713 P1890 BSTC 13 0x41000196 FP BE Sec !#3 N6714 P1891 MEMBAR !#3 N6715 P1892 PREFETCH 32 Int BE Nuc !#3 N6716 P1893 ST 7 0x1800026 Int BE Pri !#3 N6717 P1894 REPLACEMENT 32 Int BE Pri !#3 N6718 P1895 ST 1 0x1800027 Int BE Pri !#3 N6719 P1896 ST 10 0x41000197 FP BE Sec !#3 N6720 P1897 PREFETCH 3 Int BE Pri !#3 N6721 P1898 REPLACEMENT 31 Int BE Pri !#3 N6722 P1899 MEMBAR !#3 N6723 P1900 BST 21 0x41000198 FP BE Pri !#3 N6724 P1900 BST 22 0x41000199 FP BE Pri !#A N6723 N6724 !#3 N6725 P1900 BST 23 0x4100019a FP BE Pri !#3 N6726 P1901 MEMBAR !#3 N6727 P1902 BLD 5 -1 FP BE Pri !#3 N6728 P1902 BLD 6 -1 FP BE Pri !#3 N6729 P1903 MEMBAR !#3 N6730 P1904 PREFETCH 5 Int BE Pri !#3 N6731 P1905 PREFETCH 10 Int BE Pri !#3 N6732 P1906 REPLACEMENT 5 Int BE Pri !#3 N6733 P1907 MEMBAR !#3 N6734 P1908 BLD 21 -1 FP BE Pri !#3 N6735 P1908 BLD 22 -1 FP BE Pri !#A N6734 N6735 !#3 N6736 P1908 BLD 23 -1 FP BE Pri !#3 N6737 P1909 MEMBAR !#3 N6738 P1910 BLD 24 -1 FP BE Pri !#3 N6739 P1910 BLD 25 -1 FP BE Pri !#3 N6740 P1911 MEMBAR !#3 N6741 P1912 LD 23 -1 FP BE Pri !#3 N6742 P1913 MEMBAR !#3 N6743 P1914 BLD 10 -1 FP BE Pri !#3 N6744 P1915 MEMBAR !#3 N6745 P1916 BST 14 0x4100019b FP BE Pri !#3 N6746 P1917 MEMBAR !#3 N6747 P1918 BLD 32 -1 FP BE Pri !#3 N6748 P1919 MEMBAR !#3 N6749 P1920 PREFETCH 27 Int BE Pri !#3 N6750 P1921 MEMBAR !#3 N6751 P1922 BLD 0 -1 FP BE Pri !#3 N6752 P1922 BLD 1 -1 FP BE Pri !#A N6751 N6752 !#3 N6753 P1922 BLD 2 -1 FP BE Pri !#3 N6754 P1922 BLD 3 -1 FP BE Pri !#3 N6755 P1922 BLD 4 -1 FP BE Pri !#3 N6756 P1923 MEMBAR !#3 N6757 P1924 BSTC 5 0x4100019c FP BE Sec !#3 N6758 P1924 BSTC 6 0x4100019d FP BE Sec !#3 N6759 P1925 MEMBAR !#3 N6760 P1926 BLD 8 -1 FP BE Pri !#3 N6761 P1926 BLD 9 -1 FP BE Pri !#3 N6762 P1927 MEMBAR !#3 N6763 P1928 LD 25 -1 Int BE Pri !#3 N6764 P1929 MEMBAR !#3 N6765 P1930 BLD 10 -1 FP BE Pri !#3 N6766 P1931 MEMBAR !#3 N6767 P1932 ST 33 0x1800028 Int BE Sec !#3 N6768 P1933 PREFETCH 30 Int BE Pri !#3 N6769 P1934 MEMBAR !#3 N6770 P1935 BST 32 0x4100019e FP BE Pri !#3 N6771 P1936 MEMBAR !#3 N6772 P1937 LD 3 -1 Int BE Nuc !#3 N6773 P1938 MEMBAR !#3 N6774 P1939 BLD 33 -1 FP BE Pri !#3 N6775 P1940 MEMBAR !#3 N6776 P1941 LD 14 -1 Int BE Pri Loop_exit !#3 N6777 P1942 MEMBAR !#4 N6778 P1943 MEMBAR !#4 N6779 P1944 BST 5 0x41800001 FP BE Pri !#4 N6780 P1944 BST 6 0x41800002 FP BE Pri !#4 N6781 P1945 MEMBAR !#4 N6782 P1946 LD 29 -1 FP BE Pri !#4 N6783 P1947 ST 26 0x2000001 Int BE Pri !#4 N6784 P1948 ST 14 0x41800003 FP BE Pri !#4 N6785 P1949 MEMBAR !#4 N6786 P1950 REPLACEMENT 4 Int BE Pri !#4 N6787 P1951 MEMBAR !#4 N6788 P1952 BLD 11 -1 FP BE Pri !#4 N6789 P1952 BLD 12 -1 FP BE Pri !#A N6788 N6789 !#4 N6790 P1952 BLD 13 -1 FP BE Pri !#4 N6791 P1953 MEMBAR !#4 N6792 P1954 BST 33 0x41800004 FP BE Pri !#4 N6793 P1955 MEMBAR !#4 N6794 P1956 REPLACEMENT 28 Int BE Nuc !#4 N6795 P1957 PREFETCH 27 Int BE Pri !#4 N6796 P1958 REPLACEMENT 26 Int BE Pri !#4 N6797 P1959 MEMBAR !#4 N6798 P1960 BST 11 0x41800005 FP BE Sec !#4 N6799 P1960 BST 12 0x41800006 FP BE Sec !#A N6798 N6799 !#4 N6800 P1960 BST 13 0x41800007 FP BE Sec !#4 N6801 P1961 MEMBAR !#4 N6802 P1962 REPLACEMENT 1 Int BE Pri !#4 N6803 P1963 MEMBAR !#4 N6804 P1964 BSTC 5 0x41800008 FP BE Sec !#4 N6805 P1964 BSTC 6 0x41800009 FP BE Sec !#4 N6806 P1965 MEMBAR !#4 N6807 P1966 BSTC 26 0x4180000a FP BE Pri !#4 N6808 P1966 BSTC 27 0x4180000b FP BE Pri !#4 N6809 P1967 MEMBAR !#4 N6810 P1968 LD 9 -1 Int BE Pri !#4 N6811 P1969 MEMBAR !#4 N6812 P1970 BLD 5 -1 FP BE Pri !#4 N6813 P1970 BLD 6 -1 FP BE Pri !#4 N6814 P1971 MEMBAR !#4 N6815 P1972 BST 15 0x4180000c FP BE Pri !#4 N6816 P1973 MEMBAR !#4 N6817 P1974 BLD 24 -1 FP BE Pri !#4 N6818 P1974 BLD 25 -1 FP BE Pri !#4 N6819 P1975 MEMBAR !#4 N6820 P1976 REPLACEMENT 24 Int BE Pri !#4 N6821 P1977 MEMBAR !#4 N6822 P1978 BST 20 0x4180000d FP BE Pri !#4 N6823 P1979 MEMBAR !#4 N6824 P1980 PREFETCH 30 Int BE Pri !#4 N6825 P1981 MEMBAR !#4 N6826 P1982 BLD 11 -1 FP BE Pri !#4 N6827 P1982 BLD 12 -1 FP BE Pri !#A N6826 N6827 !#4 N6828 P1982 BLD 13 -1 FP BE Pri !#4 N6829 P1983 MEMBAR !#4 N6830 P1984 BSTC 17 0x4180000e FP BE Pri !#4 N6831 P1985 MEMBAR !#4 N6832 P1986 BSTC 11 0x4180000f FP BE Pri !#4 N6833 P1986 BSTC 12 0x41800010 FP BE Pri !#A N6832 N6833 !#4 N6834 P1986 BSTC 13 0x41800011 FP BE Pri !#4 N6835 P1987 MEMBAR !#4 N6836 P1988 ST 27 0x41800012 FP BE Sec !#4 N6837 P1989 MEMBAR !#4 N6838 P1990 BLD 10 -1 FP BE Pri !#4 N6839 P1991 MEMBAR !#4 N6840 P1992 BLD 20 -1 FP BE Pri !#4 N6841 P1993 MEMBAR !#4 N6842 P1994 REPLACEMENT 32 Int BE Pri !#4 N6843 P1995 ST 8 0x41800013 FP BE Pri !#4 N6844 P1996 MEMBAR !#4 N6845 P1997 BSTC 15 0x41800014 FP BE Pri !#4 N6846 P1998 MEMBAR !#4 N6847 P1999 ST 10 0x41800015 FP BE Pri !#4 N6848 P2000 PREFETCH 30 Int BE Pri !#4 N6849 P2001 REPLACEMENT 31 Int BE Pri !#4 N6850 P2002 MEMBAR !#4 N6851 P2003 BSTC 7 0x41800016 FP BE Pri !#4 N6852 P2004 MEMBAR !#4 N6853 P2005 REPLACEMENT 14 Int BE Pri !#4 N6854 P2006 MEMBAR !#4 N6855 P2007 BLD 20 -1 FP BE Pri !#4 N6856 P2008 MEMBAR !#4 N6857 P2009 PREFETCH 30 Int BE Sec !#4 N6858 P2010 MEMBAR !#4 N6859 P2011 BLD 14 -1 FP BE Pri !#4 N6860 P2012 MEMBAR !#4 N6861 P2013 BST 31 0x41800017 FP BE Pri !#4 N6862 P2014 MEMBAR !#4 N6863 P2015 BLD 0 -1 FP BE Pri !#4 N6864 P2015 BLD 1 -1 FP BE Pri !#A N6863 N6864 !#4 N6865 P2015 BLD 2 -1 FP BE Pri !#4 N6866 P2015 BLD 3 -1 FP BE Pri !#4 N6867 P2015 BLD 4 -1 FP BE Pri !#4 N6868 P2016 MEMBAR !#4 N6869 P2017 BST 24 0x41800018 FP BE Pri !#4 N6870 P2017 BST 25 0x41800019 FP BE Pri !#4 N6871 P2018 MEMBAR !#4 N6872 P2019 BLD 26 -1 FP BE Sec !#4 N6873 P2019 BLD 27 -1 FP BE Sec !#4 N6874 P2020 MEMBAR !#4 N6875 P2021 PREFETCH 19 Int BE Pri !#4 N6876 P2022 REPLACEMENT 26 Int BE Pri !#4 N6877 P2023 LD 3 -1 Int BE Sec !#4 N6878 P2024 MEMBAR !#4 N6879 P2025 BLD 30 -1 FP BE Pri !#4 N6880 P2026 MEMBAR !#4 N6881 P2027 BLD 24 -1 FP BE Pri !#4 N6882 P2027 BLD 25 -1 FP BE Pri !#4 N6883 P2028 MEMBAR !#4 N6884 P2029 BLD 5 -1 FP BE Pri !#4 N6885 P2029 BLD 6 -1 FP BE Pri !#4 N6886 P2030 MEMBAR !#4 N6887 P2031 REPLACEMENT 5 Int BE Nuc !#4 N6888 P2032 LD 16 -1 FP BE Sec !#4 N6889 P2033 REPLACEMENT 22 Int BE Pri !#4 N6890 P2034 ST 18 0x2000002 Int BE Sec !#4 N6891 P2035 ST 24 0x2000003 Int LE Nuc !#4 N6892 P2036 MEMBAR !#4 N6893 P2037 BLD 26 -1 FP BE Pri !#4 N6894 P2037 BLD 27 -1 FP BE Pri !#4 N6895 P2038 MEMBAR !#4 N6896 P2039 BLD 0 -1 FP BE Pri !#4 N6897 P2039 BLD 1 -1 FP BE Pri !#A N6896 N6897 !#4 N6898 P2039 BLD 2 -1 FP BE Pri !#4 N6899 P2039 BLD 3 -1 FP BE Pri !#4 N6900 P2039 BLD 4 -1 FP BE Pri !#4 N6901 P2040 MEMBAR !#4 N6902 P2041 IDC_FLIP 22 Int BE Pri !#4 N6903 P2042 MEMBAR !#4 N6904 P2043 BLD 11 -1 FP BE Pri !#4 N6905 P2043 BLD 12 -1 FP BE Pri !#A N6904 N6905 !#4 N6906 P2043 BLD 13 -1 FP BE Pri !#4 N6907 P2044 MEMBAR !#4 N6908 P2045 BLD 26 -1 FP BE Pri !#4 N6909 P2045 BLD 27 -1 FP BE Pri !#4 N6910 P2046 MEMBAR !#4 N6911 P2047 PREFETCH 4 Int BE Pri !#4 N6912 P2048 MEMBAR !#4 N6913 P2049 BLD 5 -1 FP BE Pri !#4 N6914 P2049 BLD 6 -1 FP BE Pri !#4 N6915 P2050 MEMBAR !#4 N6916 P2051 BLD 26 -1 FP BE Pri !#4 N6917 P2051 BLD 27 -1 FP BE Pri !#4 N6918 P2052 MEMBAR !#4 N6919 P2053 BLD 28 -1 FP BE Pri !#4 N6920 P2054 MEMBAR !#4 N6921 P2055 REPLACEMENT 9 Int BE Pri !#4 N6922 P2056 REPLACEMENT 3 Int BE Pri !#4 N6923 P2057 ST 13 0x2000004 Int BE Pri !#4 N6924 P2058 MEMBAR !#4 N6925 P2059 BSTC 24 0x4180001a FP BE Sec !#4 N6926 P2059 BSTC 25 0x4180001b FP BE Sec !#4 N6927 P2060 MEMBAR !#4 N6928 P2061 LD 22 -1 Int BE Sec !#4 N6929 P2062 MEMBAR !#4 N6930 P2063 BLD 10 -1 FP BE Sec !#4 N6931 P2064 MEMBAR !#4 N6932 P2065 REPLACEMENT 2 Int BE Pri !#4 N6933 P2066 PREFETCH 17 Int BE Pri !#4 N6934 P2067 REPLACEMENT 17 Int BE Pri !#4 N6935 P2068 ST 29 0x2000005 Int LE Pri !#4 N6936 P2069 MEMBAR !#4 N6937 P2070 BLD 17 -1 FP BE Pri !#4 N6938 P2071 MEMBAR !#4 N6939 P2072 BLD 21 -1 FP BE Pri !#4 N6940 P2072 BLD 22 -1 FP BE Pri !#A N6939 N6940 !#4 N6941 P2072 BLD 23 -1 FP BE Pri !#4 N6942 P2073 MEMBAR !#4 N6943 P2074 LD 14 -1 Int BE Pri !#4 N6944 P2075 REPLACEMENT 6 Int BE Pri !#4 N6945 P2076 MEMBAR !#4 N6946 P2077 BST 24 0x4180001c FP BE Pri !#4 N6947 P2077 BST 25 0x4180001d FP BE Pri !#4 N6948 P2078 MEMBAR !#4 N6949 P2079 BLD 20 -1 FP BE Pri !#4 N6950 P2080 MEMBAR !#4 N6951 P2081 BLD 21 -1 FP BE Sec !#4 N6952 P2081 BLD 22 -1 FP BE Sec !#A N6951 N6952 !#4 N6953 P2081 BLD 23 -1 FP BE Sec !#4 N6954 P2082 MEMBAR !#4 N6955 P2083 LD 32 -1 FP BE Pri !#4 N6956 P2084 MEMBAR !#4 N6957 P2085 BSTC 8 0x4180001e FP BE Pri !#4 N6958 P2085 BSTC 9 0x4180001f FP BE Pri !#4 N6959 P2086 MEMBAR !#4 N6960 P2087 BLD 20 -1 FP BE Pri !#4 N6961 P2088 MEMBAR !#4 N6962 P2089 LD 27 -1 FP BE Pri !#4 N6963 P2090 MEMBAR !#4 N6964 P2091 BLD 29 -1 FP BE Sec !#4 N6965 P2092 MEMBAR !#4 N6966 P2093 BLD 7 -1 FP BE Sec !#4 N6967 P2094 MEMBAR !#4 N6968 P2095 BLD 21 -1 FP BE Sec !#4 N6969 P2095 BLD 22 -1 FP BE Sec !#A N6968 N6969 !#4 N6970 P2095 BLD 23 -1 FP BE Sec !#4 N6971 P2096 MEMBAR !#4 N6972 P2097 LD 6 -1 FP BE Sec !#4 N6973 P2098 LD 8 -1 Int BE Pri !#4 N6974 P2099 MEMBAR !#4 N6975 P2100 BLD 8 -1 FP BE Pri !#4 N6976 P2100 BLD 9 -1 FP BE Pri !#4 N6977 P2101 MEMBAR !#4 N6978 P2102 BLD 21 -1 FP BE Pri !#4 N6979 P2102 BLD 22 -1 FP BE Pri !#A N6978 N6979 !#4 N6980 P2102 BLD 23 -1 FP BE Pri !#4 N6981 P2103 MEMBAR !#4 N6982 P2104 REPLACEMENT 23 Int BE Sec !#4 N6983 P2105 ST 26 0x41800020 FP BE Pri !#4 N6984 P2106 REPLACEMENT 6 Int BE Pri !#4 N6985 P2107 LD 27 -1 FP BE Nuc !#4 N6986 P2108 LD 21 -1 FP BE Pri !#4 N6987 P2109 MEMBAR !#4 N6988 P2110 BST 26 0x41800021 FP BE Pri !#4 N6989 P2110 BST 27 0x41800022 FP BE Pri !#4 N6990 P2111 MEMBAR !#4 N6991 P2112 ST 14 0x2000006 Int BE Nuc !#4 N6992 P2113 REPLACEMENT 2 Int BE Pri !#4 N6993 P2114 REPLACEMENT 16 Int BE Pri !#4 N6994 P2115 REPLACEMENT 24 Int BE Pri !#4 N6995 P2116 REPLACEMENT 24 Int BE Pri !#4 N6996 P2117 REPLACEMENT 23 Int BE Pri !#4 N6997 P2118 MEMBAR !#4 N6998 P2119 BSTC 33 0x41800023 FP BE Pri !#4 N6999 P2120 MEMBAR !#4 N7000 P2121 PREFETCH 19 Int BE Pri !#4 N7001 P2122 LD 0 -1 Int BE Pri Loop_exit !#4 N7002 P1943 MEMBAR !#4 N7003 P1944 BST 5 0x41800024 FP BE Pri !#4 N7004 P1944 BST 6 0x41800025 FP BE Pri !#4 N7005 P1945 MEMBAR !#4 N7006 P1946 LD 29 -1 FP BE Pri !#4 N7007 P1947 ST 26 0x2000007 Int BE Pri !#4 N7008 P1948 ST 14 0x41800026 FP BE Pri !#4 N7009 P1949 MEMBAR !#4 N7010 P1950 REPLACEMENT 4 Int BE Pri !#4 N7011 P1951 MEMBAR !#4 N7012 P1952 BLD 11 -1 FP BE Pri !#4 N7013 P1952 BLD 12 -1 FP BE Pri !#A N7012 N7013 !#4 N7014 P1952 BLD 13 -1 FP BE Pri !#4 N7015 P1953 MEMBAR !#4 N7016 P1954 BST 33 0x41800027 FP BE Pri !#4 N7017 P1955 MEMBAR !#4 N7018 P1956 REPLACEMENT 28 Int BE Nuc !#4 N7019 P1957 PREFETCH 27 Int BE Pri !#4 N7020 P1958 REPLACEMENT 26 Int BE Pri !#4 N7021 P1959 MEMBAR !#4 N7022 P1960 BST 11 0x41800028 FP BE Sec !#4 N7023 P1960 BST 12 0x41800029 FP BE Sec !#A N7022 N7023 !#4 N7024 P1960 BST 13 0x4180002a FP BE Sec !#4 N7025 P1961 MEMBAR !#4 N7026 P1962 REPLACEMENT 1 Int BE Pri !#4 N7027 P1963 MEMBAR !#4 N7028 P1964 BSTC 5 0x4180002b FP BE Sec !#4 N7029 P1964 BSTC 6 0x4180002c FP BE Sec !#4 N7030 P1965 MEMBAR !#4 N7031 P1966 BSTC 26 0x4180002d FP BE Pri !#4 N7032 P1966 BSTC 27 0x4180002e FP BE Pri !#4 N7033 P1967 MEMBAR !#4 N7034 P1968 LD 9 -1 Int BE Pri !#4 N7035 P1969 MEMBAR !#4 N7036 P1970 BLD 5 -1 FP BE Pri !#4 N7037 P1970 BLD 6 -1 FP BE Pri !#4 N7038 P1971 MEMBAR !#4 N7039 P1972 BST 15 0x4180002f FP BE Pri !#4 N7040 P1973 MEMBAR !#4 N7041 P1974 BLD 24 -1 FP BE Pri !#4 N7042 P1974 BLD 25 -1 FP BE Pri !#4 N7043 P1975 MEMBAR !#4 N7044 P1976 REPLACEMENT 24 Int BE Pri !#4 N7045 P1977 MEMBAR !#4 N7046 P1978 BST 20 0x41800030 FP BE Pri !#4 N7047 P1979 MEMBAR !#4 N7048 P1980 PREFETCH 30 Int BE Pri !#4 N7049 P1981 MEMBAR !#4 N7050 P1982 BLD 11 -1 FP BE Pri !#4 N7051 P1982 BLD 12 -1 FP BE Pri !#A N7050 N7051 !#4 N7052 P1982 BLD 13 -1 FP BE Pri !#4 N7053 P1983 MEMBAR !#4 N7054 P1984 BSTC 17 0x41800031 FP BE Pri !#4 N7055 P1985 MEMBAR !#4 N7056 P1986 BSTC 11 0x41800032 FP BE Pri !#4 N7057 P1986 BSTC 12 0x41800033 FP BE Pri !#A N7056 N7057 !#4 N7058 P1986 BSTC 13 0x41800034 FP BE Pri !#4 N7059 P1987 MEMBAR !#4 N7060 P1988 ST 27 0x41800035 FP BE Sec !#4 N7061 P1989 MEMBAR !#4 N7062 P1990 BLD 10 -1 FP BE Pri !#4 N7063 P1991 MEMBAR !#4 N7064 P1992 BLD 20 -1 FP BE Pri !#4 N7065 P1993 MEMBAR !#4 N7066 P1994 REPLACEMENT 32 Int BE Pri !#4 N7067 P1995 ST 8 0x41800036 FP BE Pri !#4 N7068 P1996 MEMBAR !#4 N7069 P1997 BSTC 15 0x41800037 FP BE Pri !#4 N7070 P1998 MEMBAR !#4 N7071 P1999 ST 10 0x41800038 FP BE Pri !#4 N7072 P2000 PREFETCH 30 Int BE Pri !#4 N7073 P2001 REPLACEMENT 31 Int BE Pri !#4 N7074 P2002 MEMBAR !#4 N7075 P2003 BSTC 7 0x41800039 FP BE Pri !#4 N7076 P2004 MEMBAR !#4 N7077 P2005 REPLACEMENT 14 Int BE Pri !#4 N7078 P2006 MEMBAR !#4 N7079 P2007 BLD 20 -1 FP BE Pri !#4 N7080 P2008 MEMBAR !#4 N7081 P2009 PREFETCH 30 Int BE Sec !#4 N7082 P2010 MEMBAR !#4 N7083 P2011 BLD 14 -1 FP BE Pri !#4 N7084 P2012 MEMBAR !#4 N7085 P2013 BST 31 0x4180003a FP BE Pri !#4 N7086 P2014 MEMBAR !#4 N7087 P2015 BLD 0 -1 FP BE Pri !#4 N7088 P2015 BLD 1 -1 FP BE Pri !#A N7087 N7088 !#4 N7089 P2015 BLD 2 -1 FP BE Pri !#4 N7090 P2015 BLD 3 -1 FP BE Pri !#4 N7091 P2015 BLD 4 -1 FP BE Pri !#4 N7092 P2016 MEMBAR !#4 N7093 P2017 BST 24 0x4180003b FP BE Pri !#4 N7094 P2017 BST 25 0x4180003c FP BE Pri !#4 N7095 P2018 MEMBAR !#4 N7096 P2019 BLD 26 -1 FP BE Sec !#4 N7097 P2019 BLD 27 -1 FP BE Sec !#4 N7098 P2020 MEMBAR !#4 N7099 P2021 PREFETCH 19 Int BE Pri !#4 N7100 P2022 REPLACEMENT 26 Int BE Pri !#4 N7101 P2023 LD 3 -1 Int BE Sec !#4 N7102 P2024 MEMBAR !#4 N7103 P2025 BLD 30 -1 FP BE Pri !#4 N7104 P2026 MEMBAR !#4 N7105 P2027 BLD 24 -1 FP BE Pri !#4 N7106 P2027 BLD 25 -1 FP BE Pri !#4 N7107 P2028 MEMBAR !#4 N7108 P2029 BLD 5 -1 FP BE Pri !#4 N7109 P2029 BLD 6 -1 FP BE Pri !#4 N7110 P2030 MEMBAR !#4 N7111 P2031 REPLACEMENT 5 Int BE Nuc !#4 N7112 P2032 LD 16 -1 FP BE Sec !#4 N7113 P2033 REPLACEMENT 22 Int BE Pri !#4 N7114 P2034 ST 18 0x2000008 Int BE Sec !#4 N7115 P2035 ST 24 0x2000009 Int LE Nuc !#4 N7116 P2036 MEMBAR !#4 N7117 P2037 BLD 26 -1 FP BE Pri !#4 N7118 P2037 BLD 27 -1 FP BE Pri !#4 N7119 P2038 MEMBAR !#4 N7120 P2039 BLD 0 -1 FP BE Pri !#4 N7121 P2039 BLD 1 -1 FP BE Pri !#A N7120 N7121 !#4 N7122 P2039 BLD 2 -1 FP BE Pri !#4 N7123 P2039 BLD 3 -1 FP BE Pri !#4 N7124 P2039 BLD 4 -1 FP BE Pri !#4 N7125 P2040 MEMBAR !#4 N7126 P2041 IDC_FLIP 22 Int BE Pri !#4 N7127 P2042 MEMBAR !#4 N7128 P2043 BLD 11 -1 FP BE Pri !#4 N7129 P2043 BLD 12 -1 FP BE Pri !#A N7128 N7129 !#4 N7130 P2043 BLD 13 -1 FP BE Pri !#4 N7131 P2044 MEMBAR !#4 N7132 P2045 BLD 26 -1 FP BE Pri !#4 N7133 P2045 BLD 27 -1 FP BE Pri !#4 N7134 P2046 MEMBAR !#4 N7135 P2047 PREFETCH 4 Int BE Pri !#4 N7136 P2048 MEMBAR !#4 N7137 P2049 BLD 5 -1 FP BE Pri !#4 N7138 P2049 BLD 6 -1 FP BE Pri !#4 N7139 P2050 MEMBAR !#4 N7140 P2051 BLD 26 -1 FP BE Pri !#4 N7141 P2051 BLD 27 -1 FP BE Pri !#4 N7142 P2052 MEMBAR !#4 N7143 P2053 BLD 28 -1 FP BE Pri !#4 N7144 P2054 MEMBAR !#4 N7145 P2055 REPLACEMENT 9 Int BE Pri !#4 N7146 P2056 REPLACEMENT 3 Int BE Pri !#4 N7147 P2057 ST 13 0x200000a Int BE Pri !#4 N7148 P2058 MEMBAR !#4 N7149 P2059 BSTC 24 0x4180003d FP BE Sec !#4 N7150 P2059 BSTC 25 0x4180003e FP BE Sec !#4 N7151 P2060 MEMBAR !#4 N7152 P2061 LD 22 -1 Int BE Sec !#4 N7153 P2062 MEMBAR !#4 N7154 P2063 BLD 10 -1 FP BE Sec !#4 N7155 P2064 MEMBAR !#4 N7156 P2065 REPLACEMENT 2 Int BE Pri !#4 N7157 P2066 PREFETCH 17 Int BE Pri !#4 N7158 P2067 REPLACEMENT 17 Int BE Pri !#4 N7159 P2068 ST 29 0x200000b Int LE Pri !#4 N7160 P2069 MEMBAR !#4 N7161 P2070 BLD 17 -1 FP BE Pri !#4 N7162 P2071 MEMBAR !#4 N7163 P2072 BLD 21 -1 FP BE Pri !#4 N7164 P2072 BLD 22 -1 FP BE Pri !#A N7163 N7164 !#4 N7165 P2072 BLD 23 -1 FP BE Pri !#4 N7166 P2073 MEMBAR !#4 N7167 P2074 LD 14 -1 Int BE Pri !#4 N7168 P2075 REPLACEMENT 6 Int BE Pri !#4 N7169 P2076 MEMBAR !#4 N7170 P2077 BST 24 0x4180003f FP BE Pri !#4 N7171 P2077 BST 25 0x41800040 FP BE Pri !#4 N7172 P2078 MEMBAR !#4 N7173 P2079 BLD 20 -1 FP BE Pri !#4 N7174 P2080 MEMBAR !#4 N7175 P2081 BLD 21 -1 FP BE Sec !#4 N7176 P2081 BLD 22 -1 FP BE Sec !#A N7175 N7176 !#4 N7177 P2081 BLD 23 -1 FP BE Sec !#4 N7178 P2082 MEMBAR !#4 N7179 P2083 LD 32 -1 FP BE Pri !#4 N7180 P2084 MEMBAR !#4 N7181 P2085 BSTC 8 0x41800041 FP BE Pri !#4 N7182 P2085 BSTC 9 0x41800042 FP BE Pri !#4 N7183 P2086 MEMBAR !#4 N7184 P2087 BLD 20 -1 FP BE Pri !#4 N7185 P2088 MEMBAR !#4 N7186 P2089 LD 27 -1 FP BE Pri !#4 N7187 P2090 MEMBAR !#4 N7188 P2091 BLD 29 -1 FP BE Sec !#4 N7189 P2092 MEMBAR !#4 N7190 P2093 BLD 7 -1 FP BE Sec !#4 N7191 P2094 MEMBAR !#4 N7192 P2095 BLD 21 -1 FP BE Sec !#4 N7193 P2095 BLD 22 -1 FP BE Sec !#A N7192 N7193 !#4 N7194 P2095 BLD 23 -1 FP BE Sec !#4 N7195 P2096 MEMBAR !#4 N7196 P2097 LD 6 -1 FP BE Sec !#4 N7197 P2098 LD 8 -1 Int BE Pri !#4 N7198 P2099 MEMBAR !#4 N7199 P2100 BLD 8 -1 FP BE Pri !#4 N7200 P2100 BLD 9 -1 FP BE Pri !#4 N7201 P2101 MEMBAR !#4 N7202 P2102 BLD 21 -1 FP BE Pri !#4 N7203 P2102 BLD 22 -1 FP BE Pri !#A N7202 N7203 !#4 N7204 P2102 BLD 23 -1 FP BE Pri !#4 N7205 P2103 MEMBAR !#4 N7206 P2104 REPLACEMENT 23 Int BE Sec !#4 N7207 P2105 ST 26 0x41800043 FP BE Pri !#4 N7208 P2106 REPLACEMENT 6 Int BE Pri !#4 N7209 P2107 LD 27 -1 FP BE Nuc !#4 N7210 P2108 LD 21 -1 FP BE Pri !#4 N7211 P2109 MEMBAR !#4 N7212 P2110 BST 26 0x41800044 FP BE Pri !#4 N7213 P2110 BST 27 0x41800045 FP BE Pri !#4 N7214 P2111 MEMBAR !#4 N7215 P2112 ST 14 0x200000c Int BE Nuc !#4 N7216 P2113 REPLACEMENT 2 Int BE Pri !#4 N7217 P2114 REPLACEMENT 16 Int BE Pri !#4 N7218 P2115 REPLACEMENT 24 Int BE Pri !#4 N7219 P2116 REPLACEMENT 24 Int BE Pri !#4 N7220 P2117 REPLACEMENT 23 Int BE Pri !#4 N7221 P2118 MEMBAR !#4 N7222 P2119 BSTC 33 0x41800046 FP BE Pri !#4 N7223 P2120 MEMBAR !#4 N7224 P2121 PREFETCH 19 Int BE Pri !#4 N7225 P2122 LD 0 -1 Int BE Pri Loop_exit !#4 N7226 P1943 MEMBAR !#4 N7227 P1944 BST 5 0x41800047 FP BE Pri !#4 N7228 P1944 BST 6 0x41800048 FP BE Pri !#4 N7229 P1945 MEMBAR !#4 N7230 P1946 LD 29 -1 FP BE Pri !#4 N7231 P1947 ST 26 0x200000d Int BE Pri !#4 N7232 P1948 ST 14 0x41800049 FP BE Pri !#4 N7233 P1949 MEMBAR !#4 N7234 P1950 REPLACEMENT 4 Int BE Pri !#4 N7235 P1951 MEMBAR !#4 N7236 P1952 BLD 11 -1 FP BE Pri !#4 N7237 P1952 BLD 12 -1 FP BE Pri !#A N7236 N7237 !#4 N7238 P1952 BLD 13 -1 FP BE Pri !#4 N7239 P1953 MEMBAR !#4 N7240 P1954 BST 33 0x4180004a FP BE Pri !#4 N7241 P1955 MEMBAR !#4 N7242 P1956 REPLACEMENT 28 Int BE Nuc !#4 N7243 P1957 PREFETCH 27 Int BE Pri !#4 N7244 P1958 REPLACEMENT 26 Int BE Pri !#4 N7245 P1959 MEMBAR !#4 N7246 P1960 BST 11 0x4180004b FP BE Sec !#4 N7247 P1960 BST 12 0x4180004c FP BE Sec !#A N7246 N7247 !#4 N7248 P1960 BST 13 0x4180004d FP BE Sec !#4 N7249 P1961 MEMBAR !#4 N7250 P1962 REPLACEMENT 1 Int BE Pri !#4 N7251 P1963 MEMBAR !#4 N7252 P1964 BSTC 5 0x4180004e FP BE Sec !#4 N7253 P1964 BSTC 6 0x4180004f FP BE Sec !#4 N7254 P1965 MEMBAR !#4 N7255 P1966 BSTC 26 0x41800050 FP BE Pri !#4 N7256 P1966 BSTC 27 0x41800051 FP BE Pri !#4 N7257 P1967 MEMBAR !#4 N7258 P1968 LD 9 -1 Int BE Pri !#4 N7259 P1969 MEMBAR !#4 N7260 P1970 BLD 5 -1 FP BE Pri !#4 N7261 P1970 BLD 6 -1 FP BE Pri !#4 N7262 P1971 MEMBAR !#4 N7263 P1972 BST 15 0x41800052 FP BE Pri !#4 N7264 P1973 MEMBAR !#4 N7265 P1974 BLD 24 -1 FP BE Pri !#4 N7266 P1974 BLD 25 -1 FP BE Pri !#4 N7267 P1975 MEMBAR !#4 N7268 P1976 REPLACEMENT 24 Int BE Pri !#4 N7269 P1977 MEMBAR !#4 N7270 P1978 BST 20 0x41800053 FP BE Pri !#4 N7271 P1979 MEMBAR !#4 N7272 P1980 PREFETCH 30 Int BE Pri !#4 N7273 P1981 MEMBAR !#4 N7274 P1982 BLD 11 -1 FP BE Pri !#4 N7275 P1982 BLD 12 -1 FP BE Pri !#A N7274 N7275 !#4 N7276 P1982 BLD 13 -1 FP BE Pri !#4 N7277 P1983 MEMBAR !#4 N7278 P1984 BSTC 17 0x41800054 FP BE Pri !#4 N7279 P1985 MEMBAR !#4 N7280 P1986 BSTC 11 0x41800055 FP BE Pri !#4 N7281 P1986 BSTC 12 0x41800056 FP BE Pri !#A N7280 N7281 !#4 N7282 P1986 BSTC 13 0x41800057 FP BE Pri !#4 N7283 P1987 MEMBAR !#4 N7284 P1988 ST 27 0x41800058 FP BE Sec !#4 N7285 P1989 MEMBAR !#4 N7286 P1990 BLD 10 -1 FP BE Pri !#4 N7287 P1991 MEMBAR !#4 N7288 P1992 BLD 20 -1 FP BE Pri !#4 N7289 P1993 MEMBAR !#4 N7290 P1994 REPLACEMENT 32 Int BE Pri !#4 N7291 P1995 ST 8 0x41800059 FP BE Pri !#4 N7292 P1996 MEMBAR !#4 N7293 P1997 BSTC 15 0x4180005a FP BE Pri !#4 N7294 P1998 MEMBAR !#4 N7295 P1999 ST 10 0x4180005b FP BE Pri !#4 N7296 P2000 PREFETCH 30 Int BE Pri !#4 N7297 P2001 REPLACEMENT 31 Int BE Pri !#4 N7298 P2002 MEMBAR !#4 N7299 P2003 BSTC 7 0x4180005c FP BE Pri !#4 N7300 P2004 MEMBAR !#4 N7301 P2005 REPLACEMENT 14 Int BE Pri !#4 N7302 P2006 MEMBAR !#4 N7303 P2007 BLD 20 -1 FP BE Pri !#4 N7304 P2008 MEMBAR !#4 N7305 P2009 PREFETCH 30 Int BE Sec !#4 N7306 P2010 MEMBAR !#4 N7307 P2011 BLD 14 -1 FP BE Pri !#4 N7308 P2012 MEMBAR !#4 N7309 P2013 BST 31 0x4180005d FP BE Pri !#4 N7310 P2014 MEMBAR !#4 N7311 P2015 BLD 0 -1 FP BE Pri !#4 N7312 P2015 BLD 1 -1 FP BE Pri !#A N7311 N7312 !#4 N7313 P2015 BLD 2 -1 FP BE Pri !#4 N7314 P2015 BLD 3 -1 FP BE Pri !#4 N7315 P2015 BLD 4 -1 FP BE Pri !#4 N7316 P2016 MEMBAR !#4 N7317 P2017 BST 24 0x4180005e FP BE Pri !#4 N7318 P2017 BST 25 0x4180005f FP BE Pri !#4 N7319 P2018 MEMBAR !#4 N7320 P2019 BLD 26 -1 FP BE Sec !#4 N7321 P2019 BLD 27 -1 FP BE Sec !#4 N7322 P2020 MEMBAR !#4 N7323 P2021 PREFETCH 19 Int BE Pri !#4 N7324 P2022 REPLACEMENT 26 Int BE Pri !#4 N7325 P2023 LD 3 -1 Int BE Sec !#4 N7326 P2024 MEMBAR !#4 N7327 P2025 BLD 30 -1 FP BE Pri !#4 N7328 P2026 MEMBAR !#4 N7329 P2027 BLD 24 -1 FP BE Pri !#4 N7330 P2027 BLD 25 -1 FP BE Pri !#4 N7331 P2028 MEMBAR !#4 N7332 P2029 BLD 5 -1 FP BE Pri !#4 N7333 P2029 BLD 6 -1 FP BE Pri !#4 N7334 P2030 MEMBAR !#4 N7335 P2031 REPLACEMENT 5 Int BE Nuc !#4 N7336 P2032 LD 16 -1 FP BE Sec !#4 N7337 P2033 REPLACEMENT 22 Int BE Pri !#4 N7338 P2034 ST 18 0x200000e Int BE Sec !#4 N7339 P2035 ST 24 0x200000f Int LE Nuc !#4 N7340 P2036 MEMBAR !#4 N7341 P2037 BLD 26 -1 FP BE Pri !#4 N7342 P2037 BLD 27 -1 FP BE Pri !#4 N7343 P2038 MEMBAR !#4 N7344 P2039 BLD 0 -1 FP BE Pri !#4 N7345 P2039 BLD 1 -1 FP BE Pri !#A N7344 N7345 !#4 N7346 P2039 BLD 2 -1 FP BE Pri !#4 N7347 P2039 BLD 3 -1 FP BE Pri !#4 N7348 P2039 BLD 4 -1 FP BE Pri !#4 N7349 P2040 MEMBAR !#4 N7350 P2041 IDC_FLIP 22 Int BE Pri !#4 N7351 P2042 MEMBAR !#4 N7352 P2043 BLD 11 -1 FP BE Pri !#4 N7353 P2043 BLD 12 -1 FP BE Pri !#A N7352 N7353 !#4 N7354 P2043 BLD 13 -1 FP BE Pri !#4 N7355 P2044 MEMBAR !#4 N7356 P2045 BLD 26 -1 FP BE Pri !#4 N7357 P2045 BLD 27 -1 FP BE Pri !#4 N7358 P2046 MEMBAR !#4 N7359 P2047 PREFETCH 4 Int BE Pri !#4 N7360 P2048 MEMBAR !#4 N7361 P2049 BLD 5 -1 FP BE Pri !#4 N7362 P2049 BLD 6 -1 FP BE Pri !#4 N7363 P2050 MEMBAR !#4 N7364 P2051 BLD 26 -1 FP BE Pri !#4 N7365 P2051 BLD 27 -1 FP BE Pri !#4 N7366 P2052 MEMBAR !#4 N7367 P2053 BLD 28 -1 FP BE Pri !#4 N7368 P2054 MEMBAR !#4 N7369 P2055 REPLACEMENT 9 Int BE Pri !#4 N7370 P2056 REPLACEMENT 3 Int BE Pri !#4 N7371 P2057 ST 13 0x2000010 Int BE Pri !#4 N7372 P2058 MEMBAR !#4 N7373 P2059 BSTC 24 0x41800060 FP BE Sec !#4 N7374 P2059 BSTC 25 0x41800061 FP BE Sec !#4 N7375 P2060 MEMBAR !#4 N7376 P2061 LD 22 -1 Int BE Sec !#4 N7377 P2062 MEMBAR !#4 N7378 P2063 BLD 10 -1 FP BE Sec !#4 N7379 P2064 MEMBAR !#4 N7380 P2065 REPLACEMENT 2 Int BE Pri !#4 N7381 P2066 PREFETCH 17 Int BE Pri !#4 N7382 P2067 REPLACEMENT 17 Int BE Pri !#4 N7383 P2068 ST 29 0x2000011 Int LE Pri !#4 N7384 P2069 MEMBAR !#4 N7385 P2070 BLD 17 -1 FP BE Pri !#4 N7386 P2071 MEMBAR !#4 N7387 P2072 BLD 21 -1 FP BE Pri !#4 N7388 P2072 BLD 22 -1 FP BE Pri !#A N7387 N7388 !#4 N7389 P2072 BLD 23 -1 FP BE Pri !#4 N7390 P2073 MEMBAR !#4 N7391 P2074 LD 14 -1 Int BE Pri !#4 N7392 P2075 REPLACEMENT 6 Int BE Pri !#4 N7393 P2076 MEMBAR !#4 N7394 P2077 BST 24 0x41800062 FP BE Pri !#4 N7395 P2077 BST 25 0x41800063 FP BE Pri !#4 N7396 P2078 MEMBAR !#4 N7397 P2079 BLD 20 -1 FP BE Pri !#4 N7398 P2080 MEMBAR !#4 N7399 P2081 BLD 21 -1 FP BE Sec !#4 N7400 P2081 BLD 22 -1 FP BE Sec !#A N7399 N7400 !#4 N7401 P2081 BLD 23 -1 FP BE Sec !#4 N7402 P2082 MEMBAR !#4 N7403 P2083 LD 32 -1 FP BE Pri !#4 N7404 P2084 MEMBAR !#4 N7405 P2085 BSTC 8 0x41800064 FP BE Pri !#4 N7406 P2085 BSTC 9 0x41800065 FP BE Pri !#4 N7407 P2086 MEMBAR !#4 N7408 P2087 BLD 20 -1 FP BE Pri !#4 N7409 P2088 MEMBAR !#4 N7410 P2089 LD 27 -1 FP BE Pri !#4 N7411 P2090 MEMBAR !#4 N7412 P2091 BLD 29 -1 FP BE Sec !#4 N7413 P2092 MEMBAR !#4 N7414 P2093 BLD 7 -1 FP BE Sec !#4 N7415 P2094 MEMBAR !#4 N7416 P2095 BLD 21 -1 FP BE Sec !#4 N7417 P2095 BLD 22 -1 FP BE Sec !#A N7416 N7417 !#4 N7418 P2095 BLD 23 -1 FP BE Sec !#4 N7419 P2096 MEMBAR !#4 N7420 P2097 LD 6 -1 FP BE Sec !#4 N7421 P2098 LD 8 -1 Int BE Pri !#4 N7422 P2099 MEMBAR !#4 N7423 P2100 BLD 8 -1 FP BE Pri !#4 N7424 P2100 BLD 9 -1 FP BE Pri !#4 N7425 P2101 MEMBAR !#4 N7426 P2102 BLD 21 -1 FP BE Pri !#4 N7427 P2102 BLD 22 -1 FP BE Pri !#A N7426 N7427 !#4 N7428 P2102 BLD 23 -1 FP BE Pri !#4 N7429 P2103 MEMBAR !#4 N7430 P2104 REPLACEMENT 23 Int BE Sec !#4 N7431 P2105 ST 26 0x41800066 FP BE Pri !#4 N7432 P2106 REPLACEMENT 6 Int BE Pri !#4 N7433 P2107 LD 27 -1 FP BE Nuc !#4 N7434 P2108 LD 21 -1 FP BE Pri !#4 N7435 P2109 MEMBAR !#4 N7436 P2110 BST 26 0x41800067 FP BE Pri !#4 N7437 P2110 BST 27 0x41800068 FP BE Pri !#4 N7438 P2111 MEMBAR !#4 N7439 P2112 ST 14 0x2000012 Int BE Nuc !#4 N7440 P2113 REPLACEMENT 2 Int BE Pri !#4 N7441 P2114 REPLACEMENT 16 Int BE Pri !#4 N7442 P2115 REPLACEMENT 24 Int BE Pri !#4 N7443 P2116 REPLACEMENT 24 Int BE Pri !#4 N7444 P2117 REPLACEMENT 23 Int BE Pri !#4 N7445 P2118 MEMBAR !#4 N7446 P2119 BSTC 33 0x41800069 FP BE Pri !#4 N7447 P2120 MEMBAR !#4 N7448 P2121 PREFETCH 19 Int BE Pri !#4 N7449 P2122 LD 0 -1 Int BE Pri Loop_exit !#4 N7450 P1943 MEMBAR !#4 N7451 P1944 BST 5 0x4180006a FP BE Pri !#4 N7452 P1944 BST 6 0x4180006b FP BE Pri !#4 N7453 P1945 MEMBAR !#4 N7454 P1946 LD 29 -1 FP BE Pri !#4 N7455 P1947 ST 26 0x2000013 Int BE Pri !#4 N7456 P1948 ST 14 0x4180006c FP BE Pri !#4 N7457 P1949 MEMBAR !#4 N7458 P1950 REPLACEMENT 4 Int BE Pri !#4 N7459 P1951 MEMBAR !#4 N7460 P1952 BLD 11 -1 FP BE Pri !#4 N7461 P1952 BLD 12 -1 FP BE Pri !#A N7460 N7461 !#4 N7462 P1952 BLD 13 -1 FP BE Pri !#4 N7463 P1953 MEMBAR !#4 N7464 P1954 BST 33 0x4180006d FP BE Pri !#4 N7465 P1955 MEMBAR !#4 N7466 P1956 REPLACEMENT 28 Int BE Nuc !#4 N7467 P1957 PREFETCH 27 Int BE Pri !#4 N7468 P1958 REPLACEMENT 26 Int BE Pri !#4 N7469 P1959 MEMBAR !#4 N7470 P1960 BST 11 0x4180006e FP BE Sec !#4 N7471 P1960 BST 12 0x4180006f FP BE Sec !#A N7470 N7471 !#4 N7472 P1960 BST 13 0x41800070 FP BE Sec !#4 N7473 P1961 MEMBAR !#4 N7474 P1962 REPLACEMENT 1 Int BE Pri !#4 N7475 P1963 MEMBAR !#4 N7476 P1964 BSTC 5 0x41800071 FP BE Sec !#4 N7477 P1964 BSTC 6 0x41800072 FP BE Sec !#4 N7478 P1965 MEMBAR !#4 N7479 P1966 BSTC 26 0x41800073 FP BE Pri !#4 N7480 P1966 BSTC 27 0x41800074 FP BE Pri !#4 N7481 P1967 MEMBAR !#4 N7482 P1968 LD 9 -1 Int BE Pri !#4 N7483 P1969 MEMBAR !#4 N7484 P1970 BLD 5 -1 FP BE Pri !#4 N7485 P1970 BLD 6 -1 FP BE Pri !#4 N7486 P1971 MEMBAR !#4 N7487 P1972 BST 15 0x41800075 FP BE Pri !#4 N7488 P1973 MEMBAR !#4 N7489 P1974 BLD 24 -1 FP BE Pri !#4 N7490 P1974 BLD 25 -1 FP BE Pri !#4 N7491 P1975 MEMBAR !#4 N7492 P1976 REPLACEMENT 24 Int BE Pri !#4 N7493 P1977 MEMBAR !#4 N7494 P1978 BST 20 0x41800076 FP BE Pri !#4 N7495 P1979 MEMBAR !#4 N7496 P1980 PREFETCH 30 Int BE Pri !#4 N7497 P1981 MEMBAR !#4 N7498 P1982 BLD 11 -1 FP BE Pri !#4 N7499 P1982 BLD 12 -1 FP BE Pri !#A N7498 N7499 !#4 N7500 P1982 BLD 13 -1 FP BE Pri !#4 N7501 P1983 MEMBAR !#4 N7502 P1984 BSTC 17 0x41800077 FP BE Pri !#4 N7503 P1985 MEMBAR !#4 N7504 P1986 BSTC 11 0x41800078 FP BE Pri !#4 N7505 P1986 BSTC 12 0x41800079 FP BE Pri !#A N7504 N7505 !#4 N7506 P1986 BSTC 13 0x4180007a FP BE Pri !#4 N7507 P1987 MEMBAR !#4 N7508 P1988 ST 27 0x4180007b FP BE Sec !#4 N7509 P1989 MEMBAR !#4 N7510 P1990 BLD 10 -1 FP BE Pri !#4 N7511 P1991 MEMBAR !#4 N7512 P1992 BLD 20 -1 FP BE Pri !#4 N7513 P1993 MEMBAR !#4 N7514 P1994 REPLACEMENT 32 Int BE Pri !#4 N7515 P1995 ST 8 0x4180007c FP BE Pri !#4 N7516 P1996 MEMBAR !#4 N7517 P1997 BSTC 15 0x4180007d FP BE Pri !#4 N7518 P1998 MEMBAR !#4 N7519 P1999 ST 10 0x4180007e FP BE Pri !#4 N7520 P2000 PREFETCH 30 Int BE Pri !#4 N7521 P2001 REPLACEMENT 31 Int BE Pri !#4 N7522 P2002 MEMBAR !#4 N7523 P2003 BSTC 7 0x4180007f FP BE Pri !#4 N7524 P2004 MEMBAR !#4 N7525 P2005 REPLACEMENT 14 Int BE Pri !#4 N7526 P2006 MEMBAR !#4 N7527 P2007 BLD 20 -1 FP BE Pri !#4 N7528 P2008 MEMBAR !#4 N7529 P2009 PREFETCH 30 Int BE Sec !#4 N7530 P2010 MEMBAR !#4 N7531 P2011 BLD 14 -1 FP BE Pri !#4 N7532 P2012 MEMBAR !#4 N7533 P2013 BST 31 0x41800080 FP BE Pri !#4 N7534 P2014 MEMBAR !#4 N7535 P2015 BLD 0 -1 FP BE Pri !#4 N7536 P2015 BLD 1 -1 FP BE Pri !#A N7535 N7536 !#4 N7537 P2015 BLD 2 -1 FP BE Pri !#4 N7538 P2015 BLD 3 -1 FP BE Pri !#4 N7539 P2015 BLD 4 -1 FP BE Pri !#4 N7540 P2016 MEMBAR !#4 N7541 P2017 BST 24 0x41800081 FP BE Pri !#4 N7542 P2017 BST 25 0x41800082 FP BE Pri !#4 N7543 P2018 MEMBAR !#4 N7544 P2019 BLD 26 -1 FP BE Sec !#4 N7545 P2019 BLD 27 -1 FP BE Sec !#4 N7546 P2020 MEMBAR !#4 N7547 P2021 PREFETCH 19 Int BE Pri !#4 N7548 P2022 REPLACEMENT 26 Int BE Pri !#4 N7549 P2023 LD 3 -1 Int BE Sec !#4 N7550 P2024 MEMBAR !#4 N7551 P2025 BLD 30 -1 FP BE Pri !#4 N7552 P2026 MEMBAR !#4 N7553 P2027 BLD 24 -1 FP BE Pri !#4 N7554 P2027 BLD 25 -1 FP BE Pri !#4 N7555 P2028 MEMBAR !#4 N7556 P2029 BLD 5 -1 FP BE Pri !#4 N7557 P2029 BLD 6 -1 FP BE Pri !#4 N7558 P2030 MEMBAR !#4 N7559 P2031 REPLACEMENT 5 Int BE Nuc !#4 N7560 P2032 LD 16 -1 FP BE Sec !#4 N7561 P2033 REPLACEMENT 22 Int BE Pri !#4 N7562 P2034 ST 18 0x2000014 Int BE Sec !#4 N7563 P2035 ST 24 0x2000015 Int LE Nuc !#4 N7564 P2036 MEMBAR !#4 N7565 P2037 BLD 26 -1 FP BE Pri !#4 N7566 P2037 BLD 27 -1 FP BE Pri !#4 N7567 P2038 MEMBAR !#4 N7568 P2039 BLD 0 -1 FP BE Pri !#4 N7569 P2039 BLD 1 -1 FP BE Pri !#A N7568 N7569 !#4 N7570 P2039 BLD 2 -1 FP BE Pri !#4 N7571 P2039 BLD 3 -1 FP BE Pri !#4 N7572 P2039 BLD 4 -1 FP BE Pri !#4 N7573 P2040 MEMBAR !#4 N7574 P2041 IDC_FLIP 22 Int BE Pri !#4 N7575 P2042 MEMBAR !#4 N7576 P2043 BLD 11 -1 FP BE Pri !#4 N7577 P2043 BLD 12 -1 FP BE Pri !#A N7576 N7577 !#4 N7578 P2043 BLD 13 -1 FP BE Pri !#4 N7579 P2044 MEMBAR !#4 N7580 P2045 BLD 26 -1 FP BE Pri !#4 N7581 P2045 BLD 27 -1 FP BE Pri !#4 N7582 P2046 MEMBAR !#4 N7583 P2047 PREFETCH 4 Int BE Pri !#4 N7584 P2048 MEMBAR !#4 N7585 P2049 BLD 5 -1 FP BE Pri !#4 N7586 P2049 BLD 6 -1 FP BE Pri !#4 N7587 P2050 MEMBAR !#4 N7588 P2051 BLD 26 -1 FP BE Pri !#4 N7589 P2051 BLD 27 -1 FP BE Pri !#4 N7590 P2052 MEMBAR !#4 N7591 P2053 BLD 28 -1 FP BE Pri !#4 N7592 P2054 MEMBAR !#4 N7593 P2055 REPLACEMENT 9 Int BE Pri !#4 N7594 P2056 REPLACEMENT 3 Int BE Pri !#4 N7595 P2057 ST 13 0x2000016 Int BE Pri !#4 N7596 P2058 MEMBAR !#4 N7597 P2059 BSTC 24 0x41800083 FP BE Sec !#4 N7598 P2059 BSTC 25 0x41800084 FP BE Sec !#4 N7599 P2060 MEMBAR !#4 N7600 P2061 LD 22 -1 Int BE Sec !#4 N7601 P2062 MEMBAR !#4 N7602 P2063 BLD 10 -1 FP BE Sec !#4 N7603 P2064 MEMBAR !#4 N7604 P2065 REPLACEMENT 2 Int BE Pri !#4 N7605 P2066 PREFETCH 17 Int BE Pri !#4 N7606 P2067 REPLACEMENT 17 Int BE Pri !#4 N7607 P2068 ST 29 0x2000017 Int LE Pri !#4 N7608 P2069 MEMBAR !#4 N7609 P2070 BLD 17 -1 FP BE Pri !#4 N7610 P2071 MEMBAR !#4 N7611 P2072 BLD 21 -1 FP BE Pri !#4 N7612 P2072 BLD 22 -1 FP BE Pri !#A N7611 N7612 !#4 N7613 P2072 BLD 23 -1 FP BE Pri !#4 N7614 P2073 MEMBAR !#4 N7615 P2074 LD 14 -1 Int BE Pri !#4 N7616 P2075 REPLACEMENT 6 Int BE Pri !#4 N7617 P2076 MEMBAR !#4 N7618 P2077 BST 24 0x41800085 FP BE Pri !#4 N7619 P2077 BST 25 0x41800086 FP BE Pri !#4 N7620 P2078 MEMBAR !#4 N7621 P2079 BLD 20 -1 FP BE Pri !#4 N7622 P2080 MEMBAR !#4 N7623 P2081 BLD 21 -1 FP BE Sec !#4 N7624 P2081 BLD 22 -1 FP BE Sec !#A N7623 N7624 !#4 N7625 P2081 BLD 23 -1 FP BE Sec !#4 N7626 P2082 MEMBAR !#4 N7627 P2083 LD 32 -1 FP BE Pri !#4 N7628 P2084 MEMBAR !#4 N7629 P2085 BSTC 8 0x41800087 FP BE Pri !#4 N7630 P2085 BSTC 9 0x41800088 FP BE Pri !#4 N7631 P2086 MEMBAR !#4 N7632 P2087 BLD 20 -1 FP BE Pri !#4 N7633 P2088 MEMBAR !#4 N7634 P2089 LD 27 -1 FP BE Pri !#4 N7635 P2090 MEMBAR !#4 N7636 P2091 BLD 29 -1 FP BE Sec !#4 N7637 P2092 MEMBAR !#4 N7638 P2093 BLD 7 -1 FP BE Sec !#4 N7639 P2094 MEMBAR !#4 N7640 P2095 BLD 21 -1 FP BE Sec !#4 N7641 P2095 BLD 22 -1 FP BE Sec !#A N7640 N7641 !#4 N7642 P2095 BLD 23 -1 FP BE Sec !#4 N7643 P2096 MEMBAR !#4 N7644 P2097 LD 6 -1 FP BE Sec !#4 N7645 P2098 LD 8 -1 Int BE Pri !#4 N7646 P2099 MEMBAR !#4 N7647 P2100 BLD 8 -1 FP BE Pri !#4 N7648 P2100 BLD 9 -1 FP BE Pri !#4 N7649 P2101 MEMBAR !#4 N7650 P2102 BLD 21 -1 FP BE Pri !#4 N7651 P2102 BLD 22 -1 FP BE Pri !#A N7650 N7651 !#4 N7652 P2102 BLD 23 -1 FP BE Pri !#4 N7653 P2103 MEMBAR !#4 N7654 P2104 REPLACEMENT 23 Int BE Sec !#4 N7655 P2105 ST 26 0x41800089 FP BE Pri !#4 N7656 P2106 REPLACEMENT 6 Int BE Pri !#4 N7657 P2107 LD 27 -1 FP BE Nuc !#4 N7658 P2108 LD 21 -1 FP BE Pri !#4 N7659 P2109 MEMBAR !#4 N7660 P2110 BST 26 0x4180008a FP BE Pri !#4 N7661 P2110 BST 27 0x4180008b FP BE Pri !#4 N7662 P2111 MEMBAR !#4 N7663 P2112 ST 14 0x2000018 Int BE Nuc !#4 N7664 P2113 REPLACEMENT 2 Int BE Pri !#4 N7665 P2114 REPLACEMENT 16 Int BE Pri !#4 N7666 P2115 REPLACEMENT 24 Int BE Pri !#4 N7667 P2116 REPLACEMENT 24 Int BE Pri !#4 N7668 P2117 REPLACEMENT 23 Int BE Pri !#4 N7669 P2118 MEMBAR !#4 N7670 P2119 BSTC 33 0x4180008c FP BE Pri !#4 N7671 P2120 MEMBAR !#4 N7672 P2121 PREFETCH 19 Int BE Pri !#4 N7673 P2122 LD 0 -1 Int BE Pri Loop_exit !#4 N7674 P1943 MEMBAR !#4 N7675 P1944 BST 5 0x4180008d FP BE Pri !#4 N7676 P1944 BST 6 0x4180008e FP BE Pri !#4 N7677 P1945 MEMBAR !#4 N7678 P1946 LD 29 -1 FP BE Pri !#4 N7679 P1947 ST 26 0x2000019 Int BE Pri !#4 N7680 P1948 ST 14 0x4180008f FP BE Pri !#4 N7681 P1949 MEMBAR !#4 N7682 P1950 REPLACEMENT 4 Int BE Pri !#4 N7683 P1951 MEMBAR !#4 N7684 P1952 BLD 11 -1 FP BE Pri !#4 N7685 P1952 BLD 12 -1 FP BE Pri !#A N7684 N7685 !#4 N7686 P1952 BLD 13 -1 FP BE Pri !#4 N7687 P1953 MEMBAR !#4 N7688 P1954 BST 33 0x41800090 FP BE Pri !#4 N7689 P1955 MEMBAR !#4 N7690 P1956 REPLACEMENT 28 Int BE Nuc !#4 N7691 P1957 PREFETCH 27 Int BE Pri !#4 N7692 P1958 REPLACEMENT 26 Int BE Pri !#4 N7693 P1959 MEMBAR !#4 N7694 P1960 BST 11 0x41800091 FP BE Sec !#4 N7695 P1960 BST 12 0x41800092 FP BE Sec !#A N7694 N7695 !#4 N7696 P1960 BST 13 0x41800093 FP BE Sec !#4 N7697 P1961 MEMBAR !#4 N7698 P1962 REPLACEMENT 1 Int BE Pri !#4 N7699 P1963 MEMBAR !#4 N7700 P1964 BSTC 5 0x41800094 FP BE Sec !#4 N7701 P1964 BSTC 6 0x41800095 FP BE Sec !#4 N7702 P1965 MEMBAR !#4 N7703 P1966 BSTC 26 0x41800096 FP BE Pri !#4 N7704 P1966 BSTC 27 0x41800097 FP BE Pri !#4 N7705 P1967 MEMBAR !#4 N7706 P1968 LD 9 -1 Int BE Pri !#4 N7707 P1969 MEMBAR !#4 N7708 P1970 BLD 5 -1 FP BE Pri !#4 N7709 P1970 BLD 6 -1 FP BE Pri !#4 N7710 P1971 MEMBAR !#4 N7711 P1972 BST 15 0x41800098 FP BE Pri !#4 N7712 P1973 MEMBAR !#4 N7713 P1974 BLD 24 -1 FP BE Pri !#4 N7714 P1974 BLD 25 -1 FP BE Pri !#4 N7715 P1975 MEMBAR !#4 N7716 P1976 REPLACEMENT 24 Int BE Pri !#4 N7717 P1977 MEMBAR !#4 N7718 P1978 BST 20 0x41800099 FP BE Pri !#4 N7719 P1979 MEMBAR !#4 N7720 P1980 PREFETCH 30 Int BE Pri !#4 N7721 P1981 MEMBAR !#4 N7722 P1982 BLD 11 -1 FP BE Pri !#4 N7723 P1982 BLD 12 -1 FP BE Pri !#A N7722 N7723 !#4 N7724 P1982 BLD 13 -1 FP BE Pri !#4 N7725 P1983 MEMBAR !#4 N7726 P1984 BSTC 17 0x4180009a FP BE Pri !#4 N7727 P1985 MEMBAR !#4 N7728 P1986 BSTC 11 0x4180009b FP BE Pri !#4 N7729 P1986 BSTC 12 0x4180009c FP BE Pri !#A N7728 N7729 !#4 N7730 P1986 BSTC 13 0x4180009d FP BE Pri !#4 N7731 P1987 MEMBAR !#4 N7732 P1988 ST 27 0x4180009e FP BE Sec !#4 N7733 P1989 MEMBAR !#4 N7734 P1990 BLD 10 -1 FP BE Pri !#4 N7735 P1991 MEMBAR !#4 N7736 P1992 BLD 20 -1 FP BE Pri !#4 N7737 P1993 MEMBAR !#4 N7738 P1994 REPLACEMENT 32 Int BE Pri !#4 N7739 P1995 ST 8 0x4180009f FP BE Pri !#4 N7740 P1996 MEMBAR !#4 N7741 P1997 BSTC 15 0x418000a0 FP BE Pri !#4 N7742 P1998 MEMBAR !#4 N7743 P1999 ST 10 0x418000a1 FP BE Pri !#4 N7744 P2000 PREFETCH 30 Int BE Pri !#4 N7745 P2001 REPLACEMENT 31 Int BE Pri !#4 N7746 P2002 MEMBAR !#4 N7747 P2003 BSTC 7 0x418000a2 FP BE Pri !#4 N7748 P2004 MEMBAR !#4 N7749 P2005 REPLACEMENT 14 Int BE Pri !#4 N7750 P2006 MEMBAR !#4 N7751 P2007 BLD 20 -1 FP BE Pri !#4 N7752 P2008 MEMBAR !#4 N7753 P2009 PREFETCH 30 Int BE Sec !#4 N7754 P2010 MEMBAR !#4 N7755 P2011 BLD 14 -1 FP BE Pri !#4 N7756 P2012 MEMBAR !#4 N7757 P2013 BST 31 0x418000a3 FP BE Pri !#4 N7758 P2014 MEMBAR !#4 N7759 P2015 BLD 0 -1 FP BE Pri !#4 N7760 P2015 BLD 1 -1 FP BE Pri !#A N7759 N7760 !#4 N7761 P2015 BLD 2 -1 FP BE Pri !#4 N7762 P2015 BLD 3 -1 FP BE Pri !#4 N7763 P2015 BLD 4 -1 FP BE Pri !#4 N7764 P2016 MEMBAR !#4 N7765 P2017 BST 24 0x418000a4 FP BE Pri !#4 N7766 P2017 BST 25 0x418000a5 FP BE Pri !#4 N7767 P2018 MEMBAR !#4 N7768 P2019 BLD 26 -1 FP BE Sec !#4 N7769 P2019 BLD 27 -1 FP BE Sec !#4 N7770 P2020 MEMBAR !#4 N7771 P2021 PREFETCH 19 Int BE Pri !#4 N7772 P2022 REPLACEMENT 26 Int BE Pri !#4 N7773 P2023 LD 3 -1 Int BE Sec !#4 N7774 P2024 MEMBAR !#4 N7775 P2025 BLD 30 -1 FP BE Pri !#4 N7776 P2026 MEMBAR !#4 N7777 P2027 BLD 24 -1 FP BE Pri !#4 N7778 P2027 BLD 25 -1 FP BE Pri !#4 N7779 P2028 MEMBAR !#4 N7780 P2029 BLD 5 -1 FP BE Pri !#4 N7781 P2029 BLD 6 -1 FP BE Pri !#4 N7782 P2030 MEMBAR !#4 N7783 P2031 REPLACEMENT 5 Int BE Nuc !#4 N7784 P2032 LD 16 -1 FP BE Sec !#4 N7785 P2033 REPLACEMENT 22 Int BE Pri !#4 N7786 P2034 ST 18 0x200001a Int BE Sec !#4 N7787 P2035 ST 24 0x200001b Int LE Nuc !#4 N7788 P2036 MEMBAR !#4 N7789 P2037 BLD 26 -1 FP BE Pri !#4 N7790 P2037 BLD 27 -1 FP BE Pri !#4 N7791 P2038 MEMBAR !#4 N7792 P2039 BLD 0 -1 FP BE Pri !#4 N7793 P2039 BLD 1 -1 FP BE Pri !#A N7792 N7793 !#4 N7794 P2039 BLD 2 -1 FP BE Pri !#4 N7795 P2039 BLD 3 -1 FP BE Pri !#4 N7796 P2039 BLD 4 -1 FP BE Pri !#4 N7797 P2040 MEMBAR !#4 N7798 P2041 IDC_FLIP 22 Int BE Pri !#4 N7799 P2042 MEMBAR !#4 N7800 P2043 BLD 11 -1 FP BE Pri !#4 N7801 P2043 BLD 12 -1 FP BE Pri !#A N7800 N7801 !#4 N7802 P2043 BLD 13 -1 FP BE Pri !#4 N7803 P2044 MEMBAR !#4 N7804 P2045 BLD 26 -1 FP BE Pri !#4 N7805 P2045 BLD 27 -1 FP BE Pri !#4 N7806 P2046 MEMBAR !#4 N7807 P2047 PREFETCH 4 Int BE Pri !#4 N7808 P2048 MEMBAR !#4 N7809 P2049 BLD 5 -1 FP BE Pri !#4 N7810 P2049 BLD 6 -1 FP BE Pri !#4 N7811 P2050 MEMBAR !#4 N7812 P2051 BLD 26 -1 FP BE Pri !#4 N7813 P2051 BLD 27 -1 FP BE Pri !#4 N7814 P2052 MEMBAR !#4 N7815 P2053 BLD 28 -1 FP BE Pri !#4 N7816 P2054 MEMBAR !#4 N7817 P2055 REPLACEMENT 9 Int BE Pri !#4 N7818 P2056 REPLACEMENT 3 Int BE Pri !#4 N7819 P2057 ST 13 0x200001c Int BE Pri !#4 N7820 P2058 MEMBAR !#4 N7821 P2059 BSTC 24 0x418000a6 FP BE Sec !#4 N7822 P2059 BSTC 25 0x418000a7 FP BE Sec !#4 N7823 P2060 MEMBAR !#4 N7824 P2061 LD 22 -1 Int BE Sec !#4 N7825 P2062 MEMBAR !#4 N7826 P2063 BLD 10 -1 FP BE Sec !#4 N7827 P2064 MEMBAR !#4 N7828 P2065 REPLACEMENT 2 Int BE Pri !#4 N7829 P2066 PREFETCH 17 Int BE Pri !#4 N7830 P2067 REPLACEMENT 17 Int BE Pri !#4 N7831 P2068 ST 29 0x200001d Int LE Pri !#4 N7832 P2069 MEMBAR !#4 N7833 P2070 BLD 17 -1 FP BE Pri !#4 N7834 P2071 MEMBAR !#4 N7835 P2072 BLD 21 -1 FP BE Pri !#4 N7836 P2072 BLD 22 -1 FP BE Pri !#A N7835 N7836 !#4 N7837 P2072 BLD 23 -1 FP BE Pri !#4 N7838 P2073 MEMBAR !#4 N7839 P2074 LD 14 -1 Int BE Pri !#4 N7840 P2075 REPLACEMENT 6 Int BE Pri !#4 N7841 P2076 MEMBAR !#4 N7842 P2077 BST 24 0x418000a8 FP BE Pri !#4 N7843 P2077 BST 25 0x418000a9 FP BE Pri !#4 N7844 P2078 MEMBAR !#4 N7845 P2079 BLD 20 -1 FP BE Pri !#4 N7846 P2080 MEMBAR !#4 N7847 P2081 BLD 21 -1 FP BE Sec !#4 N7848 P2081 BLD 22 -1 FP BE Sec !#A N7847 N7848 !#4 N7849 P2081 BLD 23 -1 FP BE Sec !#4 N7850 P2082 MEMBAR !#4 N7851 P2083 LD 32 -1 FP BE Pri !#4 N7852 P2084 MEMBAR !#4 N7853 P2085 BSTC 8 0x418000aa FP BE Pri !#4 N7854 P2085 BSTC 9 0x418000ab FP BE Pri !#4 N7855 P2086 MEMBAR !#4 N7856 P2087 BLD 20 -1 FP BE Pri !#4 N7857 P2088 MEMBAR !#4 N7858 P2089 LD 27 -1 FP BE Pri !#4 N7859 P2090 MEMBAR !#4 N7860 P2091 BLD 29 -1 FP BE Sec !#4 N7861 P2092 MEMBAR !#4 N7862 P2093 BLD 7 -1 FP BE Sec !#4 N7863 P2094 MEMBAR !#4 N7864 P2095 BLD 21 -1 FP BE Sec !#4 N7865 P2095 BLD 22 -1 FP BE Sec !#A N7864 N7865 !#4 N7866 P2095 BLD 23 -1 FP BE Sec !#4 N7867 P2096 MEMBAR !#4 N7868 P2097 LD 6 -1 FP BE Sec !#4 N7869 P2098 LD 8 -1 Int BE Pri !#4 N7870 P2099 MEMBAR !#4 N7871 P2100 BLD 8 -1 FP BE Pri !#4 N7872 P2100 BLD 9 -1 FP BE Pri !#4 N7873 P2101 MEMBAR !#4 N7874 P2102 BLD 21 -1 FP BE Pri !#4 N7875 P2102 BLD 22 -1 FP BE Pri !#A N7874 N7875 !#4 N7876 P2102 BLD 23 -1 FP BE Pri !#4 N7877 P2103 MEMBAR !#4 N7878 P2104 REPLACEMENT 23 Int BE Sec !#4 N7879 P2105 ST 26 0x418000ac FP BE Pri !#4 N7880 P2106 REPLACEMENT 6 Int BE Pri !#4 N7881 P2107 LD 27 -1 FP BE Nuc !#4 N7882 P2108 LD 21 -1 FP BE Pri !#4 N7883 P2109 MEMBAR !#4 N7884 P2110 BST 26 0x418000ad FP BE Pri !#4 N7885 P2110 BST 27 0x418000ae FP BE Pri !#4 N7886 P2111 MEMBAR !#4 N7887 P2112 ST 14 0x200001e Int BE Nuc !#4 N7888 P2113 REPLACEMENT 2 Int BE Pri !#4 N7889 P2114 REPLACEMENT 16 Int BE Pri !#4 N7890 P2115 REPLACEMENT 24 Int BE Pri !#4 N7891 P2116 REPLACEMENT 24 Int BE Pri !#4 N7892 P2117 REPLACEMENT 23 Int BE Pri !#4 N7893 P2118 MEMBAR !#4 N7894 P2119 BSTC 33 0x418000af FP BE Pri !#4 N7895 P2120 MEMBAR !#4 N7896 P2121 PREFETCH 19 Int BE Pri !#4 N7897 P2122 LD 0 -1 Int BE Pri Loop_exit !#4 N7898 P2123 MEMBAR !#4 N7899 P2124 BLD 32 -1 FP BE Pri !#4 N7900 P2125 MEMBAR !#4 N7901 P2126 BLD 31 -1 FP BE Sec !#4 N7902 P2127 MEMBAR !#4 N7903 P2128 BSTC 15 0x418000b0 FP BE Pri !#4 N7904 P2129 MEMBAR !#4 N7905 P2130 REPLACEMENT 4 Int BE Pri !#4 N7906 P2131 REPLACEMENT 20 Int BE Pri !#4 N7907 P2132 ST 8 0x200001f Int BE Pri !#4 N7908 P2133 MEMBAR !#4 N7909 P2134 BLD 29 -1 FP BE Pri !#4 N7910 P2135 MEMBAR !#4 N7911 P2136 REPLACEMENT 12 Int BE Pri !#4 N7912 P2137 REPLACEMENT 26 Int BE Pri !#4 N7913 P2138 ST 21 0x418000b1 FP BE Pri !#4 N7914 P2139 MEMBAR !#4 N7915 P2140 BST 26 0x418000b2 FP BE Pri !#4 N7916 P2140 BST 27 0x418000b3 FP BE Pri !#4 N7917 P2141 MEMBAR !#4 N7918 P2142 REPLACEMENT 19 Int BE Sec !#4 N7919 P2143 MEMBAR !#4 N7920 P2144 BSTC 11 0x418000b4 FP BE Pri !#4 N7921 P2144 BSTC 12 0x418000b5 FP BE Pri !#A N7920 N7921 !#4 N7922 P2144 BSTC 13 0x418000b6 FP BE Pri !#4 N7923 P2145 MEMBAR !#4 N7924 P2146 BLD 5 -1 FP BE Pri !#4 N7925 P2146 BLD 6 -1 FP BE Pri !#4 N7926 P2147 MEMBAR !#4 N7927 P2148 BLD 30 -1 FP BE Pri !#4 N7928 P2149 MEMBAR !#4 N7929 P2150 BLD 30 -1 FP BE Pri !#4 N7930 P2151 MEMBAR !#4 N7931 P2152 BLD 0 -1 FP BE Pri !#4 N7932 P2152 BLD 1 -1 FP BE Pri !#A N7931 N7932 !#4 N7933 P2152 BLD 2 -1 FP BE Pri !#4 N7934 P2152 BLD 3 -1 FP BE Pri !#4 N7935 P2152 BLD 4 -1 FP BE Pri !#4 N7936 P2153 MEMBAR !#4 N7937 P2154 BSTC 8 0x418000b7 FP BE Pri !#4 N7938 P2154 BSTC 9 0x418000b8 FP BE Pri !#4 N7939 P2155 MEMBAR !#4 N7940 P2156 REPLACEMENT 31 Int BE Pri !#4 N7941 P2157 LD 27 -1 FP BE Pri !#4 N7942 P2158 REPLACEMENT 16 Int BE Pri !#4 N7943 P2159 MEMBAR !#4 N7944 P2160 BSTC 32 0x418000b9 FP BE Sec !#4 N7945 P2161 MEMBAR !#4 N7946 P2162 REPLACEMENT 8 Int BE Pri !#4 N7947 P2163 MEMBAR !#4 N7948 P2164 BST 8 0x418000ba FP BE Pri !#4 N7949 P2164 BST 9 0x418000bb FP BE Pri !#4 N7950 P2165 MEMBAR !#4 N7951 P2166 BST 21 0x418000bc FP BE Pri !#4 N7952 P2166 BST 22 0x418000bd FP BE Pri !#A N7951 N7952 !#4 N7953 P2166 BST 23 0x418000be FP BE Pri !#4 N7954 P2167 MEMBAR !#4 N7955 P2168 ST 10 0x418000bf FP BE Pri !#4 N7956 P2169 PREFETCH 18 Int BE Pri !#4 N7957 P2170 REPLACEMENT 23 Int BE Pri !#4 N7958 P2171 MEMBAR !#4 N7959 P2172 BLD 7 -1 FP BE Pri !#4 N7960 P2173 MEMBAR !#4 N7961 P2174 BST 33 0x418000c0 FP BE Pri !#4 N7962 P2175 MEMBAR !#4 N7963 P2176 PREFETCH 32 Int LE Sec !#4 N7964 P2177 ST 18 0x418000c1 FP BE Pri !#4 N7965 P2178 PREFETCH 7 Int BE Pri !#4 N7966 P2179 LD 0 -1 FP BE Pri !#4 N7967 P2180 MEMBAR !#4 N7968 P2181 BST 21 0x418000c2 FP BE Pri !#4 N7969 P2181 BST 22 0x418000c3 FP BE Pri !#A N7968 N7969 !#4 N7970 P2181 BST 23 0x418000c4 FP BE Pri !#4 N7971 P2182 MEMBAR !#4 N7972 P2183 ST 33 0x418000c5 FP BE Pri !#4 N7973 P2184 REPLACEMENT 12 Int BE Sec !#4 N7974 P2185 REPLACEMENT 24 Int BE Nuc !#4 N7975 P2186 ST 15 0x2000020 Int BE Nuc !#4 N7976 P2187 REPLACEMENT 10 Int BE Pri !#4 N7977 P2188 PREFETCH 15 Int LE Pri !#4 N7978 P2189 MEMBAR !#4 N7979 P2190 BLD 18 -1 FP BE Pri !#4 N7980 P2191 MEMBAR !#4 N7981 P2192 ST 27 0x418000c6 FP BE Sec !#4 N7982 P2193 ST 14 0x2000021 Int BE Pri !#4 N7983 P2194 MEMBAR !#4 N7984 P2195 BST 21 0x418000c7 FP BE Sec !#4 N7985 P2195 BST 22 0x418000c8 FP BE Sec !#A N7984 N7985 !#4 N7986 P2195 BST 23 0x418000c9 FP BE Sec !#4 N7987 P2196 MEMBAR !#4 N7988 P2197 REPLACEMENT 16 Int BE Nuc !#4 N7989 P2198 REPLACEMENT 6 Int BE Pri !#4 N7990 P2199 MEMBAR !#4 N7991 P2200 BLD 31 -1 FP BE Pri !#4 N7992 P2201 MEMBAR !#4 N7993 P2202 BLD 26 -1 FP BE Pri !#4 N7994 P2202 BLD 27 -1 FP BE Pri !#4 N7995 P2203 MEMBAR !#4 N7996 P2204 BLD 24 -1 FP BE Pri !#4 N7997 P2204 BLD 25 -1 FP BE Pri !#4 N7998 P2205 MEMBAR !#4 N7999 P2206 PREFETCH 32 Int BE Nuc !#4 N8000 P2207 ST 1 0x2000022 Int BE Pri !#4 N8001 P2208 MEMBAR !#4 N8002 P2209 BLD 20 -1 FP BE Pri !#4 N8003 P2210 MEMBAR !#4 N8004 P2211 REPLACEMENT 26 Int BE Pri !#4 N8005 P2212 MEMBAR !#4 N8006 P2213 BLD 26 -1 FP BE Pri !#4 N8007 P2213 BLD 27 -1 FP BE Pri !#4 N8008 P2214 MEMBAR !#4 N8009 P2215 BLD 19 -1 FP BE Pri !#4 N8010 P2216 MEMBAR !#4 N8011 P2217 BST 10 0x418000ca FP BE Pri !#4 N8012 P2218 MEMBAR !#4 N8013 P2219 IDC_FLIP 20 Int BE Pri !#4 N8014 P2220 ST 16 0x2000023 Int BE Pri !#4 N8015 P2221 REPLACEMENT 21 Int BE Sec !#4 N8016 P2222 MEMBAR !#4 N8017 P2223 BLD 0 -1 FP BE Pri !#4 N8018 P2223 BLD 1 -1 FP BE Pri !#A N8017 N8018 !#4 N8019 P2223 BLD 2 -1 FP BE Pri !#4 N8020 P2223 BLD 3 -1 FP BE Pri !#4 N8021 P2223 BLD 4 -1 FP BE Pri !#4 N8022 P2224 MEMBAR !#4 N8023 P2225 MEMBAR !#5 N8024 P2226 MEMBAR !#5 N8025 P2227 BST 5 0x42000001 FP BE Pri !#5 N8026 P2227 BST 6 0x42000002 FP BE Pri !#5 N8027 P2228 MEMBAR !#5 N8028 P2229 BLD 11 -1 FP BE Sec !#5 N8029 P2229 BLD 12 -1 FP BE Sec !#A N8028 N8029 !#5 N8030 P2229 BLD 13 -1 FP BE Sec !#5 N8031 P2230 MEMBAR !#5 N8032 P2231 BST 11 0x42000003 FP BE Sec !#5 N8033 P2231 BST 12 0x42000004 FP BE Sec !#A N8032 N8033 !#5 N8034 P2231 BST 13 0x42000005 FP BE Sec !#5 N8035 P2232 MEMBAR !#5 N8036 P2233 ST 32 0x2800001 Int BE Nuc !#5 N8037 P2234 MEMBAR !#5 N8038 P2235 BLD 33 -1 FP BE Pri !#5 N8039 P2236 MEMBAR !#5 N8040 P2237 REPLACEMENT 27 Int BE Sec !#5 N8041 P2238 MEMBAR !#5 N8042 P2239 BLD 17 -1 FP BE Sec !#5 N8043 P2240 MEMBAR !#5 N8044 P2241 REPLACEMENT 23 Int BE Nuc !#5 N8045 P2242 MEMBAR !#5 N8046 P2243 BLD 20 -1 FP BE Pri !#5 N8047 P2244 MEMBAR !#5 N8048 P2245 BST 10 0x42000006 FP BE Pri !#5 N8049 P2246 MEMBAR !#5 N8050 P2247 ST 20 0x42000007 FP BE Pri !#5 N8051 P2248 PREFETCH 11 Int LE Pri !#5 N8052 P2249 ST 31 0x2800002 Int BE Pri !#5 N8053 P2250 LD 26 -1 FP BE Sec !#5 N8054 P2251 MEMBAR !#5 N8055 P2252 BLD 20 -1 FP BE Pri !#5 N8056 P2253 MEMBAR !#5 N8057 P2254 PREFETCH 7 Int BE Nuc !#5 N8058 P2255 MEMBAR !#5 N8059 P2256 BST 15 0x42000008 FP BE Pri !#5 N8060 P2257 MEMBAR !#5 N8061 P2258 BSTC 0 0x42000009 FP BE Pri !#5 N8062 P2258 BSTC 1 0x4200000a FP BE Pri !#A N8061 N8062 !#5 N8063 P2258 BSTC 2 0x4200000b FP BE Pri !#5 N8064 P2258 BSTC 3 0x4200000c FP BE Pri !#5 N8065 P2258 BSTC 4 0x4200000d FP BE Pri !#5 N8066 P2259 MEMBAR !#5 N8067 P2260 REPLACEMENT 13 Int BE Pri !#5 N8068 P2261 MEMBAR !#5 N8069 P2262 BST 11 0x4200000e FP BE Pri !#5 N8070 P2262 BST 12 0x4200000f FP BE Pri !#A N8069 N8070 !#5 N8071 P2262 BST 13 0x42000010 FP BE Pri !#5 N8072 P2263 MEMBAR !#5 N8073 P2264 ST 20 0x2800003 Int BE Pri !#5 N8074 P2265 MEMBAR !#5 N8075 P2266 BLD 10 -1 FP BE Pri !#5 N8076 P2267 MEMBAR !#5 N8077 P2268 REPLACEMENT 2 Int BE Pri !#5 N8078 P2269 MEMBAR !#5 N8079 P2270 BLD 5 -1 FP BE Sec !#5 N8080 P2270 BLD 6 -1 FP BE Sec !#5 N8081 P2271 MEMBAR !#5 N8082 P2272 PREFETCH 5 Int BE Nuc !#5 N8083 P2273 ST 13 0x42000011 FP BE Nuc !#5 N8084 P2274 REPLACEMENT 7 Int BE Pri !#5 N8085 P2275 LD 11 -1 Int BE Pri !#5 N8086 P2276 ST 12 0x2800004 Int BE Sec !#5 N8087 P2277 MEMBAR !#5 N8088 P2278 BLD 31 -1 FP BE Pri !#5 N8089 P2279 MEMBAR !#5 N8090 P2280 BST 20 0x42000012 FP BE Pri !#5 N8091 P2281 MEMBAR !#5 N8092 P2282 REPLACEMENT 19 Int BE Pri !#5 N8093 P2283 MEMBAR !#5 N8094 P2284 BST 17 0x42000013 FP BE Pri !#5 N8095 P2285 MEMBAR !#5 N8096 P2286 BST 16 0x42000014 FP BE Pri !#5 N8097 P2287 MEMBAR !#5 N8098 P2288 ST 11 0x2800005 Int BE Nuc !#5 N8099 P2289 REPLACEMENT 17 Int BE Pri !#5 N8100 P2290 REPLACEMENT 17 Int BE Pri !#5 N8101 P2291 MEMBAR !#5 N8102 P2292 BSTC 14 0x42000015 FP BE Sec !#5 N8103 P2293 MEMBAR !#5 N8104 P2294 BST 0 0x42000016 FP BE Pri !#5 N8105 P2294 BST 1 0x42000017 FP BE Pri !#A N8104 N8105 !#5 N8106 P2294 BST 2 0x42000018 FP BE Pri !#5 N8107 P2294 BST 3 0x42000019 FP BE Pri !#5 N8108 P2294 BST 4 0x4200001a FP BE Pri !#5 N8109 P2295 MEMBAR !#5 N8110 P2296 REPLACEMENT 13 Int BE Pri !#5 N8111 P2297 MEMBAR !#5 N8112 P2298 BST 20 0x4200001b FP BE Pri !#5 N8113 P2299 MEMBAR !#5 N8114 P2300 BLD 8 -1 FP BE Pri !#5 N8115 P2300 BLD 9 -1 FP BE Pri !#5 N8116 P2301 MEMBAR !#5 N8117 P2302 LD 27 -1 FP BE Pri !#5 N8118 P2303 MEMBAR !#5 N8119 P2304 BLD 8 -1 FP BE Pri !#5 N8120 P2304 BLD 9 -1 FP BE Pri !#5 N8121 P2305 MEMBAR !#5 N8122 P2306 REPLACEMENT 25 Int BE Sec !#5 N8123 P2307 REPLACEMENT 5 Int BE Pri !#5 N8124 P2308 REPLACEMENT 15 Int BE Pri !#5 N8125 P2309 MEMBAR !#5 N8126 P2310 BLD 0 -1 FP BE Sec !#5 N8127 P2310 BLD 1 -1 FP BE Sec !#A N8126 N8127 !#5 N8128 P2310 BLD 2 -1 FP BE Sec !#5 N8129 P2310 BLD 3 -1 FP BE Sec !#5 N8130 P2310 BLD 4 -1 FP BE Sec !#5 N8131 P2311 MEMBAR !#5 N8132 P2312 LD 15 -1 Int BE Pri !#5 N8133 P2313 PREFETCH 0 Int BE Pri !#5 N8134 P2314 MEMBAR !#5 N8135 P2315 BLD 21 -1 FP BE Pri !#5 N8136 P2315 BLD 22 -1 FP BE Pri !#A N8135 N8136 !#5 N8137 P2315 BLD 23 -1 FP BE Pri !#5 N8138 P2316 MEMBAR !#5 N8139 P2317 BST 10 0x4200001c FP BE Pri !#5 N8140 P2318 MEMBAR !#5 N8141 P2319 LD 13 -1 Int BE Pri !#5 N8142 P2320 MEMBAR !#5 N8143 P2321 BST 8 0x4200001d FP BE Pri !#5 N8144 P2321 BST 9 0x4200001e FP BE Pri !#5 N8145 P2322 MEMBAR !#5 N8146 P2323 REPLACEMENT 25 Int BE Sec !#5 N8147 P2324 LD 4 -1 FP BE Pri !#5 N8148 P2325 LD 14 -1 Int BE Pri !#5 N8149 P2326 PREFETCH 18 Int BE Sec !#5 N8150 P2327 IDC_FLIP 11 Int BE Pri !#5 N8151 P2328 ST 14 0x4200001f FP BE Pri !#5 N8152 P2329 MEMBAR !#5 N8153 P2330 BST 24 0x42000020 FP BE Pri !#5 N8154 P2330 BST 25 0x42000021 FP BE Pri !#5 N8155 P2331 MEMBAR !#5 N8156 P2332 ST 3 0x2800006 Int BE Sec !#5 N8157 P2333 REPLACEMENT 9 Int BE Nuc !#5 N8158 P2334 REPLACEMENT 16 Int BE Pri !#5 N8159 P2335 PREFETCH 25 Int BE Pri !#5 N8160 P2336 MEMBAR !#5 N8161 P2337 BLD 8 -1 FP BE Pri !#5 N8162 P2337 BLD 9 -1 FP BE Pri !#5 N8163 P2338 MEMBAR !#5 N8164 P2339 LD 21 -1 FP BE Pri !#5 N8165 P2340 MEMBAR !#5 N8166 P2341 BLD 15 -1 FP BE Pri !#5 N8167 P2342 MEMBAR !#5 N8168 P2343 PREFETCH 3 Int BE Pri !#5 N8169 P2344 MEMBAR !#5 N8170 P2345 BLD 17 -1 FP BE Pri !#5 N8171 P2346 MEMBAR !#5 N8172 P2347 BST 31 0x42000022 FP BE Pri !#5 N8173 P2348 MEMBAR !#5 N8174 P2349 ST 9 0x42000023 FP BE Pri !#5 N8175 P2350 PREFETCH 8 Int BE Sec !#5 N8176 P2351 PREFETCH 22 Int BE Pri !#5 N8177 P2352 MEMBAR !#5 N8178 P2353 BLD 32 -1 FP BE Sec !#5 N8179 P2354 MEMBAR !#5 N8180 P2355 REPLACEMENT 18 Int BE Pri !#5 N8181 P2356 MEMBAR !#5 N8182 P2357 BST 11 0x42000024 FP BE Pri !#5 N8183 P2357 BST 12 0x42000025 FP BE Pri !#A N8182 N8183 !#5 N8184 P2357 BST 13 0x42000026 FP BE Pri !#5 N8185 P2358 MEMBAR !#5 N8186 P2359 BLD 0 -1 FP BE Pri !#5 N8187 P2359 BLD 1 -1 FP BE Pri !#A N8186 N8187 !#5 N8188 P2359 BLD 2 -1 FP BE Pri !#5 N8189 P2359 BLD 3 -1 FP BE Pri !#5 N8190 P2359 BLD 4 -1 FP BE Pri !#5 N8191 P2360 MEMBAR !#5 N8192 P2361 BSTC 0 0x42000027 FP BE Sec !#5 N8193 P2361 BSTC 1 0x42000028 FP BE Sec !#A N8192 N8193 !#5 N8194 P2361 BSTC 2 0x42000029 FP BE Sec !#5 N8195 P2361 BSTC 3 0x4200002a FP BE Sec !#5 N8196 P2361 BSTC 4 0x4200002b FP BE Sec !#5 N8197 P2362 MEMBAR !#5 N8198 P2363 REPLACEMENT 13 Int BE Pri !#5 N8199 P2364 MEMBAR !#5 N8200 P2365 BLD 18 -1 FP BE Pri !#5 N8201 P2366 MEMBAR !#5 N8202 P2367 BLD 29 -1 FP BE Pri !#5 N8203 P2368 MEMBAR !#5 N8204 P2369 LD 14 -1 Int BE Pri !#5 N8205 P2370 LD 26 -1 Int BE Pri !#5 N8206 P2371 REPLACEMENT 1 Int BE Pri !#5 N8207 P2372 MEMBAR !#5 N8208 P2373 BSTC 14 0x4200002c FP BE Sec !#5 N8209 P2374 MEMBAR !#5 N8210 P2375 BLD 0 -1 FP BE Sec !#5 N8211 P2375 BLD 1 -1 FP BE Sec !#A N8210 N8211 !#5 N8212 P2375 BLD 2 -1 FP BE Sec !#5 N8213 P2375 BLD 3 -1 FP BE Sec !#5 N8214 P2375 BLD 4 -1 FP BE Sec !#5 N8215 P2376 MEMBAR !#5 N8216 P2377 LD 11 -1 Int BE Pri !#5 N8217 P2378 MEMBAR !#5 N8218 P2379 BSTC 17 0x4200002d FP BE Pri !#5 N8219 P2380 MEMBAR !#5 N8220 P2381 BSTC 32 0x4200002e FP BE Pri !#5 N8221 P2382 MEMBAR !#5 N8222 P2383 BLD 21 -1 FP BE Pri !#5 N8223 P2383 BLD 22 -1 FP BE Pri !#A N8222 N8223 !#5 N8224 P2383 BLD 23 -1 FP BE Pri !#5 N8225 P2384 MEMBAR !#5 N8226 P2385 ST 13 0x2800007 Int BE Nuc !#5 N8227 P2386 LD 26 -1 Int BE Pri !#5 N8228 P2387 REPLACEMENT 4 Int BE Pri !#5 N8229 P2388 MEMBAR !#5 N8230 P2389 BLD 32 -1 FP BE Pri !#5 N8231 P2390 MEMBAR !#5 N8232 P2391 ST 11 0x2800008 Int BE Pri !#5 N8233 P2392 REPLACEMENT 7 Int BE Pri !#5 N8234 P2393 PREFETCH 26 Int BE Pri !#5 N8235 P2394 MEMBAR !#5 N8236 P2395 BSTC 10 0x4200002f FP BE Pri !#5 N8237 P2396 MEMBAR !#5 N8238 P2397 BSTC 33 0x42000030 FP BE Pri !#5 N8239 P2398 MEMBAR !#5 N8240 P2399 ST 18 0x42000031 FP BE Pri !#5 N8241 P2400 REPLACEMENT 8 Int BE Pri !#5 N8242 P2401 MEMBAR !#5 N8243 P2402 BST 19 0x42000032 FP BE Pri !#5 N8244 P2403 MEMBAR !#5 N8245 P2404 BSTC 24 0x42000033 FP BE Pri !#5 N8246 P2404 BSTC 25 0x42000034 FP BE Pri !#5 N8247 P2405 MEMBAR !#5 N8248 P2406 BLD 17 -1 FP BE Pri !#5 N8249 P2407 MEMBAR !#5 N8250 P2408 REPLACEMENT 23 Int BE Nuc !#5 N8251 P2409 REPLACEMENT 14 Int BE Pri !#5 N8252 P2410 MEMBAR !#5 N8253 P2411 BLD 26 -1 FP BE Pri !#5 N8254 P2411 BLD 27 -1 FP BE Pri !#5 N8255 P2412 MEMBAR !#5 N8256 P2413 BLD 11 -1 FP BE Pri !#5 N8257 P2413 BLD 12 -1 FP BE Pri !#A N8256 N8257 !#5 N8258 P2413 BLD 13 -1 FP BE Pri !#5 N8259 P2414 MEMBAR !#5 N8260 P2415 REPLACEMENT 30 Int BE Pri !#5 N8261 P2416 MEMBAR !#5 N8262 P2417 BLD 15 -1 FP BE Pri !#5 N8263 P2418 MEMBAR !#5 N8264 P2419 BSTC 0 0x42000035 FP BE Pri !#5 N8265 P2419 BSTC 1 0x42000036 FP BE Pri !#A N8264 N8265 !#5 N8266 P2419 BSTC 2 0x42000037 FP BE Pri !#5 N8267 P2419 BSTC 3 0x42000038 FP BE Pri !#5 N8268 P2419 BSTC 4 0x42000039 FP BE Pri !#5 N8269 P2420 MEMBAR !#5 N8270 P2421 BSTC 26 0x4200003a FP BE Pri !#5 N8271 P2421 BSTC 27 0x4200003b FP BE Pri !#5 N8272 P2422 MEMBAR !#5 N8273 P2423 REPLACEMENT 3 Int BE Pri !#5 N8274 P2424 ST 21 0x2800009 Int BE Pri !#5 N8275 P2425 IDC_FLIP 29 Int BE Pri !#5 N8276 P2426 MEMBAR !#5 N8277 P2427 BSTC 0 0x4200003c FP BE Pri !#5 N8278 P2427 BSTC 1 0x4200003d FP BE Pri !#A N8277 N8278 !#5 N8279 P2427 BSTC 2 0x4200003e FP BE Pri !#5 N8280 P2427 BSTC 3 0x4200003f FP BE Pri !#5 N8281 P2427 BSTC 4 0x42000040 FP BE Pri !#5 N8282 P2428 MEMBAR !#5 N8283 P2429 LD 33 -1 FP BE Pri !#5 N8284 P2430 MEMBAR !#5 N8285 P2431 BLD 5 -1 FP BE Pri !#5 N8286 P2431 BLD 6 -1 FP BE Pri !#5 N8287 P2432 MEMBAR !#5 N8288 P2433 ST 18 0x280000a Int BE Pri !#5 N8289 P2434 LD 8 -1 Int BE Sec !#5 N8290 P2435 MEMBAR !#5 N8291 P2436 BST 0 0x42000041 FP BE Pri !#5 N8292 P2436 BST 1 0x42000042 FP BE Pri !#A N8291 N8292 !#5 N8293 P2436 BST 2 0x42000043 FP BE Pri !#5 N8294 P2436 BST 3 0x42000044 FP BE Pri !#5 N8295 P2436 BST 4 0x42000045 FP BE Pri !#5 N8296 P2437 MEMBAR !#5 N8297 P2438 BST 26 0x42000046 FP BE Pri !#5 N8298 P2438 BST 27 0x42000047 FP BE Pri !#5 N8299 P2439 MEMBAR !#5 N8300 P2440 LD 5 -1 FP BE Pri !#5 N8301 P2441 MEMBAR !#5 N8302 P2442 BLD 16 -1 FP BE Sec !#5 N8303 P2443 MEMBAR !#5 N8304 P2444 BSTC 15 0x42000048 FP BE Sec !#5 N8305 P2445 MEMBAR !#5 N8306 P2446 PREFETCH 15 Int BE Sec !#5 N8307 P2447 MEMBAR !#5 N8308 P2448 BLD 31 -1 FP BE Sec !#5 N8309 P2449 MEMBAR !#5 N8310 P2450 BLD 29 -1 FP BE Pri !#5 N8311 P2451 MEMBAR !#5 N8312 P2452 PREFETCH 31 Int BE Pri !#5 N8313 P2453 ST 20 0x280000b Int BE Pri !#5 N8314 P2454 IDC_FLIP 0 Int BE Pri !#5 N8315 P2455 LD 9 -1 FP BE Pri !#5 N8316 P2456 MEMBAR !#5 N8317 P2457 BLD 32 -1 FP BE Pri !#5 N8318 P2458 MEMBAR !#5 N8319 P2459 LD 25 -1 FP BE Pri !#5 N8320 P2460 ST 19 0x280000c Int BE Pri !#5 N8321 P2461 ST 1 0x280000d Int BE Pri !#5 N8322 P2462 PREFETCH 31 Int BE Pri !#5 N8323 P2463 LD 2 -1 FP BE Sec !#5 N8324 P2464 MEMBAR !#5 N8325 P2465 BSTC 24 0x42000049 FP BE Pri !#5 N8326 P2465 BSTC 25 0x4200004a FP BE Pri !#5 N8327 P2466 MEMBAR !#5 N8328 P2467 BLD 33 -1 FP BE Pri !#5 N8329 P2468 MEMBAR !#5 N8330 P2469 BSTC 32 0x4200004b FP BE Sec !#5 N8331 P2470 MEMBAR !#5 N8332 P2471 ST 7 0x4200004c FP BE Nuc !#5 N8333 P2472 REPLACEMENT 22 Int BE Pri !#5 N8334 P2473 MEMBAR !#5 N8335 P2474 BLD 8 -1 FP BE Pri !#5 N8336 P2474 BLD 9 -1 FP BE Pri !#5 N8337 P2475 MEMBAR !#5 N8338 P2476 BLD 11 -1 FP BE Pri !#5 N8339 P2476 BLD 12 -1 FP BE Pri !#A N8338 N8339 !#5 N8340 P2476 BLD 13 -1 FP BE Pri !#5 N8341 P2477 MEMBAR !#5 N8342 P2478 BLD 8 -1 FP BE Sec !#5 N8343 P2478 BLD 9 -1 FP BE Sec !#5 N8344 P2479 MEMBAR !#5 N8345 P2480 ST 15 0x280000e Int BE Pri !#5 N8346 P2481 MEMBAR !#5 N8347 P2482 BLD 29 -1 FP BE Pri !#5 N8348 P2483 MEMBAR !#5 N8349 P2484 BLD 21 -1 FP BE Pri !#5 N8350 P2484 BLD 22 -1 FP BE Pri !#A N8349 N8350 !#5 N8351 P2484 BLD 23 -1 FP BE Pri !#5 N8352 P2485 MEMBAR !#5 N8353 P2486 BLD 18 -1 FP BE Pri !#5 N8354 P2487 MEMBAR !#5 N8355 P2488 PREFETCH 16 Int BE Pri !#5 N8356 P2489 LD 30 -1 FP BE Pri !#5 N8357 P2490 ST 19 0x280000f Int BE Pri !#5 N8358 P2491 LD 26 -1 Int BE Pri !#5 N8359 P2492 REPLACEMENT 28 Int BE Pri !#5 N8360 P2493 ST 29 0x2800010 Int BE Nuc !#5 N8361 P2494 LD 28 -1 Int LE Pri !#5 N8362 P2495 LD 1 -1 Int BE Pri !#5 N8363 P2496 ST 16 0x2800011 Int BE Pri !#5 N8364 P2497 ST 20 0x4200004d FP BE Nuc !#5 N8365 P2498 MEMBAR !#5 N8366 P2499 BSTC 0 0x4200004e FP BE Pri !#5 N8367 P2499 BSTC 1 0x4200004f FP BE Pri !#A N8366 N8367 !#5 N8368 P2499 BSTC 2 0x42000050 FP BE Pri !#5 N8369 P2499 BSTC 3 0x42000051 FP BE Pri !#5 N8370 P2499 BSTC 4 0x42000052 FP BE Pri !#5 N8371 P2500 MEMBAR !#5 N8372 P2501 BLD 8 -1 FP BE Pri !#5 N8373 P2501 BLD 9 -1 FP BE Pri !#5 N8374 P2502 MEMBAR !#5 N8375 P2503 REPLACEMENT 5 Int BE Pri !#5 N8376 P2504 MEMBAR !#5 N8377 P2505 BLD 21 -1 FP BE Sec !#5 N8378 P2505 BLD 22 -1 FP BE Sec !#A N8377 N8378 !#5 N8379 P2505 BLD 23 -1 FP BE Sec !#5 N8380 P2506 MEMBAR !#5 N8381 P2507 ST 18 0x42000053 FP BE Pri !#5 N8382 P2508 REPLACEMENT 18 Int BE Sec !#5 N8383 P2509 MEMBAR !#5 N8384 P2510 BST 11 0x42000054 FP BE Pri !#5 N8385 P2510 BST 12 0x42000055 FP BE Pri !#A N8384 N8385 !#5 N8386 P2510 BST 13 0x42000056 FP BE Pri !#5 N8387 P2511 MEMBAR !#5 N8388 P2512 BLD 32 -1 FP BE Pri !#5 N8389 P2513 MEMBAR !#5 N8390 P2514 BLD 26 -1 FP BE Sec !#5 N8391 P2514 BLD 27 -1 FP BE Sec !#5 N8392 P2515 MEMBAR !#5 N8393 P2516 BLD 0 -1 FP BE Pri !#5 N8394 P2516 BLD 1 -1 FP BE Pri !#A N8393 N8394 !#5 N8395 P2516 BLD 2 -1 FP BE Pri !#5 N8396 P2516 BLD 3 -1 FP BE Pri !#5 N8397 P2516 BLD 4 -1 FP BE Pri !#5 N8398 P2517 MEMBAR !#5 N8399 P2518 LD 21 -1 FP BE Pri !#5 N8400 P2519 IDC_FLIP 23 Int BE Pri !#5 N8401 P2520 ST 3 0x42000057 FP BE Pri !#5 N8402 P2521 ST 28 0x42000058 FP BE Pri !#5 N8403 P2522 ST 27 0x42000059 FP BE Pri !#5 N8404 P2523 REPLACEMENT 18 Int BE Sec !#5 N8405 P2524 LD 29 -1 FP BE Pri !#5 N8406 P2525 IDC_FLIP 20 Int BE Pri !#5 N8407 P2526 LD 3 -1 Int BE Pri !#5 N8408 P2527 PREFETCH 14 Int BE Pri !#5 N8409 P2528 ST 12 0x2800012 Int BE Pri !#5 N8410 P2529 PREFETCH 21 Int BE Pri !#5 N8411 P2530 REPLACEMENT 16 Int BE Pri !#5 N8412 P2531 ST 20 0x4200005a FP BE Pri !#5 N8413 P2532 ST 6 0x2800013 Int BE Nuc !#5 N8414 P2533 REPLACEMENT 4 Int BE Pri !#5 N8415 P2534 REPLACEMENT 5 Int BE Sec !#5 N8416 P2535 MEMBAR !#5 N8417 P2536 BSTC 15 0x4200005b FP BE Pri !#5 N8418 P2537 MEMBAR !#5 N8419 P2538 ST 22 0x4200005c FP BE Pri !#5 N8420 P2539 ST 16 0x4200005d FP BE Pri !#5 N8421 P2540 MEMBAR !#5 N8422 P2541 BST 21 0x4200005e FP BE Sec !#5 N8423 P2541 BST 22 0x4200005f FP BE Sec !#A N8422 N8423 !#5 N8424 P2541 BST 23 0x42000060 FP BE Sec !#5 N8425 P2542 MEMBAR !#5 N8426 P2543 BST 5 0x42000061 FP BE Pri !#5 N8427 P2543 BST 6 0x42000062 FP BE Pri !#5 N8428 P2544 MEMBAR !#5 N8429 P2545 BLD 0 -1 FP BE Pri !#5 N8430 P2545 BLD 1 -1 FP BE Pri !#A N8429 N8430 !#5 N8431 P2545 BLD 2 -1 FP BE Pri !#5 N8432 P2545 BLD 3 -1 FP BE Pri !#5 N8433 P2545 BLD 4 -1 FP BE Pri !#5 N8434 P2546 MEMBAR !#5 N8435 P2547 BLD 5 -1 FP BE Pri !#5 N8436 P2547 BLD 6 -1 FP BE Pri !#5 N8437 P2548 MEMBAR !#5 N8438 P2549 BST 24 0x42000063 FP BE Pri !#5 N8439 P2549 BST 25 0x42000064 FP BE Pri !#5 N8440 P2550 MEMBAR !#5 N8441 P2551 REPLACEMENT 21 Int BE Pri !#5 N8442 P2552 REPLACEMENT 3 Int BE Pri !#5 N8443 P2553 MEMBAR !#5 N8444 P2554 BST 32 0x42000065 FP BE Pri !#5 N8445 P2555 MEMBAR !#5 N8446 P2556 PREFETCH 30 Int BE Pri !#5 N8447 P2557 MEMBAR !#5 N8448 P2558 BLD 0 -1 FP BE Pri !#5 N8449 P2558 BLD 1 -1 FP BE Pri !#A N8448 N8449 !#5 N8450 P2558 BLD 2 -1 FP BE Pri !#5 N8451 P2558 BLD 3 -1 FP BE Pri !#5 N8452 P2558 BLD 4 -1 FP BE Pri !#5 N8453 P2559 MEMBAR !#5 N8454 P2560 BST 14 0x42000066 FP BE Pri !#5 N8455 P2561 MEMBAR !#5 N8456 P2562 BLD 21 -1 FP BE Pri !#5 N8457 P2562 BLD 22 -1 FP BE Pri !#A N8456 N8457 !#5 N8458 P2562 BLD 23 -1 FP BE Pri !#5 N8459 P2563 MEMBAR !#5 N8460 P2564 BSTC 24 0x42000067 FP BE Pri !#5 N8461 P2564 BSTC 25 0x42000068 FP BE Pri !#5 N8462 P2565 MEMBAR !#5 N8463 P2566 BLD 11 -1 FP BE Pri !#5 N8464 P2566 BLD 12 -1 FP BE Pri !#A N8463 N8464 !#5 N8465 P2566 BLD 13 -1 FP BE Pri !#5 N8466 P2567 MEMBAR !#5 N8467 P2568 LD 10 -1 FP BE Pri !#5 N8468 P2569 MEMBAR !#5 N8469 P2570 BLD 21 -1 FP BE Sec !#5 N8470 P2570 BLD 22 -1 FP BE Sec !#A N8469 N8470 !#5 N8471 P2570 BLD 23 -1 FP BE Sec !#5 N8472 P2571 MEMBAR !#5 N8473 P2572 BLD 5 -1 FP BE Pri !#5 N8474 P2572 BLD 6 -1 FP BE Pri !#5 N8475 P2573 MEMBAR !#5 N8476 P2574 REPLACEMENT 7 Int BE Pri !#5 N8477 P2575 MEMBAR !#5 N8478 P2576 BST 21 0x42000069 FP BE Sec !#5 N8479 P2576 BST 22 0x4200006a FP BE Sec !#A N8478 N8479 !#5 N8480 P2576 BST 23 0x4200006b FP BE Sec !#5 N8481 P2577 MEMBAR !#5 N8482 P2578 BLD 8 -1 FP BE Pri !#5 N8483 P2578 BLD 9 -1 FP BE Pri !#5 N8484 P2579 MEMBAR !#5 N8485 P2580 BSTC 26 0x4200006c FP BE Pri !#5 N8486 P2580 BSTC 27 0x4200006d FP BE Pri !#5 N8487 P2581 MEMBAR !#5 N8488 P2582 BSTC 0 0x4200006e FP BE Pri !#5 N8489 P2582 BSTC 1 0x4200006f FP BE Pri !#A N8488 N8489 !#5 N8490 P2582 BSTC 2 0x42000070 FP BE Pri !#5 N8491 P2582 BSTC 3 0x42000071 FP BE Pri !#5 N8492 P2582 BSTC 4 0x42000072 FP BE Pri !#5 N8493 P2583 MEMBAR !#5 N8494 P2584 BLD 26 -1 FP BE Pri !#5 N8495 P2584 BLD 27 -1 FP BE Pri !#5 N8496 P2585 MEMBAR !#5 N8497 P2586 BLD 29 -1 FP BE Pri !#5 N8498 P2587 MEMBAR !#5 N8499 P2588 REPLACEMENT 33 Int BE Pri !#5 N8500 P2589 MEMBAR !#5 N8501 P2590 BST 15 0x42000073 FP BE Pri !#5 N8502 P2591 MEMBAR !#5 N8503 P2592 LD 30 -1 FP BE Nuc !#5 N8504 P2593 MEMBAR !#5 N8505 P2594 BST 26 0x42000074 FP BE Pri !#5 N8506 P2594 BST 27 0x42000075 FP BE Pri !#5 N8507 P2595 MEMBAR !#5 N8508 P2596 BSTC 30 0x42000076 FP BE Pri !#5 N8509 P2597 MEMBAR !#5 N8510 P2598 REPLACEMENT 2 Int BE Nuc !#5 N8511 P2599 MEMBAR !#5 N8512 P2600 BLD 18 -1 FP BE Pri !#5 N8513 P2601 MEMBAR !#5 N8514 P2602 BLD 21 -1 FP BE Pri !#5 N8515 P2602 BLD 22 -1 FP BE Pri !#A N8514 N8515 !#5 N8516 P2602 BLD 23 -1 FP BE Pri !#5 N8517 P2603 MEMBAR !#5 N8518 P2604 BLD 0 -1 FP BE Pri !#5 N8519 P2604 BLD 1 -1 FP BE Pri !#A N8518 N8519 !#5 N8520 P2604 BLD 2 -1 FP BE Pri !#5 N8521 P2604 BLD 3 -1 FP BE Pri !#5 N8522 P2604 BLD 4 -1 FP BE Pri !#5 N8523 P2605 MEMBAR !#5 N8524 P2606 REPLACEMENT 22 Int BE Sec !#5 N8525 P2607 LD 31 -1 FP BE Pri !#5 N8526 P2608 MEMBAR !#5 N8527 P2609 BST 11 0x42000077 FP BE Pri !#5 N8528 P2609 BST 12 0x42000078 FP BE Pri !#A N8527 N8528 !#5 N8529 P2609 BST 13 0x42000079 FP BE Pri !#5 N8530 P2610 MEMBAR !#5 N8531 P2611 BLD 0 -1 FP BE Pri !#5 N8532 P2611 BLD 1 -1 FP BE Pri !#A N8531 N8532 !#5 N8533 P2611 BLD 2 -1 FP BE Pri !#5 N8534 P2611 BLD 3 -1 FP BE Pri !#5 N8535 P2611 BLD 4 -1 FP BE Pri !#5 N8536 P2612 MEMBAR !#5 N8537 P2613 LD 1 -1 FP BE Pri !#5 N8538 P2614 MEMBAR !#5 N8539 P2615 BSTC 15 0x4200007a FP BE Sec !#5 N8540 P2616 MEMBAR !#5 N8541 P2617 ST 8 0x4200007b FP BE Pri !#5 N8542 P2618 MEMBAR !#5 N8543 P2619 BSTC 11 0x4200007c FP BE Pri !#5 N8544 P2619 BSTC 12 0x4200007d FP BE Pri !#A N8543 N8544 !#5 N8545 P2619 BSTC 13 0x4200007e FP BE Pri !#5 N8546 P2620 MEMBAR !#5 N8547 P2621 ST 27 0x4200007f FP BE Sec !#5 N8548 P2622 MEMBAR !#5 N8549 P2623 BLD 11 -1 FP BE Pri !#5 N8550 P2623 BLD 12 -1 FP BE Pri !#A N8549 N8550 !#5 N8551 P2623 BLD 13 -1 FP BE Pri !#5 N8552 P2624 MEMBAR !#5 N8553 P2625 REPLACEMENT 30 Int BE Nuc !#5 N8554 P2626 MEMBAR !#5 N8555 P2627 BSTC 0 0x42000080 FP BE Pri !#5 N8556 P2627 BSTC 1 0x42000081 FP BE Pri !#A N8555 N8556 !#5 N8557 P2627 BSTC 2 0x42000082 FP BE Pri !#5 N8558 P2627 BSTC 3 0x42000083 FP BE Pri !#5 N8559 P2627 BSTC 4 0x42000084 FP BE Pri !#5 N8560 P2628 MEMBAR !#5 N8561 P2629 REPLACEMENT 12 Int BE Pri !#5 N8562 P2630 MEMBAR !#5 N8563 P2631 BLD 11 -1 FP BE Pri !#5 N8564 P2631 BLD 12 -1 FP BE Pri !#A N8563 N8564 !#5 N8565 P2631 BLD 13 -1 FP BE Pri !#5 N8566 P2632 MEMBAR !#5 N8567 P2633 BSTC 20 0x42000085 FP BE Pri !#5 N8568 P2634 MEMBAR !#5 N8569 P2635 PREFETCH 18 Int BE Pri !#5 N8570 P2636 LD 19 -1 Int BE Pri Loop_exit !#5 N8571 P2226 MEMBAR !#5 N8572 P2227 BST 5 0x42000086 FP BE Pri !#5 N8573 P2227 BST 6 0x42000087 FP BE Pri !#5 N8574 P2228 MEMBAR !#5 N8575 P2229 BLD 11 -1 FP BE Sec !#5 N8576 P2229 BLD 12 -1 FP BE Sec !#A N8575 N8576 !#5 N8577 P2229 BLD 13 -1 FP BE Sec !#5 N8578 P2230 MEMBAR !#5 N8579 P2231 BST 11 0x42000088 FP BE Sec !#5 N8580 P2231 BST 12 0x42000089 FP BE Sec !#A N8579 N8580 !#5 N8581 P2231 BST 13 0x4200008a FP BE Sec !#5 N8582 P2232 MEMBAR !#5 N8583 P2233 ST 32 0x2800014 Int BE Nuc !#5 N8584 P2234 MEMBAR !#5 N8585 P2235 BLD 33 -1 FP BE Pri !#5 N8586 P2236 MEMBAR !#5 N8587 P2237 REPLACEMENT 27 Int BE Sec !#5 N8588 P2238 MEMBAR !#5 N8589 P2239 BLD 17 -1 FP BE Sec !#5 N8590 P2240 MEMBAR !#5 N8591 P2241 REPLACEMENT 23 Int BE Nuc !#5 N8592 P2242 MEMBAR !#5 N8593 P2243 BLD 20 -1 FP BE Pri !#5 N8594 P2244 MEMBAR !#5 N8595 P2245 BST 10 0x4200008b FP BE Pri !#5 N8596 P2246 MEMBAR !#5 N8597 P2247 ST 20 0x4200008c FP BE Pri !#5 N8598 P2248 PREFETCH 11 Int LE Pri !#5 N8599 P2249 ST 31 0x2800015 Int BE Pri !#5 N8600 P2250 LD 26 -1 FP BE Sec !#5 N8601 P2251 MEMBAR !#5 N8602 P2252 BLD 20 -1 FP BE Pri !#5 N8603 P2253 MEMBAR !#5 N8604 P2254 PREFETCH 7 Int BE Nuc !#5 N8605 P2255 MEMBAR !#5 N8606 P2256 BST 15 0x4200008d FP BE Pri !#5 N8607 P2257 MEMBAR !#5 N8608 P2258 BSTC 0 0x4200008e FP BE Pri !#5 N8609 P2258 BSTC 1 0x4200008f FP BE Pri !#A N8608 N8609 !#5 N8610 P2258 BSTC 2 0x42000090 FP BE Pri !#5 N8611 P2258 BSTC 3 0x42000091 FP BE Pri !#5 N8612 P2258 BSTC 4 0x42000092 FP BE Pri !#5 N8613 P2259 MEMBAR !#5 N8614 P2260 REPLACEMENT 13 Int BE Pri !#5 N8615 P2261 MEMBAR !#5 N8616 P2262 BST 11 0x42000093 FP BE Pri !#5 N8617 P2262 BST 12 0x42000094 FP BE Pri !#A N8616 N8617 !#5 N8618 P2262 BST 13 0x42000095 FP BE Pri !#5 N8619 P2263 MEMBAR !#5 N8620 P2264 ST 20 0x2800016 Int BE Pri !#5 N8621 P2265 MEMBAR !#5 N8622 P2266 BLD 10 -1 FP BE Pri !#5 N8623 P2267 MEMBAR !#5 N8624 P2268 REPLACEMENT 2 Int BE Pri !#5 N8625 P2269 MEMBAR !#5 N8626 P2270 BLD 5 -1 FP BE Sec !#5 N8627 P2270 BLD 6 -1 FP BE Sec !#5 N8628 P2271 MEMBAR !#5 N8629 P2272 PREFETCH 5 Int BE Nuc !#5 N8630 P2273 ST 13 0x42000096 FP BE Nuc !#5 N8631 P2274 REPLACEMENT 7 Int BE Pri !#5 N8632 P2275 LD 11 -1 Int BE Pri !#5 N8633 P2276 ST 12 0x2800017 Int BE Sec !#5 N8634 P2277 MEMBAR !#5 N8635 P2278 BLD 31 -1 FP BE Pri !#5 N8636 P2279 MEMBAR !#5 N8637 P2280 BST 20 0x42000097 FP BE Pri !#5 N8638 P2281 MEMBAR !#5 N8639 P2282 REPLACEMENT 19 Int BE Pri !#5 N8640 P2283 MEMBAR !#5 N8641 P2284 BST 17 0x42000098 FP BE Pri !#5 N8642 P2285 MEMBAR !#5 N8643 P2286 BST 16 0x42000099 FP BE Pri !#5 N8644 P2287 MEMBAR !#5 N8645 P2288 ST 11 0x2800018 Int BE Nuc !#5 N8646 P2289 REPLACEMENT 17 Int BE Pri !#5 N8647 P2290 REPLACEMENT 17 Int BE Pri !#5 N8648 P2291 MEMBAR !#5 N8649 P2292 BSTC 14 0x4200009a FP BE Sec !#5 N8650 P2293 MEMBAR !#5 N8651 P2294 BST 0 0x4200009b FP BE Pri !#5 N8652 P2294 BST 1 0x4200009c FP BE Pri !#A N8651 N8652 !#5 N8653 P2294 BST 2 0x4200009d FP BE Pri !#5 N8654 P2294 BST 3 0x4200009e FP BE Pri !#5 N8655 P2294 BST 4 0x4200009f FP BE Pri !#5 N8656 P2295 MEMBAR !#5 N8657 P2296 REPLACEMENT 13 Int BE Pri !#5 N8658 P2297 MEMBAR !#5 N8659 P2298 BST 20 0x420000a0 FP BE Pri !#5 N8660 P2299 MEMBAR !#5 N8661 P2300 BLD 8 -1 FP BE Pri !#5 N8662 P2300 BLD 9 -1 FP BE Pri !#5 N8663 P2301 MEMBAR !#5 N8664 P2302 LD 27 -1 FP BE Pri !#5 N8665 P2303 MEMBAR !#5 N8666 P2304 BLD 8 -1 FP BE Pri !#5 N8667 P2304 BLD 9 -1 FP BE Pri !#5 N8668 P2305 MEMBAR !#5 N8669 P2306 REPLACEMENT 25 Int BE Sec !#5 N8670 P2307 REPLACEMENT 5 Int BE Pri !#5 N8671 P2308 REPLACEMENT 15 Int BE Pri !#5 N8672 P2309 MEMBAR !#5 N8673 P2310 BLD 0 -1 FP BE Sec !#5 N8674 P2310 BLD 1 -1 FP BE Sec !#A N8673 N8674 !#5 N8675 P2310 BLD 2 -1 FP BE Sec !#5 N8676 P2310 BLD 3 -1 FP BE Sec !#5 N8677 P2310 BLD 4 -1 FP BE Sec !#5 N8678 P2311 MEMBAR !#5 N8679 P2312 LD 15 -1 Int BE Pri !#5 N8680 P2313 PREFETCH 0 Int BE Pri !#5 N8681 P2314 MEMBAR !#5 N8682 P2315 BLD 21 -1 FP BE Pri !#5 N8683 P2315 BLD 22 -1 FP BE Pri !#A N8682 N8683 !#5 N8684 P2315 BLD 23 -1 FP BE Pri !#5 N8685 P2316 MEMBAR !#5 N8686 P2317 BST 10 0x420000a1 FP BE Pri !#5 N8687 P2318 MEMBAR !#5 N8688 P2319 LD 13 -1 Int BE Pri !#5 N8689 P2320 MEMBAR !#5 N8690 P2321 BST 8 0x420000a2 FP BE Pri !#5 N8691 P2321 BST 9 0x420000a3 FP BE Pri !#5 N8692 P2322 MEMBAR !#5 N8693 P2323 REPLACEMENT 25 Int BE Sec !#5 N8694 P2324 LD 4 -1 FP BE Pri !#5 N8695 P2325 LD 14 -1 Int BE Pri !#5 N8696 P2326 PREFETCH 18 Int BE Sec !#5 N8697 P2327 IDC_FLIP 11 Int BE Pri !#5 N8698 P2328 ST 14 0x420000a4 FP BE Pri !#5 N8699 P2329 MEMBAR !#5 N8700 P2330 BST 24 0x420000a5 FP BE Pri !#5 N8701 P2330 BST 25 0x420000a6 FP BE Pri !#5 N8702 P2331 MEMBAR !#5 N8703 P2332 ST 3 0x2800019 Int BE Sec !#5 N8704 P2333 REPLACEMENT 9 Int BE Nuc !#5 N8705 P2334 REPLACEMENT 16 Int BE Pri !#5 N8706 P2335 PREFETCH 25 Int BE Pri !#5 N8707 P2336 MEMBAR !#5 N8708 P2337 BLD 8 -1 FP BE Pri !#5 N8709 P2337 BLD 9 -1 FP BE Pri !#5 N8710 P2338 MEMBAR !#5 N8711 P2339 LD 21 -1 FP BE Pri !#5 N8712 P2340 MEMBAR !#5 N8713 P2341 BLD 15 -1 FP BE Pri !#5 N8714 P2342 MEMBAR !#5 N8715 P2343 PREFETCH 3 Int BE Pri !#5 N8716 P2344 MEMBAR !#5 N8717 P2345 BLD 17 -1 FP BE Pri !#5 N8718 P2346 MEMBAR !#5 N8719 P2347 BST 31 0x420000a7 FP BE Pri !#5 N8720 P2348 MEMBAR !#5 N8721 P2349 ST 9 0x420000a8 FP BE Pri !#5 N8722 P2350 PREFETCH 8 Int BE Sec !#5 N8723 P2351 PREFETCH 22 Int BE Pri !#5 N8724 P2352 MEMBAR !#5 N8725 P2353 BLD 32 -1 FP BE Sec !#5 N8726 P2354 MEMBAR !#5 N8727 P2355 REPLACEMENT 18 Int BE Pri !#5 N8728 P2356 MEMBAR !#5 N8729 P2357 BST 11 0x420000a9 FP BE Pri !#5 N8730 P2357 BST 12 0x420000aa FP BE Pri !#A N8729 N8730 !#5 N8731 P2357 BST 13 0x420000ab FP BE Pri !#5 N8732 P2358 MEMBAR !#5 N8733 P2359 BLD 0 -1 FP BE Pri !#5 N8734 P2359 BLD 1 -1 FP BE Pri !#A N8733 N8734 !#5 N8735 P2359 BLD 2 -1 FP BE Pri !#5 N8736 P2359 BLD 3 -1 FP BE Pri !#5 N8737 P2359 BLD 4 -1 FP BE Pri !#5 N8738 P2360 MEMBAR !#5 N8739 P2361 BSTC 0 0x420000ac FP BE Sec !#5 N8740 P2361 BSTC 1 0x420000ad FP BE Sec !#A N8739 N8740 !#5 N8741 P2361 BSTC 2 0x420000ae FP BE Sec !#5 N8742 P2361 BSTC 3 0x420000af FP BE Sec !#5 N8743 P2361 BSTC 4 0x420000b0 FP BE Sec !#5 N8744 P2362 MEMBAR !#5 N8745 P2363 REPLACEMENT 13 Int BE Pri !#5 N8746 P2364 MEMBAR !#5 N8747 P2365 BLD 18 -1 FP BE Pri !#5 N8748 P2366 MEMBAR !#5 N8749 P2367 BLD 29 -1 FP BE Pri !#5 N8750 P2368 MEMBAR !#5 N8751 P2369 LD 14 -1 Int BE Pri !#5 N8752 P2370 LD 26 -1 Int BE Pri !#5 N8753 P2371 REPLACEMENT 1 Int BE Pri !#5 N8754 P2372 MEMBAR !#5 N8755 P2373 BSTC 14 0x420000b1 FP BE Sec !#5 N8756 P2374 MEMBAR !#5 N8757 P2375 BLD 0 -1 FP BE Sec !#5 N8758 P2375 BLD 1 -1 FP BE Sec !#A N8757 N8758 !#5 N8759 P2375 BLD 2 -1 FP BE Sec !#5 N8760 P2375 BLD 3 -1 FP BE Sec !#5 N8761 P2375 BLD 4 -1 FP BE Sec !#5 N8762 P2376 MEMBAR !#5 N8763 P2377 LD 11 -1 Int BE Pri !#5 N8764 P2378 MEMBAR !#5 N8765 P2379 BSTC 17 0x420000b2 FP BE Pri !#5 N8766 P2380 MEMBAR !#5 N8767 P2381 BSTC 32 0x420000b3 FP BE Pri !#5 N8768 P2382 MEMBAR !#5 N8769 P2383 BLD 21 -1 FP BE Pri !#5 N8770 P2383 BLD 22 -1 FP BE Pri !#A N8769 N8770 !#5 N8771 P2383 BLD 23 -1 FP BE Pri !#5 N8772 P2384 MEMBAR !#5 N8773 P2385 ST 13 0x280001a Int BE Nuc !#5 N8774 P2386 LD 26 -1 Int BE Pri !#5 N8775 P2387 REPLACEMENT 4 Int BE Pri !#5 N8776 P2388 MEMBAR !#5 N8777 P2389 BLD 32 -1 FP BE Pri !#5 N8778 P2390 MEMBAR !#5 N8779 P2391 ST 11 0x280001b Int BE Pri !#5 N8780 P2392 REPLACEMENT 7 Int BE Pri !#5 N8781 P2393 PREFETCH 26 Int BE Pri !#5 N8782 P2394 MEMBAR !#5 N8783 P2395 BSTC 10 0x420000b4 FP BE Pri !#5 N8784 P2396 MEMBAR !#5 N8785 P2397 BSTC 33 0x420000b5 FP BE Pri !#5 N8786 P2398 MEMBAR !#5 N8787 P2399 ST 18 0x420000b6 FP BE Pri !#5 N8788 P2400 REPLACEMENT 8 Int BE Pri !#5 N8789 P2401 MEMBAR !#5 N8790 P2402 BST 19 0x420000b7 FP BE Pri !#5 N8791 P2403 MEMBAR !#5 N8792 P2404 BSTC 24 0x420000b8 FP BE Pri !#5 N8793 P2404 BSTC 25 0x420000b9 FP BE Pri !#5 N8794 P2405 MEMBAR !#5 N8795 P2406 BLD 17 -1 FP BE Pri !#5 N8796 P2407 MEMBAR !#5 N8797 P2408 REPLACEMENT 23 Int BE Nuc !#5 N8798 P2409 REPLACEMENT 14 Int BE Pri !#5 N8799 P2410 MEMBAR !#5 N8800 P2411 BLD 26 -1 FP BE Pri !#5 N8801 P2411 BLD 27 -1 FP BE Pri !#5 N8802 P2412 MEMBAR !#5 N8803 P2413 BLD 11 -1 FP BE Pri !#5 N8804 P2413 BLD 12 -1 FP BE Pri !#A N8803 N8804 !#5 N8805 P2413 BLD 13 -1 FP BE Pri !#5 N8806 P2414 MEMBAR !#5 N8807 P2415 REPLACEMENT 30 Int BE Pri !#5 N8808 P2416 MEMBAR !#5 N8809 P2417 BLD 15 -1 FP BE Pri !#5 N8810 P2418 MEMBAR !#5 N8811 P2419 BSTC 0 0x420000ba FP BE Pri !#5 N8812 P2419 BSTC 1 0x420000bb FP BE Pri !#A N8811 N8812 !#5 N8813 P2419 BSTC 2 0x420000bc FP BE Pri !#5 N8814 P2419 BSTC 3 0x420000bd FP BE Pri !#5 N8815 P2419 BSTC 4 0x420000be FP BE Pri !#5 N8816 P2420 MEMBAR !#5 N8817 P2421 BSTC 26 0x420000bf FP BE Pri !#5 N8818 P2421 BSTC 27 0x420000c0 FP BE Pri !#5 N8819 P2422 MEMBAR !#5 N8820 P2423 REPLACEMENT 3 Int BE Pri !#5 N8821 P2424 ST 21 0x280001c Int BE Pri !#5 N8822 P2425 IDC_FLIP 29 Int BE Pri !#5 N8823 P2426 MEMBAR !#5 N8824 P2427 BSTC 0 0x420000c1 FP BE Pri !#5 N8825 P2427 BSTC 1 0x420000c2 FP BE Pri !#A N8824 N8825 !#5 N8826 P2427 BSTC 2 0x420000c3 FP BE Pri !#5 N8827 P2427 BSTC 3 0x420000c4 FP BE Pri !#5 N8828 P2427 BSTC 4 0x420000c5 FP BE Pri !#5 N8829 P2428 MEMBAR !#5 N8830 P2429 LD 33 -1 FP BE Pri !#5 N8831 P2430 MEMBAR !#5 N8832 P2431 BLD 5 -1 FP BE Pri !#5 N8833 P2431 BLD 6 -1 FP BE Pri !#5 N8834 P2432 MEMBAR !#5 N8835 P2433 ST 18 0x280001d Int BE Pri !#5 N8836 P2434 LD 8 -1 Int BE Sec !#5 N8837 P2435 MEMBAR !#5 N8838 P2436 BST 0 0x420000c6 FP BE Pri !#5 N8839 P2436 BST 1 0x420000c7 FP BE Pri !#A N8838 N8839 !#5 N8840 P2436 BST 2 0x420000c8 FP BE Pri !#5 N8841 P2436 BST 3 0x420000c9 FP BE Pri !#5 N8842 P2436 BST 4 0x420000ca FP BE Pri !#5 N8843 P2437 MEMBAR !#5 N8844 P2438 BST 26 0x420000cb FP BE Pri !#5 N8845 P2438 BST 27 0x420000cc FP BE Pri !#5 N8846 P2439 MEMBAR !#5 N8847 P2440 LD 5 -1 FP BE Pri !#5 N8848 P2441 MEMBAR !#5 N8849 P2442 BLD 16 -1 FP BE Sec !#5 N8850 P2443 MEMBAR !#5 N8851 P2444 BSTC 15 0x420000cd FP BE Sec !#5 N8852 P2445 MEMBAR !#5 N8853 P2446 PREFETCH 15 Int BE Sec !#5 N8854 P2447 MEMBAR !#5 N8855 P2448 BLD 31 -1 FP BE Sec !#5 N8856 P2449 MEMBAR !#5 N8857 P2450 BLD 29 -1 FP BE Pri !#5 N8858 P2451 MEMBAR !#5 N8859 P2452 PREFETCH 31 Int BE Pri !#5 N8860 P2453 ST 20 0x280001e Int BE Pri !#5 N8861 P2454 IDC_FLIP 0 Int BE Pri !#5 N8862 P2455 LD 9 -1 FP BE Pri !#5 N8863 P2456 MEMBAR !#5 N8864 P2457 BLD 32 -1 FP BE Pri !#5 N8865 P2458 MEMBAR !#5 N8866 P2459 LD 25 -1 FP BE Pri !#5 N8867 P2460 ST 19 0x280001f Int BE Pri !#5 N8868 P2461 ST 1 0x2800020 Int BE Pri !#5 N8869 P2462 PREFETCH 31 Int BE Pri !#5 N8870 P2463 LD 2 -1 FP BE Sec !#5 N8871 P2464 MEMBAR !#5 N8872 P2465 BSTC 24 0x420000ce FP BE Pri !#5 N8873 P2465 BSTC 25 0x420000cf FP BE Pri !#5 N8874 P2466 MEMBAR !#5 N8875 P2467 BLD 33 -1 FP BE Pri !#5 N8876 P2468 MEMBAR !#5 N8877 P2469 BSTC 32 0x420000d0 FP BE Sec !#5 N8878 P2470 MEMBAR !#5 N8879 P2471 ST 7 0x420000d1 FP BE Nuc !#5 N8880 P2472 REPLACEMENT 22 Int BE Pri !#5 N8881 P2473 MEMBAR !#5 N8882 P2474 BLD 8 -1 FP BE Pri !#5 N8883 P2474 BLD 9 -1 FP BE Pri !#5 N8884 P2475 MEMBAR !#5 N8885 P2476 BLD 11 -1 FP BE Pri !#5 N8886 P2476 BLD 12 -1 FP BE Pri !#A N8885 N8886 !#5 N8887 P2476 BLD 13 -1 FP BE Pri !#5 N8888 P2477 MEMBAR !#5 N8889 P2478 BLD 8 -1 FP BE Sec !#5 N8890 P2478 BLD 9 -1 FP BE Sec !#5 N8891 P2479 MEMBAR !#5 N8892 P2480 ST 15 0x2800021 Int BE Pri !#5 N8893 P2481 MEMBAR !#5 N8894 P2482 BLD 29 -1 FP BE Pri !#5 N8895 P2483 MEMBAR !#5 N8896 P2484 BLD 21 -1 FP BE Pri !#5 N8897 P2484 BLD 22 -1 FP BE Pri !#A N8896 N8897 !#5 N8898 P2484 BLD 23 -1 FP BE Pri !#5 N8899 P2485 MEMBAR !#5 N8900 P2486 BLD 18 -1 FP BE Pri !#5 N8901 P2487 MEMBAR !#5 N8902 P2488 PREFETCH 16 Int BE Pri !#5 N8903 P2489 LD 30 -1 FP BE Pri !#5 N8904 P2490 ST 19 0x2800022 Int BE Pri !#5 N8905 P2491 LD 26 -1 Int BE Pri !#5 N8906 P2492 REPLACEMENT 28 Int BE Pri !#5 N8907 P2493 ST 29 0x2800023 Int BE Nuc !#5 N8908 P2494 LD 28 -1 Int LE Pri !#5 N8909 P2495 LD 1 -1 Int BE Pri !#5 N8910 P2496 ST 16 0x2800024 Int BE Pri !#5 N8911 P2497 ST 20 0x420000d2 FP BE Nuc !#5 N8912 P2498 MEMBAR !#5 N8913 P2499 BSTC 0 0x420000d3 FP BE Pri !#5 N8914 P2499 BSTC 1 0x420000d4 FP BE Pri !#A N8913 N8914 !#5 N8915 P2499 BSTC 2 0x420000d5 FP BE Pri !#5 N8916 P2499 BSTC 3 0x420000d6 FP BE Pri !#5 N8917 P2499 BSTC 4 0x420000d7 FP BE Pri !#5 N8918 P2500 MEMBAR !#5 N8919 P2501 BLD 8 -1 FP BE Pri !#5 N8920 P2501 BLD 9 -1 FP BE Pri !#5 N8921 P2502 MEMBAR !#5 N8922 P2503 REPLACEMENT 5 Int BE Pri !#5 N8923 P2504 MEMBAR !#5 N8924 P2505 BLD 21 -1 FP BE Sec !#5 N8925 P2505 BLD 22 -1 FP BE Sec !#A N8924 N8925 !#5 N8926 P2505 BLD 23 -1 FP BE Sec !#5 N8927 P2506 MEMBAR !#5 N8928 P2507 ST 18 0x420000d8 FP BE Pri !#5 N8929 P2508 REPLACEMENT 18 Int BE Sec !#5 N8930 P2509 MEMBAR !#5 N8931 P2510 BST 11 0x420000d9 FP BE Pri !#5 N8932 P2510 BST 12 0x420000da FP BE Pri !#A N8931 N8932 !#5 N8933 P2510 BST 13 0x420000db FP BE Pri !#5 N8934 P2511 MEMBAR !#5 N8935 P2512 BLD 32 -1 FP BE Pri !#5 N8936 P2513 MEMBAR !#5 N8937 P2514 BLD 26 -1 FP BE Sec !#5 N8938 P2514 BLD 27 -1 FP BE Sec !#5 N8939 P2515 MEMBAR !#5 N8940 P2516 BLD 0 -1 FP BE Pri !#5 N8941 P2516 BLD 1 -1 FP BE Pri !#A N8940 N8941 !#5 N8942 P2516 BLD 2 -1 FP BE Pri !#5 N8943 P2516 BLD 3 -1 FP BE Pri !#5 N8944 P2516 BLD 4 -1 FP BE Pri !#5 N8945 P2517 MEMBAR !#5 N8946 P2518 LD 21 -1 FP BE Pri !#5 N8947 P2519 IDC_FLIP 23 Int BE Pri !#5 N8948 P2520 ST 3 0x420000dc FP BE Pri !#5 N8949 P2521 ST 28 0x420000dd FP BE Pri !#5 N8950 P2522 ST 27 0x420000de FP BE Pri !#5 N8951 P2523 REPLACEMENT 18 Int BE Sec !#5 N8952 P2524 LD 29 -1 FP BE Pri !#5 N8953 P2525 IDC_FLIP 20 Int BE Pri !#5 N8954 P2526 LD 3 -1 Int BE Pri !#5 N8955 P2527 PREFETCH 14 Int BE Pri !#5 N8956 P2528 ST 12 0x2800025 Int BE Pri !#5 N8957 P2529 PREFETCH 21 Int BE Pri !#5 N8958 P2530 REPLACEMENT 16 Int BE Pri !#5 N8959 P2531 ST 20 0x420000df FP BE Pri !#5 N8960 P2532 ST 6 0x2800026 Int BE Nuc !#5 N8961 P2533 REPLACEMENT 4 Int BE Pri !#5 N8962 P2534 REPLACEMENT 5 Int BE Sec !#5 N8963 P2535 MEMBAR !#5 N8964 P2536 BSTC 15 0x420000e0 FP BE Pri !#5 N8965 P2537 MEMBAR !#5 N8966 P2538 ST 22 0x420000e1 FP BE Pri !#5 N8967 P2539 ST 16 0x420000e2 FP BE Pri !#5 N8968 P2540 MEMBAR !#5 N8969 P2541 BST 21 0x420000e3 FP BE Sec !#5 N8970 P2541 BST 22 0x420000e4 FP BE Sec !#A N8969 N8970 !#5 N8971 P2541 BST 23 0x420000e5 FP BE Sec !#5 N8972 P2542 MEMBAR !#5 N8973 P2543 BST 5 0x420000e6 FP BE Pri !#5 N8974 P2543 BST 6 0x420000e7 FP BE Pri !#5 N8975 P2544 MEMBAR !#5 N8976 P2545 BLD 0 -1 FP BE Pri !#5 N8977 P2545 BLD 1 -1 FP BE Pri !#A N8976 N8977 !#5 N8978 P2545 BLD 2 -1 FP BE Pri !#5 N8979 P2545 BLD 3 -1 FP BE Pri !#5 N8980 P2545 BLD 4 -1 FP BE Pri !#5 N8981 P2546 MEMBAR !#5 N8982 P2547 BLD 5 -1 FP BE Pri !#5 N8983 P2547 BLD 6 -1 FP BE Pri !#5 N8984 P2548 MEMBAR !#5 N8985 P2549 BST 24 0x420000e8 FP BE Pri !#5 N8986 P2549 BST 25 0x420000e9 FP BE Pri !#5 N8987 P2550 MEMBAR !#5 N8988 P2551 REPLACEMENT 21 Int BE Pri !#5 N8989 P2552 REPLACEMENT 3 Int BE Pri !#5 N8990 P2553 MEMBAR !#5 N8991 P2554 BST 32 0x420000ea FP BE Pri !#5 N8992 P2555 MEMBAR !#5 N8993 P2556 PREFETCH 30 Int BE Pri !#5 N8994 P2557 MEMBAR !#5 N8995 P2558 BLD 0 -1 FP BE Pri !#5 N8996 P2558 BLD 1 -1 FP BE Pri !#A N8995 N8996 !#5 N8997 P2558 BLD 2 -1 FP BE Pri !#5 N8998 P2558 BLD 3 -1 FP BE Pri !#5 N8999 P2558 BLD 4 -1 FP BE Pri !#5 N9000 P2559 MEMBAR !#5 N9001 P2560 BST 14 0x420000eb FP BE Pri !#5 N9002 P2561 MEMBAR !#5 N9003 P2562 BLD 21 -1 FP BE Pri !#5 N9004 P2562 BLD 22 -1 FP BE Pri !#A N9003 N9004 !#5 N9005 P2562 BLD 23 -1 FP BE Pri !#5 N9006 P2563 MEMBAR !#5 N9007 P2564 BSTC 24 0x420000ec FP BE Pri !#5 N9008 P2564 BSTC 25 0x420000ed FP BE Pri !#5 N9009 P2565 MEMBAR !#5 N9010 P2566 BLD 11 -1 FP BE Pri !#5 N9011 P2566 BLD 12 -1 FP BE Pri !#A N9010 N9011 !#5 N9012 P2566 BLD 13 -1 FP BE Pri !#5 N9013 P2567 MEMBAR !#5 N9014 P2568 LD 10 -1 FP BE Pri !#5 N9015 P2569 MEMBAR !#5 N9016 P2570 BLD 21 -1 FP BE Sec !#5 N9017 P2570 BLD 22 -1 FP BE Sec !#A N9016 N9017 !#5 N9018 P2570 BLD 23 -1 FP BE Sec !#5 N9019 P2571 MEMBAR !#5 N9020 P2572 BLD 5 -1 FP BE Pri !#5 N9021 P2572 BLD 6 -1 FP BE Pri !#5 N9022 P2573 MEMBAR !#5 N9023 P2574 REPLACEMENT 7 Int BE Pri !#5 N9024 P2575 MEMBAR !#5 N9025 P2576 BST 21 0x420000ee FP BE Sec !#5 N9026 P2576 BST 22 0x420000ef FP BE Sec !#A N9025 N9026 !#5 N9027 P2576 BST 23 0x420000f0 FP BE Sec !#5 N9028 P2577 MEMBAR !#5 N9029 P2578 BLD 8 -1 FP BE Pri !#5 N9030 P2578 BLD 9 -1 FP BE Pri !#5 N9031 P2579 MEMBAR !#5 N9032 P2580 BSTC 26 0x420000f1 FP BE Pri !#5 N9033 P2580 BSTC 27 0x420000f2 FP BE Pri !#5 N9034 P2581 MEMBAR !#5 N9035 P2582 BSTC 0 0x420000f3 FP BE Pri !#5 N9036 P2582 BSTC 1 0x420000f4 FP BE Pri !#A N9035 N9036 !#5 N9037 P2582 BSTC 2 0x420000f5 FP BE Pri !#5 N9038 P2582 BSTC 3 0x420000f6 FP BE Pri !#5 N9039 P2582 BSTC 4 0x420000f7 FP BE Pri !#5 N9040 P2583 MEMBAR !#5 N9041 P2584 BLD 26 -1 FP BE Pri !#5 N9042 P2584 BLD 27 -1 FP BE Pri !#5 N9043 P2585 MEMBAR !#5 N9044 P2586 BLD 29 -1 FP BE Pri !#5 N9045 P2587 MEMBAR !#5 N9046 P2588 REPLACEMENT 33 Int BE Pri !#5 N9047 P2589 MEMBAR !#5 N9048 P2590 BST 15 0x420000f8 FP BE Pri !#5 N9049 P2591 MEMBAR !#5 N9050 P2592 LD 30 -1 FP BE Nuc !#5 N9051 P2593 MEMBAR !#5 N9052 P2594 BST 26 0x420000f9 FP BE Pri !#5 N9053 P2594 BST 27 0x420000fa FP BE Pri !#5 N9054 P2595 MEMBAR !#5 N9055 P2596 BSTC 30 0x420000fb FP BE Pri !#5 N9056 P2597 MEMBAR !#5 N9057 P2598 REPLACEMENT 2 Int BE Nuc !#5 N9058 P2599 MEMBAR !#5 N9059 P2600 BLD 18 -1 FP BE Pri !#5 N9060 P2601 MEMBAR !#5 N9061 P2602 BLD 21 -1 FP BE Pri !#5 N9062 P2602 BLD 22 -1 FP BE Pri !#A N9061 N9062 !#5 N9063 P2602 BLD 23 -1 FP BE Pri !#5 N9064 P2603 MEMBAR !#5 N9065 P2604 BLD 0 -1 FP BE Pri !#5 N9066 P2604 BLD 1 -1 FP BE Pri !#A N9065 N9066 !#5 N9067 P2604 BLD 2 -1 FP BE Pri !#5 N9068 P2604 BLD 3 -1 FP BE Pri !#5 N9069 P2604 BLD 4 -1 FP BE Pri !#5 N9070 P2605 MEMBAR !#5 N9071 P2606 REPLACEMENT 22 Int BE Sec !#5 N9072 P2607 LD 31 -1 FP BE Pri !#5 N9073 P2608 MEMBAR !#5 N9074 P2609 BST 11 0x420000fc FP BE Pri !#5 N9075 P2609 BST 12 0x420000fd FP BE Pri !#A N9074 N9075 !#5 N9076 P2609 BST 13 0x420000fe FP BE Pri !#5 N9077 P2610 MEMBAR !#5 N9078 P2611 BLD 0 -1 FP BE Pri !#5 N9079 P2611 BLD 1 -1 FP BE Pri !#A N9078 N9079 !#5 N9080 P2611 BLD 2 -1 FP BE Pri !#5 N9081 P2611 BLD 3 -1 FP BE Pri !#5 N9082 P2611 BLD 4 -1 FP BE Pri !#5 N9083 P2612 MEMBAR !#5 N9084 P2613 LD 1 -1 FP BE Pri !#5 N9085 P2614 MEMBAR !#5 N9086 P2615 BSTC 15 0x420000ff FP BE Sec !#5 N9087 P2616 MEMBAR !#5 N9088 P2617 ST 8 0x42000100 FP BE Pri !#5 N9089 P2618 MEMBAR !#5 N9090 P2619 BSTC 11 0x42000101 FP BE Pri !#5 N9091 P2619 BSTC 12 0x42000102 FP BE Pri !#A N9090 N9091 !#5 N9092 P2619 BSTC 13 0x42000103 FP BE Pri !#5 N9093 P2620 MEMBAR !#5 N9094 P2621 ST 27 0x42000104 FP BE Sec !#5 N9095 P2622 MEMBAR !#5 N9096 P2623 BLD 11 -1 FP BE Pri !#5 N9097 P2623 BLD 12 -1 FP BE Pri !#A N9096 N9097 !#5 N9098 P2623 BLD 13 -1 FP BE Pri !#5 N9099 P2624 MEMBAR !#5 N9100 P2625 REPLACEMENT 30 Int BE Nuc !#5 N9101 P2626 MEMBAR !#5 N9102 P2627 BSTC 0 0x42000105 FP BE Pri !#5 N9103 P2627 BSTC 1 0x42000106 FP BE Pri !#A N9102 N9103 !#5 N9104 P2627 BSTC 2 0x42000107 FP BE Pri !#5 N9105 P2627 BSTC 3 0x42000108 FP BE Pri !#5 N9106 P2627 BSTC 4 0x42000109 FP BE Pri !#5 N9107 P2628 MEMBAR !#5 N9108 P2629 REPLACEMENT 12 Int BE Pri !#5 N9109 P2630 MEMBAR !#5 N9110 P2631 BLD 11 -1 FP BE Pri !#5 N9111 P2631 BLD 12 -1 FP BE Pri !#A N9110 N9111 !#5 N9112 P2631 BLD 13 -1 FP BE Pri !#5 N9113 P2632 MEMBAR !#5 N9114 P2633 BSTC 20 0x4200010a FP BE Pri !#5 N9115 P2634 MEMBAR !#5 N9116 P2635 PREFETCH 18 Int BE Pri !#5 N9117 P2636 LD 19 -1 Int BE Pri Loop_exit !#5 N9118 P2226 MEMBAR !#5 N9119 P2227 BST 5 0x4200010b FP BE Pri !#5 N9120 P2227 BST 6 0x4200010c FP BE Pri !#5 N9121 P2228 MEMBAR !#5 N9122 P2229 BLD 11 -1 FP BE Sec !#5 N9123 P2229 BLD 12 -1 FP BE Sec !#A N9122 N9123 !#5 N9124 P2229 BLD 13 -1 FP BE Sec !#5 N9125 P2230 MEMBAR !#5 N9126 P2231 BST 11 0x4200010d FP BE Sec !#5 N9127 P2231 BST 12 0x4200010e FP BE Sec !#A N9126 N9127 !#5 N9128 P2231 BST 13 0x4200010f FP BE Sec !#5 N9129 P2232 MEMBAR !#5 N9130 P2233 ST 32 0x2800027 Int BE Nuc !#5 N9131 P2234 MEMBAR !#5 N9132 P2235 BLD 33 -1 FP BE Pri !#5 N9133 P2236 MEMBAR !#5 N9134 P2237 REPLACEMENT 27 Int BE Sec !#5 N9135 P2238 MEMBAR !#5 N9136 P2239 BLD 17 -1 FP BE Sec !#5 N9137 P2240 MEMBAR !#5 N9138 P2241 REPLACEMENT 23 Int BE Nuc !#5 N9139 P2242 MEMBAR !#5 N9140 P2243 BLD 20 -1 FP BE Pri !#5 N9141 P2244 MEMBAR !#5 N9142 P2245 BST 10 0x42000110 FP BE Pri !#5 N9143 P2246 MEMBAR !#5 N9144 P2247 ST 20 0x42000111 FP BE Pri !#5 N9145 P2248 PREFETCH 11 Int LE Pri !#5 N9146 P2249 ST 31 0x2800028 Int BE Pri !#5 N9147 P2250 LD 26 -1 FP BE Sec !#5 N9148 P2251 MEMBAR !#5 N9149 P2252 BLD 20 -1 FP BE Pri !#5 N9150 P2253 MEMBAR !#5 N9151 P2254 PREFETCH 7 Int BE Nuc !#5 N9152 P2255 MEMBAR !#5 N9153 P2256 BST 15 0x42000112 FP BE Pri !#5 N9154 P2257 MEMBAR !#5 N9155 P2258 BSTC 0 0x42000113 FP BE Pri !#5 N9156 P2258 BSTC 1 0x42000114 FP BE Pri !#A N9155 N9156 !#5 N9157 P2258 BSTC 2 0x42000115 FP BE Pri !#5 N9158 P2258 BSTC 3 0x42000116 FP BE Pri !#5 N9159 P2258 BSTC 4 0x42000117 FP BE Pri !#5 N9160 P2259 MEMBAR !#5 N9161 P2260 REPLACEMENT 13 Int BE Pri !#5 N9162 P2261 MEMBAR !#5 N9163 P2262 BST 11 0x42000118 FP BE Pri !#5 N9164 P2262 BST 12 0x42000119 FP BE Pri !#A N9163 N9164 !#5 N9165 P2262 BST 13 0x4200011a FP BE Pri !#5 N9166 P2263 MEMBAR !#5 N9167 P2264 ST 20 0x2800029 Int BE Pri !#5 N9168 P2265 MEMBAR !#5 N9169 P2266 BLD 10 -1 FP BE Pri !#5 N9170 P2267 MEMBAR !#5 N9171 P2268 REPLACEMENT 2 Int BE Pri !#5 N9172 P2269 MEMBAR !#5 N9173 P2270 BLD 5 -1 FP BE Sec !#5 N9174 P2270 BLD 6 -1 FP BE Sec !#5 N9175 P2271 MEMBAR !#5 N9176 P2272 PREFETCH 5 Int BE Nuc !#5 N9177 P2273 ST 13 0x4200011b FP BE Nuc !#5 N9178 P2274 REPLACEMENT 7 Int BE Pri !#5 N9179 P2275 LD 11 -1 Int BE Pri !#5 N9180 P2276 ST 12 0x280002a Int BE Sec !#5 N9181 P2277 MEMBAR !#5 N9182 P2278 BLD 31 -1 FP BE Pri !#5 N9183 P2279 MEMBAR !#5 N9184 P2280 BST 20 0x4200011c FP BE Pri !#5 N9185 P2281 MEMBAR !#5 N9186 P2282 REPLACEMENT 19 Int BE Pri !#5 N9187 P2283 MEMBAR !#5 N9188 P2284 BST 17 0x4200011d FP BE Pri !#5 N9189 P2285 MEMBAR !#5 N9190 P2286 BST 16 0x4200011e FP BE Pri !#5 N9191 P2287 MEMBAR !#5 N9192 P2288 ST 11 0x280002b Int BE Nuc !#5 N9193 P2289 REPLACEMENT 17 Int BE Pri !#5 N9194 P2290 REPLACEMENT 17 Int BE Pri !#5 N9195 P2291 MEMBAR !#5 N9196 P2292 BSTC 14 0x4200011f FP BE Sec !#5 N9197 P2293 MEMBAR !#5 N9198 P2294 BST 0 0x42000120 FP BE Pri !#5 N9199 P2294 BST 1 0x42000121 FP BE Pri !#A N9198 N9199 !#5 N9200 P2294 BST 2 0x42000122 FP BE Pri !#5 N9201 P2294 BST 3 0x42000123 FP BE Pri !#5 N9202 P2294 BST 4 0x42000124 FP BE Pri !#5 N9203 P2295 MEMBAR !#5 N9204 P2296 REPLACEMENT 13 Int BE Pri !#5 N9205 P2297 MEMBAR !#5 N9206 P2298 BST 20 0x42000125 FP BE Pri !#5 N9207 P2299 MEMBAR !#5 N9208 P2300 BLD 8 -1 FP BE Pri !#5 N9209 P2300 BLD 9 -1 FP BE Pri !#5 N9210 P2301 MEMBAR !#5 N9211 P2302 LD 27 -1 FP BE Pri !#5 N9212 P2303 MEMBAR !#5 N9213 P2304 BLD 8 -1 FP BE Pri !#5 N9214 P2304 BLD 9 -1 FP BE Pri !#5 N9215 P2305 MEMBAR !#5 N9216 P2306 REPLACEMENT 25 Int BE Sec !#5 N9217 P2307 REPLACEMENT 5 Int BE Pri !#5 N9218 P2308 REPLACEMENT 15 Int BE Pri !#5 N9219 P2309 MEMBAR !#5 N9220 P2310 BLD 0 -1 FP BE Sec !#5 N9221 P2310 BLD 1 -1 FP BE Sec !#A N9220 N9221 !#5 N9222 P2310 BLD 2 -1 FP BE Sec !#5 N9223 P2310 BLD 3 -1 FP BE Sec !#5 N9224 P2310 BLD 4 -1 FP BE Sec !#5 N9225 P2311 MEMBAR !#5 N9226 P2312 LD 15 -1 Int BE Pri !#5 N9227 P2313 PREFETCH 0 Int BE Pri !#5 N9228 P2314 MEMBAR !#5 N9229 P2315 BLD 21 -1 FP BE Pri !#5 N9230 P2315 BLD 22 -1 FP BE Pri !#A N9229 N9230 !#5 N9231 P2315 BLD 23 -1 FP BE Pri !#5 N9232 P2316 MEMBAR !#5 N9233 P2317 BST 10 0x42000126 FP BE Pri !#5 N9234 P2318 MEMBAR !#5 N9235 P2319 LD 13 -1 Int BE Pri !#5 N9236 P2320 MEMBAR !#5 N9237 P2321 BST 8 0x42000127 FP BE Pri !#5 N9238 P2321 BST 9 0x42000128 FP BE Pri !#5 N9239 P2322 MEMBAR !#5 N9240 P2323 REPLACEMENT 25 Int BE Sec !#5 N9241 P2324 LD 4 -1 FP BE Pri !#5 N9242 P2325 LD 14 -1 Int BE Pri !#5 N9243 P2326 PREFETCH 18 Int BE Sec !#5 N9244 P2327 IDC_FLIP 11 Int BE Pri !#5 N9245 P2328 ST 14 0x42000129 FP BE Pri !#5 N9246 P2329 MEMBAR !#5 N9247 P2330 BST 24 0x4200012a FP BE Pri !#5 N9248 P2330 BST 25 0x4200012b FP BE Pri !#5 N9249 P2331 MEMBAR !#5 N9250 P2332 ST 3 0x280002c Int BE Sec !#5 N9251 P2333 REPLACEMENT 9 Int BE Nuc !#5 N9252 P2334 REPLACEMENT 16 Int BE Pri !#5 N9253 P2335 PREFETCH 25 Int BE Pri !#5 N9254 P2336 MEMBAR !#5 N9255 P2337 BLD 8 -1 FP BE Pri !#5 N9256 P2337 BLD 9 -1 FP BE Pri !#5 N9257 P2338 MEMBAR !#5 N9258 P2339 LD 21 -1 FP BE Pri !#5 N9259 P2340 MEMBAR !#5 N9260 P2341 BLD 15 -1 FP BE Pri !#5 N9261 P2342 MEMBAR !#5 N9262 P2343 PREFETCH 3 Int BE Pri !#5 N9263 P2344 MEMBAR !#5 N9264 P2345 BLD 17 -1 FP BE Pri !#5 N9265 P2346 MEMBAR !#5 N9266 P2347 BST 31 0x4200012c FP BE Pri !#5 N9267 P2348 MEMBAR !#5 N9268 P2349 ST 9 0x4200012d FP BE Pri !#5 N9269 P2350 PREFETCH 8 Int BE Sec !#5 N9270 P2351 PREFETCH 22 Int BE Pri !#5 N9271 P2352 MEMBAR !#5 N9272 P2353 BLD 32 -1 FP BE Sec !#5 N9273 P2354 MEMBAR !#5 N9274 P2355 REPLACEMENT 18 Int BE Pri !#5 N9275 P2356 MEMBAR !#5 N9276 P2357 BST 11 0x4200012e FP BE Pri !#5 N9277 P2357 BST 12 0x4200012f FP BE Pri !#A N9276 N9277 !#5 N9278 P2357 BST 13 0x42000130 FP BE Pri !#5 N9279 P2358 MEMBAR !#5 N9280 P2359 BLD 0 -1 FP BE Pri !#5 N9281 P2359 BLD 1 -1 FP BE Pri !#A N9280 N9281 !#5 N9282 P2359 BLD 2 -1 FP BE Pri !#5 N9283 P2359 BLD 3 -1 FP BE Pri !#5 N9284 P2359 BLD 4 -1 FP BE Pri !#5 N9285 P2360 MEMBAR !#5 N9286 P2361 BSTC 0 0x42000131 FP BE Sec !#5 N9287 P2361 BSTC 1 0x42000132 FP BE Sec !#A N9286 N9287 !#5 N9288 P2361 BSTC 2 0x42000133 FP BE Sec !#5 N9289 P2361 BSTC 3 0x42000134 FP BE Sec !#5 N9290 P2361 BSTC 4 0x42000135 FP BE Sec !#5 N9291 P2362 MEMBAR !#5 N9292 P2363 REPLACEMENT 13 Int BE Pri !#5 N9293 P2364 MEMBAR !#5 N9294 P2365 BLD 18 -1 FP BE Pri !#5 N9295 P2366 MEMBAR !#5 N9296 P2367 BLD 29 -1 FP BE Pri !#5 N9297 P2368 MEMBAR !#5 N9298 P2369 LD 14 -1 Int BE Pri !#5 N9299 P2370 LD 26 -1 Int BE Pri !#5 N9300 P2371 REPLACEMENT 1 Int BE Pri !#5 N9301 P2372 MEMBAR !#5 N9302 P2373 BSTC 14 0x42000136 FP BE Sec !#5 N9303 P2374 MEMBAR !#5 N9304 P2375 BLD 0 -1 FP BE Sec !#5 N9305 P2375 BLD 1 -1 FP BE Sec !#A N9304 N9305 !#5 N9306 P2375 BLD 2 -1 FP BE Sec !#5 N9307 P2375 BLD 3 -1 FP BE Sec !#5 N9308 P2375 BLD 4 -1 FP BE Sec !#5 N9309 P2376 MEMBAR !#5 N9310 P2377 LD 11 -1 Int BE Pri !#5 N9311 P2378 MEMBAR !#5 N9312 P2379 BSTC 17 0x42000137 FP BE Pri !#5 N9313 P2380 MEMBAR !#5 N9314 P2381 BSTC 32 0x42000138 FP BE Pri !#5 N9315 P2382 MEMBAR !#5 N9316 P2383 BLD 21 -1 FP BE Pri !#5 N9317 P2383 BLD 22 -1 FP BE Pri !#A N9316 N9317 !#5 N9318 P2383 BLD 23 -1 FP BE Pri !#5 N9319 P2384 MEMBAR !#5 N9320 P2385 ST 13 0x280002d Int BE Nuc !#5 N9321 P2386 LD 26 -1 Int BE Pri !#5 N9322 P2387 REPLACEMENT 4 Int BE Pri !#5 N9323 P2388 MEMBAR !#5 N9324 P2389 BLD 32 -1 FP BE Pri !#5 N9325 P2390 MEMBAR !#5 N9326 P2391 ST 11 0x280002e Int BE Pri !#5 N9327 P2392 REPLACEMENT 7 Int BE Pri !#5 N9328 P2393 PREFETCH 26 Int BE Pri !#5 N9329 P2394 MEMBAR !#5 N9330 P2395 BSTC 10 0x42000139 FP BE Pri !#5 N9331 P2396 MEMBAR !#5 N9332 P2397 BSTC 33 0x4200013a FP BE Pri !#5 N9333 P2398 MEMBAR !#5 N9334 P2399 ST 18 0x4200013b FP BE Pri !#5 N9335 P2400 REPLACEMENT 8 Int BE Pri !#5 N9336 P2401 MEMBAR !#5 N9337 P2402 BST 19 0x4200013c FP BE Pri !#5 N9338 P2403 MEMBAR !#5 N9339 P2404 BSTC 24 0x4200013d FP BE Pri !#5 N9340 P2404 BSTC 25 0x4200013e FP BE Pri !#5 N9341 P2405 MEMBAR !#5 N9342 P2406 BLD 17 -1 FP BE Pri !#5 N9343 P2407 MEMBAR !#5 N9344 P2408 REPLACEMENT 23 Int BE Nuc !#5 N9345 P2409 REPLACEMENT 14 Int BE Pri !#5 N9346 P2410 MEMBAR !#5 N9347 P2411 BLD 26 -1 FP BE Pri !#5 N9348 P2411 BLD 27 -1 FP BE Pri !#5 N9349 P2412 MEMBAR !#5 N9350 P2413 BLD 11 -1 FP BE Pri !#5 N9351 P2413 BLD 12 -1 FP BE Pri !#A N9350 N9351 !#5 N9352 P2413 BLD 13 -1 FP BE Pri !#5 N9353 P2414 MEMBAR !#5 N9354 P2415 REPLACEMENT 30 Int BE Pri !#5 N9355 P2416 MEMBAR !#5 N9356 P2417 BLD 15 -1 FP BE Pri !#5 N9357 P2418 MEMBAR !#5 N9358 P2419 BSTC 0 0x4200013f FP BE Pri !#5 N9359 P2419 BSTC 1 0x42000140 FP BE Pri !#A N9358 N9359 !#5 N9360 P2419 BSTC 2 0x42000141 FP BE Pri !#5 N9361 P2419 BSTC 3 0x42000142 FP BE Pri !#5 N9362 P2419 BSTC 4 0x42000143 FP BE Pri !#5 N9363 P2420 MEMBAR !#5 N9364 P2421 BSTC 26 0x42000144 FP BE Pri !#5 N9365 P2421 BSTC 27 0x42000145 FP BE Pri !#5 N9366 P2422 MEMBAR !#5 N9367 P2423 REPLACEMENT 3 Int BE Pri !#5 N9368 P2424 ST 21 0x280002f Int BE Pri !#5 N9369 P2425 IDC_FLIP 29 Int BE Pri !#5 N9370 P2426 MEMBAR !#5 N9371 P2427 BSTC 0 0x42000146 FP BE Pri !#5 N9372 P2427 BSTC 1 0x42000147 FP BE Pri !#A N9371 N9372 !#5 N9373 P2427 BSTC 2 0x42000148 FP BE Pri !#5 N9374 P2427 BSTC 3 0x42000149 FP BE Pri !#5 N9375 P2427 BSTC 4 0x4200014a FP BE Pri !#5 N9376 P2428 MEMBAR !#5 N9377 P2429 LD 33 -1 FP BE Pri !#5 N9378 P2430 MEMBAR !#5 N9379 P2431 BLD 5 -1 FP BE Pri !#5 N9380 P2431 BLD 6 -1 FP BE Pri !#5 N9381 P2432 MEMBAR !#5 N9382 P2433 ST 18 0x2800030 Int BE Pri !#5 N9383 P2434 LD 8 -1 Int BE Sec !#5 N9384 P2435 MEMBAR !#5 N9385 P2436 BST 0 0x4200014b FP BE Pri !#5 N9386 P2436 BST 1 0x4200014c FP BE Pri !#A N9385 N9386 !#5 N9387 P2436 BST 2 0x4200014d FP BE Pri !#5 N9388 P2436 BST 3 0x4200014e FP BE Pri !#5 N9389 P2436 BST 4 0x4200014f FP BE Pri !#5 N9390 P2437 MEMBAR !#5 N9391 P2438 BST 26 0x42000150 FP BE Pri !#5 N9392 P2438 BST 27 0x42000151 FP BE Pri !#5 N9393 P2439 MEMBAR !#5 N9394 P2440 LD 5 -1 FP BE Pri !#5 N9395 P2441 MEMBAR !#5 N9396 P2442 BLD 16 -1 FP BE Sec !#5 N9397 P2443 MEMBAR !#5 N9398 P2444 BSTC 15 0x42000152 FP BE Sec !#5 N9399 P2445 MEMBAR !#5 N9400 P2446 PREFETCH 15 Int BE Sec !#5 N9401 P2447 MEMBAR !#5 N9402 P2448 BLD 31 -1 FP BE Sec !#5 N9403 P2449 MEMBAR !#5 N9404 P2450 BLD 29 -1 FP BE Pri !#5 N9405 P2451 MEMBAR !#5 N9406 P2452 PREFETCH 31 Int BE Pri !#5 N9407 P2453 ST 20 0x2800031 Int BE Pri !#5 N9408 P2454 IDC_FLIP 0 Int BE Pri !#5 N9409 P2455 LD 9 -1 FP BE Pri !#5 N9410 P2456 MEMBAR !#5 N9411 P2457 BLD 32 -1 FP BE Pri !#5 N9412 P2458 MEMBAR !#5 N9413 P2459 LD 25 -1 FP BE Pri !#5 N9414 P2460 ST 19 0x2800032 Int BE Pri !#5 N9415 P2461 ST 1 0x2800033 Int BE Pri !#5 N9416 P2462 PREFETCH 31 Int BE Pri !#5 N9417 P2463 LD 2 -1 FP BE Sec !#5 N9418 P2464 MEMBAR !#5 N9419 P2465 BSTC 24 0x42000153 FP BE Pri !#5 N9420 P2465 BSTC 25 0x42000154 FP BE Pri !#5 N9421 P2466 MEMBAR !#5 N9422 P2467 BLD 33 -1 FP BE Pri !#5 N9423 P2468 MEMBAR !#5 N9424 P2469 BSTC 32 0x42000155 FP BE Sec !#5 N9425 P2470 MEMBAR !#5 N9426 P2471 ST 7 0x42000156 FP BE Nuc !#5 N9427 P2472 REPLACEMENT 22 Int BE Pri !#5 N9428 P2473 MEMBAR !#5 N9429 P2474 BLD 8 -1 FP BE Pri !#5 N9430 P2474 BLD 9 -1 FP BE Pri !#5 N9431 P2475 MEMBAR !#5 N9432 P2476 BLD 11 -1 FP BE Pri !#5 N9433 P2476 BLD 12 -1 FP BE Pri !#A N9432 N9433 !#5 N9434 P2476 BLD 13 -1 FP BE Pri !#5 N9435 P2477 MEMBAR !#5 N9436 P2478 BLD 8 -1 FP BE Sec !#5 N9437 P2478 BLD 9 -1 FP BE Sec !#5 N9438 P2479 MEMBAR !#5 N9439 P2480 ST 15 0x2800034 Int BE Pri !#5 N9440 P2481 MEMBAR !#5 N9441 P2482 BLD 29 -1 FP BE Pri !#5 N9442 P2483 MEMBAR !#5 N9443 P2484 BLD 21 -1 FP BE Pri !#5 N9444 P2484 BLD 22 -1 FP BE Pri !#A N9443 N9444 !#5 N9445 P2484 BLD 23 -1 FP BE Pri !#5 N9446 P2485 MEMBAR !#5 N9447 P2486 BLD 18 -1 FP BE Pri !#5 N9448 P2487 MEMBAR !#5 N9449 P2488 PREFETCH 16 Int BE Pri !#5 N9450 P2489 LD 30 -1 FP BE Pri !#5 N9451 P2490 ST 19 0x2800035 Int BE Pri !#5 N9452 P2491 LD 26 -1 Int BE Pri !#5 N9453 P2492 REPLACEMENT 28 Int BE Pri !#5 N9454 P2493 ST 29 0x2800036 Int BE Nuc !#5 N9455 P2494 LD 28 -1 Int LE Pri !#5 N9456 P2495 LD 1 -1 Int BE Pri !#5 N9457 P2496 ST 16 0x2800037 Int BE Pri !#5 N9458 P2497 ST 20 0x42000157 FP BE Nuc !#5 N9459 P2498 MEMBAR !#5 N9460 P2499 BSTC 0 0x42000158 FP BE Pri !#5 N9461 P2499 BSTC 1 0x42000159 FP BE Pri !#A N9460 N9461 !#5 N9462 P2499 BSTC 2 0x4200015a FP BE Pri !#5 N9463 P2499 BSTC 3 0x4200015b FP BE Pri !#5 N9464 P2499 BSTC 4 0x4200015c FP BE Pri !#5 N9465 P2500 MEMBAR !#5 N9466 P2501 BLD 8 -1 FP BE Pri !#5 N9467 P2501 BLD 9 -1 FP BE Pri !#5 N9468 P2502 MEMBAR !#5 N9469 P2503 REPLACEMENT 5 Int BE Pri !#5 N9470 P2504 MEMBAR !#5 N9471 P2505 BLD 21 -1 FP BE Sec !#5 N9472 P2505 BLD 22 -1 FP BE Sec !#A N9471 N9472 !#5 N9473 P2505 BLD 23 -1 FP BE Sec !#5 N9474 P2506 MEMBAR !#5 N9475 P2507 ST 18 0x4200015d FP BE Pri !#5 N9476 P2508 REPLACEMENT 18 Int BE Sec !#5 N9477 P2509 MEMBAR !#5 N9478 P2510 BST 11 0x4200015e FP BE Pri !#5 N9479 P2510 BST 12 0x4200015f FP BE Pri !#A N9478 N9479 !#5 N9480 P2510 BST 13 0x42000160 FP BE Pri !#5 N9481 P2511 MEMBAR !#5 N9482 P2512 BLD 32 -1 FP BE Pri !#5 N9483 P2513 MEMBAR !#5 N9484 P2514 BLD 26 -1 FP BE Sec !#5 N9485 P2514 BLD 27 -1 FP BE Sec !#5 N9486 P2515 MEMBAR !#5 N9487 P2516 BLD 0 -1 FP BE Pri !#5 N9488 P2516 BLD 1 -1 FP BE Pri !#A N9487 N9488 !#5 N9489 P2516 BLD 2 -1 FP BE Pri !#5 N9490 P2516 BLD 3 -1 FP BE Pri !#5 N9491 P2516 BLD 4 -1 FP BE Pri !#5 N9492 P2517 MEMBAR !#5 N9493 P2518 LD 21 -1 FP BE Pri !#5 N9494 P2519 IDC_FLIP 23 Int BE Pri !#5 N9495 P2520 ST 3 0x42000161 FP BE Pri !#5 N9496 P2521 ST 28 0x42000162 FP BE Pri !#5 N9497 P2522 ST 27 0x42000163 FP BE Pri !#5 N9498 P2523 REPLACEMENT 18 Int BE Sec !#5 N9499 P2524 LD 29 -1 FP BE Pri !#5 N9500 P2525 IDC_FLIP 20 Int BE Pri !#5 N9501 P2526 LD 3 -1 Int BE Pri !#5 N9502 P2527 PREFETCH 14 Int BE Pri !#5 N9503 P2528 ST 12 0x2800038 Int BE Pri !#5 N9504 P2529 PREFETCH 21 Int BE Pri !#5 N9505 P2530 REPLACEMENT 16 Int BE Pri !#5 N9506 P2531 ST 20 0x42000164 FP BE Pri !#5 N9507 P2532 ST 6 0x2800039 Int BE Nuc !#5 N9508 P2533 REPLACEMENT 4 Int BE Pri !#5 N9509 P2534 REPLACEMENT 5 Int BE Sec !#5 N9510 P2535 MEMBAR !#5 N9511 P2536 BSTC 15 0x42000165 FP BE Pri !#5 N9512 P2537 MEMBAR !#5 N9513 P2538 ST 22 0x42000166 FP BE Pri !#5 N9514 P2539 ST 16 0x42000167 FP BE Pri !#5 N9515 P2540 MEMBAR !#5 N9516 P2541 BST 21 0x42000168 FP BE Sec !#5 N9517 P2541 BST 22 0x42000169 FP BE Sec !#A N9516 N9517 !#5 N9518 P2541 BST 23 0x4200016a FP BE Sec !#5 N9519 P2542 MEMBAR !#5 N9520 P2543 BST 5 0x4200016b FP BE Pri !#5 N9521 P2543 BST 6 0x4200016c FP BE Pri !#5 N9522 P2544 MEMBAR !#5 N9523 P2545 BLD 0 -1 FP BE Pri !#5 N9524 P2545 BLD 1 -1 FP BE Pri !#A N9523 N9524 !#5 N9525 P2545 BLD 2 -1 FP BE Pri !#5 N9526 P2545 BLD 3 -1 FP BE Pri !#5 N9527 P2545 BLD 4 -1 FP BE Pri !#5 N9528 P2546 MEMBAR !#5 N9529 P2547 BLD 5 -1 FP BE Pri !#5 N9530 P2547 BLD 6 -1 FP BE Pri !#5 N9531 P2548 MEMBAR !#5 N9532 P2549 BST 24 0x4200016d FP BE Pri !#5 N9533 P2549 BST 25 0x4200016e FP BE Pri !#5 N9534 P2550 MEMBAR !#5 N9535 P2551 REPLACEMENT 21 Int BE Pri !#5 N9536 P2552 REPLACEMENT 3 Int BE Pri !#5 N9537 P2553 MEMBAR !#5 N9538 P2554 BST 32 0x4200016f FP BE Pri !#5 N9539 P2555 MEMBAR !#5 N9540 P2556 PREFETCH 30 Int BE Pri !#5 N9541 P2557 MEMBAR !#5 N9542 P2558 BLD 0 -1 FP BE Pri !#5 N9543 P2558 BLD 1 -1 FP BE Pri !#A N9542 N9543 !#5 N9544 P2558 BLD 2 -1 FP BE Pri !#5 N9545 P2558 BLD 3 -1 FP BE Pri !#5 N9546 P2558 BLD 4 -1 FP BE Pri !#5 N9547 P2559 MEMBAR !#5 N9548 P2560 BST 14 0x42000170 FP BE Pri !#5 N9549 P2561 MEMBAR !#5 N9550 P2562 BLD 21 -1 FP BE Pri !#5 N9551 P2562 BLD 22 -1 FP BE Pri !#A N9550 N9551 !#5 N9552 P2562 BLD 23 -1 FP BE Pri !#5 N9553 P2563 MEMBAR !#5 N9554 P2564 BSTC 24 0x42000171 FP BE Pri !#5 N9555 P2564 BSTC 25 0x42000172 FP BE Pri !#5 N9556 P2565 MEMBAR !#5 N9557 P2566 BLD 11 -1 FP BE Pri !#5 N9558 P2566 BLD 12 -1 FP BE Pri !#A N9557 N9558 !#5 N9559 P2566 BLD 13 -1 FP BE Pri !#5 N9560 P2567 MEMBAR !#5 N9561 P2568 LD 10 -1 FP BE Pri !#5 N9562 P2569 MEMBAR !#5 N9563 P2570 BLD 21 -1 FP BE Sec !#5 N9564 P2570 BLD 22 -1 FP BE Sec !#A N9563 N9564 !#5 N9565 P2570 BLD 23 -1 FP BE Sec !#5 N9566 P2571 MEMBAR !#5 N9567 P2572 BLD 5 -1 FP BE Pri !#5 N9568 P2572 BLD 6 -1 FP BE Pri !#5 N9569 P2573 MEMBAR !#5 N9570 P2574 REPLACEMENT 7 Int BE Pri !#5 N9571 P2575 MEMBAR !#5 N9572 P2576 BST 21 0x42000173 FP BE Sec !#5 N9573 P2576 BST 22 0x42000174 FP BE Sec !#A N9572 N9573 !#5 N9574 P2576 BST 23 0x42000175 FP BE Sec !#5 N9575 P2577 MEMBAR !#5 N9576 P2578 BLD 8 -1 FP BE Pri !#5 N9577 P2578 BLD 9 -1 FP BE Pri !#5 N9578 P2579 MEMBAR !#5 N9579 P2580 BSTC 26 0x42000176 FP BE Pri !#5 N9580 P2580 BSTC 27 0x42000177 FP BE Pri !#5 N9581 P2581 MEMBAR !#5 N9582 P2582 BSTC 0 0x42000178 FP BE Pri !#5 N9583 P2582 BSTC 1 0x42000179 FP BE Pri !#A N9582 N9583 !#5 N9584 P2582 BSTC 2 0x4200017a FP BE Pri !#5 N9585 P2582 BSTC 3 0x4200017b FP BE Pri !#5 N9586 P2582 BSTC 4 0x4200017c FP BE Pri !#5 N9587 P2583 MEMBAR !#5 N9588 P2584 BLD 26 -1 FP BE Pri !#5 N9589 P2584 BLD 27 -1 FP BE Pri !#5 N9590 P2585 MEMBAR !#5 N9591 P2586 BLD 29 -1 FP BE Pri !#5 N9592 P2587 MEMBAR !#5 N9593 P2588 REPLACEMENT 33 Int BE Pri !#5 N9594 P2589 MEMBAR !#5 N9595 P2590 BST 15 0x4200017d FP BE Pri !#5 N9596 P2591 MEMBAR !#5 N9597 P2592 LD 30 -1 FP BE Nuc !#5 N9598 P2593 MEMBAR !#5 N9599 P2594 BST 26 0x4200017e FP BE Pri !#5 N9600 P2594 BST 27 0x4200017f FP BE Pri !#5 N9601 P2595 MEMBAR !#5 N9602 P2596 BSTC 30 0x42000180 FP BE Pri !#5 N9603 P2597 MEMBAR !#5 N9604 P2598 REPLACEMENT 2 Int BE Nuc !#5 N9605 P2599 MEMBAR !#5 N9606 P2600 BLD 18 -1 FP BE Pri !#5 N9607 P2601 MEMBAR !#5 N9608 P2602 BLD 21 -1 FP BE Pri !#5 N9609 P2602 BLD 22 -1 FP BE Pri !#A N9608 N9609 !#5 N9610 P2602 BLD 23 -1 FP BE Pri !#5 N9611 P2603 MEMBAR !#5 N9612 P2604 BLD 0 -1 FP BE Pri !#5 N9613 P2604 BLD 1 -1 FP BE Pri !#A N9612 N9613 !#5 N9614 P2604 BLD 2 -1 FP BE Pri !#5 N9615 P2604 BLD 3 -1 FP BE Pri !#5 N9616 P2604 BLD 4 -1 FP BE Pri !#5 N9617 P2605 MEMBAR !#5 N9618 P2606 REPLACEMENT 22 Int BE Sec !#5 N9619 P2607 LD 31 -1 FP BE Pri !#5 N9620 P2608 MEMBAR !#5 N9621 P2609 BST 11 0x42000181 FP BE Pri !#5 N9622 P2609 BST 12 0x42000182 FP BE Pri !#A N9621 N9622 !#5 N9623 P2609 BST 13 0x42000183 FP BE Pri !#5 N9624 P2610 MEMBAR !#5 N9625 P2611 BLD 0 -1 FP BE Pri !#5 N9626 P2611 BLD 1 -1 FP BE Pri !#A N9625 N9626 !#5 N9627 P2611 BLD 2 -1 FP BE Pri !#5 N9628 P2611 BLD 3 -1 FP BE Pri !#5 N9629 P2611 BLD 4 -1 FP BE Pri !#5 N9630 P2612 MEMBAR !#5 N9631 P2613 LD 1 -1 FP BE Pri !#5 N9632 P2614 MEMBAR !#5 N9633 P2615 BSTC 15 0x42000184 FP BE Sec !#5 N9634 P2616 MEMBAR !#5 N9635 P2617 ST 8 0x42000185 FP BE Pri !#5 N9636 P2618 MEMBAR !#5 N9637 P2619 BSTC 11 0x42000186 FP BE Pri !#5 N9638 P2619 BSTC 12 0x42000187 FP BE Pri !#A N9637 N9638 !#5 N9639 P2619 BSTC 13 0x42000188 FP BE Pri !#5 N9640 P2620 MEMBAR !#5 N9641 P2621 ST 27 0x42000189 FP BE Sec !#5 N9642 P2622 MEMBAR !#5 N9643 P2623 BLD 11 -1 FP BE Pri !#5 N9644 P2623 BLD 12 -1 FP BE Pri !#A N9643 N9644 !#5 N9645 P2623 BLD 13 -1 FP BE Pri !#5 N9646 P2624 MEMBAR !#5 N9647 P2625 REPLACEMENT 30 Int BE Nuc !#5 N9648 P2626 MEMBAR !#5 N9649 P2627 BSTC 0 0x4200018a FP BE Pri !#5 N9650 P2627 BSTC 1 0x4200018b FP BE Pri !#A N9649 N9650 !#5 N9651 P2627 BSTC 2 0x4200018c FP BE Pri !#5 N9652 P2627 BSTC 3 0x4200018d FP BE Pri !#5 N9653 P2627 BSTC 4 0x4200018e FP BE Pri !#5 N9654 P2628 MEMBAR !#5 N9655 P2629 REPLACEMENT 12 Int BE Pri !#5 N9656 P2630 MEMBAR !#5 N9657 P2631 BLD 11 -1 FP BE Pri !#5 N9658 P2631 BLD 12 -1 FP BE Pri !#A N9657 N9658 !#5 N9659 P2631 BLD 13 -1 FP BE Pri !#5 N9660 P2632 MEMBAR !#5 N9661 P2633 BSTC 20 0x4200018f FP BE Pri !#5 N9662 P2634 MEMBAR !#5 N9663 P2635 PREFETCH 18 Int BE Pri !#5 N9664 P2636 LD 19 -1 Int BE Pri Loop_exit !#5 N9665 P2637 MEMBAR !#6 N9666 P2638 MEMBAR !#6 N9667 P2639 BLD 10 -1 FP BE Sec !#6 N9668 P2640 MEMBAR !#6 N9669 P2641 BLD 7 -1 FP BE Sec !#6 N9670 P2642 MEMBAR !#6 N9671 P2643 PREFETCH 31 Int BE Nuc !#6 N9672 P2644 MEMBAR !#6 N9673 P2645 BLD 21 -1 FP BE Pri !#6 N9674 P2645 BLD 22 -1 FP BE Pri !#A N9673 N9674 !#6 N9675 P2645 BLD 23 -1 FP BE Pri !#6 N9676 P2646 MEMBAR !#6 N9677 P2647 LD 22 -1 Int BE Pri !#6 N9678 P2648 REPLACEMENT 21 Int BE Pri !#6 N9679 P2649 MEMBAR !#6 N9680 P2650 BLD 0 -1 FP BE Sec !#6 N9681 P2650 BLD 1 -1 FP BE Sec !#A N9680 N9681 !#6 N9682 P2650 BLD 2 -1 FP BE Sec !#6 N9683 P2650 BLD 3 -1 FP BE Sec !#6 N9684 P2650 BLD 4 -1 FP BE Sec !#6 N9685 P2651 MEMBAR !#6 N9686 P2652 BSTC 11 0x42800001 FP BE Pri !#6 N9687 P2652 BSTC 12 0x42800002 FP BE Pri !#A N9686 N9687 !#6 N9688 P2652 BSTC 13 0x42800003 FP BE Pri !#6 N9689 P2653 MEMBAR !#6 N9690 P2654 BLD 0 -1 FP BE Pri !#6 N9691 P2654 BLD 1 -1 FP BE Pri !#A N9690 N9691 !#6 N9692 P2654 BLD 2 -1 FP BE Pri !#6 N9693 P2654 BLD 3 -1 FP BE Pri !#6 N9694 P2654 BLD 4 -1 FP BE Pri !#6 N9695 P2655 MEMBAR !#6 N9696 P2656 REPLACEMENT 4 Int BE Pri !#6 N9697 P2657 MEMBAR !#6 N9698 P2658 BLD 21 -1 FP BE Pri !#6 N9699 P2658 BLD 22 -1 FP BE Pri !#A N9698 N9699 !#6 N9700 P2658 BLD 23 -1 FP BE Pri !#6 N9701 P2659 MEMBAR !#6 N9702 P2660 BLD 26 -1 FP BE Pri !#6 N9703 P2660 BLD 27 -1 FP BE Pri !#6 N9704 P2661 MEMBAR !#6 N9705 P2662 BST 8 0x42800004 FP BE Sec !#6 N9706 P2662 BST 9 0x42800005 FP BE Sec !#6 N9707 P2663 MEMBAR !#6 N9708 P2664 PREFETCH 33 Int BE Nuc !#6 N9709 P2665 LD 18 -1 Int BE Pri !#6 N9710 P2666 LD 6 -1 Int BE Pri !#6 N9711 P2667 MEMBAR !#6 N9712 P2668 BST 14 0x42800006 FP BE Pri !#6 N9713 P2669 MEMBAR !#6 N9714 P2670 LD 29 -1 FP BE Pri !#6 N9715 P2671 MEMBAR !#6 N9716 P2672 BLD 24 -1 FP BE Pri !#6 N9717 P2672 BLD 25 -1 FP BE Pri !#6 N9718 P2673 MEMBAR !#6 N9719 P2674 REPLACEMENT 12 Int BE Nuc !#6 N9720 P2675 IDC_FLIP 5 Int BE Pri !#6 N9721 P2676 LD 18 -1 Int BE Pri !#6 N9722 P2677 REPLACEMENT 24 Int BE Sec !#6 N9723 P2678 REPLACEMENT 30 Int BE Pri !#6 N9724 P2679 MEMBAR !#6 N9725 P2680 BSTC 32 0x42800007 FP BE Pri !#6 N9726 P2681 MEMBAR !#6 N9727 P2682 BLD 29 -1 FP BE Pri !#6 N9728 P2683 MEMBAR !#6 N9729 P2684 BST 32 0x42800008 FP BE Pri !#6 N9730 P2685 MEMBAR !#6 N9731 P2686 BLD 0 -1 FP BE Pri !#6 N9732 P2686 BLD 1 -1 FP BE Pri !#A N9731 N9732 !#6 N9733 P2686 BLD 2 -1 FP BE Pri !#6 N9734 P2686 BLD 3 -1 FP BE Pri !#6 N9735 P2686 BLD 4 -1 FP BE Pri !#6 N9736 P2687 MEMBAR !#6 N9737 P2688 REPLACEMENT 7 Int BE Pri !#6 N9738 P2689 MEMBAR !#6 N9739 P2690 BLD 29 -1 FP BE Pri !#6 N9740 P2691 MEMBAR !#6 N9741 P2692 LD 12 -1 FP BE Pri !#6 N9742 P2693 MEMBAR !#6 N9743 P2694 BST 5 0x42800009 FP BE Pri !#6 N9744 P2694 BST 6 0x4280000a FP BE Pri !#6 N9745 P2695 MEMBAR !#6 N9746 P2696 PREFETCH 14 Int BE Pri !#6 N9747 P2697 PREFETCH 1 Int BE Nuc !#6 N9748 P2698 LD 13 -1 Int LE Pri !#6 N9749 P2699 MEMBAR !#6 N9750 P2700 BST 21 0x4280000b FP BE Pri !#6 N9751 P2700 BST 22 0x4280000c FP BE Pri !#A N9750 N9751 !#6 N9752 P2700 BST 23 0x4280000d FP BE Pri !#6 N9753 P2701 MEMBAR !#6 N9754 P2702 BLD 8 -1 FP BE Pri !#6 N9755 P2702 BLD 9 -1 FP BE Pri !#6 N9756 P2703 MEMBAR !#6 N9757 P2704 LD 13 -1 FP BE Pri !#6 N9758 P2705 MEMBAR !#6 N9759 P2706 BST 8 0x4280000e FP BE Pri !#6 N9760 P2706 BST 9 0x4280000f FP BE Pri !#6 N9761 P2707 MEMBAR !#6 N9762 P2708 ST 13 0x42800010 FP BE Pri !#6 N9763 P2709 REPLACEMENT 32 Int BE Nuc !#6 N9764 P2710 REPLACEMENT 17 Int BE Pri !#6 N9765 P2711 REPLACEMENT 19 Int BE Pri !#6 N9766 P2712 MEMBAR !#6 N9767 P2713 BSTC 8 0x42800011 FP BE Pri !#6 N9768 P2713 BSTC 9 0x42800012 FP BE Pri !#6 N9769 P2714 MEMBAR !#6 N9770 P2715 MEMBAR !#6 N9771 P2716 LD 32 -1 Int BE Pri Loop_exit !#6 N9772 P2717 PREFETCH 31 Int BE Pri Loop_entry !#6 N9773 P2718 MEMBAR !#6 N9774 P2719 BLD 5 -1 FP BE Pri !#6 N9775 P2719 BLD 6 -1 FP BE Pri !#6 N9776 P2720 MEMBAR !#6 N9777 P2721 PREFETCH 24 Int BE Pri !#6 N9778 P2722 LD 24 -1 FP BE Nuc !#6 N9779 P2723 MEMBAR !#6 N9780 P2724 BLD 18 -1 FP BE Pri !#6 N9781 P2725 MEMBAR !#6 N9782 P2726 REPLACEMENT 10 Int BE Pri !#6 N9783 P2727 ST 12 0x3000001 Int BE Sec !#6 N9784 P2728 MEMBAR !#6 N9785 P2729 BSTC 24 0x42800013 FP BE Pri !#6 N9786 P2729 BSTC 25 0x42800014 FP BE Pri !#6 N9787 P2730 MEMBAR !#6 N9788 P2731 BLD 19 -1 FP BE Pri !#6 N9789 P2732 MEMBAR !#6 N9790 P2733 REPLACEMENT 31 Int BE Pri !#6 N9791 P2734 PREFETCH 22 Int BE Pri !#6 N9792 P2735 LD 8 -1 Int BE Pri !#6 N9793 P2736 MEMBAR !#6 N9794 P2737 BST 17 0x42800015 FP BE Pri !#6 N9795 P2738 MEMBAR !#6 N9796 P2739 ST 4 0x3000002 Int BE Pri !#6 N9797 P2740 PREFETCH 31 Int BE Sec !#6 N9798 P2741 PREFETCH 3 Int BE Pri !#6 N9799 P2742 ST 14 0x42800016 FP BE Pri !#6 N9800 P2743 MEMBAR !#6 N9801 P2744 BLD 11 -1 FP BE Pri !#6 N9802 P2744 BLD 12 -1 FP BE Pri !#A N9801 N9802 !#6 N9803 P2744 BLD 13 -1 FP BE Pri !#6 N9804 P2745 MEMBAR !#6 N9805 P2746 BSTC 7 0x42800017 FP BE Pri !#6 N9806 P2747 MEMBAR !#6 N9807 P2748 ST 33 0x42800018 FP BE Sec !#6 N9808 P2749 MEMBAR !#6 N9809 P2750 BLD 0 -1 FP BE Pri !#6 N9810 P2750 BLD 1 -1 FP BE Pri !#A N9809 N9810 !#6 N9811 P2750 BLD 2 -1 FP BE Pri !#6 N9812 P2750 BLD 3 -1 FP BE Pri !#6 N9813 P2750 BLD 4 -1 FP BE Pri !#6 N9814 P2751 MEMBAR !#6 N9815 P2752 PREFETCH 26 Int BE Pri !#6 N9816 P2753 ST 10 0x42800019 FP BE Nuc !#6 N9817 P2754 PREFETCH 6 Int BE Pri !#6 N9818 P2755 MEMBAR !#6 N9819 P2756 BLD 20 -1 FP BE Pri !#6 N9820 P2757 MEMBAR !#6 N9821 P2758 BLD 28 -1 FP BE Pri !#6 N9822 P2759 MEMBAR !#6 N9823 P2760 BLD 8 -1 FP BE Pri !#6 N9824 P2760 BLD 9 -1 FP BE Pri !#6 N9825 P2761 MEMBAR !#6 N9826 P2762 REPLACEMENT 26 Int BE Pri !#6 N9827 P2763 MEMBAR !#6 N9828 P2764 BSTC 20 0x4280001a FP BE Pri !#6 N9829 P2765 MEMBAR !#6 N9830 P2766 BST 5 0x4280001b FP BE Pri !#6 N9831 P2766 BST 6 0x4280001c FP BE Pri !#6 N9832 P2767 MEMBAR !#6 N9833 P2768 REPLACEMENT 1 Int BE Pri !#6 N9834 P2769 MEMBAR !#6 N9835 P2770 BLD 21 -1 FP BE Pri !#6 N9836 P2770 BLD 22 -1 FP BE Pri !#A N9835 N9836 !#6 N9837 P2770 BLD 23 -1 FP BE Pri !#6 N9838 P2771 MEMBAR !#6 N9839 P2772 ST 23 0x4280001d FP BE Pri !#6 N9840 P2773 LD 25 -1 Int BE Pri !#6 N9841 P2774 MEMBAR !#6 N9842 P2775 BLD 0 -1 FP BE Pri !#6 N9843 P2775 BLD 1 -1 FP BE Pri !#A N9842 N9843 !#6 N9844 P2775 BLD 2 -1 FP BE Pri !#6 N9845 P2775 BLD 3 -1 FP BE Pri !#6 N9846 P2775 BLD 4 -1 FP BE Pri !#6 N9847 P2776 MEMBAR !#6 N9848 P2777 BSTC 29 0x4280001e FP BE Pri !#6 N9849 P2778 MEMBAR !#6 N9850 P2779 PREFETCH 7 Int BE Pri !#6 N9851 P2780 MEMBAR !#6 N9852 P2781 BSTC 0 0x4280001f FP BE Sec !#6 N9853 P2781 BSTC 1 0x42800020 FP BE Sec !#A N9852 N9853 !#6 N9854 P2781 BSTC 2 0x42800021 FP BE Sec !#6 N9855 P2781 BSTC 3 0x42800022 FP BE Sec !#6 N9856 P2781 BSTC 4 0x42800023 FP BE Sec !#6 N9857 P2782 MEMBAR !#6 N9858 P2783 BLD 17 -1 FP BE Sec !#6 N9859 P2784 MEMBAR !#6 N9860 P2785 BST 24 0x42800024 FP BE Sec !#6 N9861 P2785 BST 25 0x42800025 FP BE Sec !#6 N9862 P2786 MEMBAR !#6 N9863 P2787 BSTC 26 0x42800026 FP BE Pri !#6 N9864 P2787 BSTC 27 0x42800027 FP BE Pri !#6 N9865 P2788 MEMBAR !#6 N9866 P2789 BST 10 0x42800028 FP BE Pri !#6 N9867 P2790 MEMBAR !#6 N9868 P2791 BLD 11 -1 FP BE Pri !#6 N9869 P2791 BLD 12 -1 FP BE Pri !#A N9868 N9869 !#6 N9870 P2791 BLD 13 -1 FP BE Pri !#6 N9871 P2792 MEMBAR !#6 N9872 P2793 BSTC 0 0x42800029 FP BE Pri !#6 N9873 P2793 BSTC 1 0x4280002a FP BE Pri !#A N9872 N9873 !#6 N9874 P2793 BSTC 2 0x4280002b FP BE Pri !#6 N9875 P2793 BSTC 3 0x4280002c FP BE Pri !#6 N9876 P2793 BSTC 4 0x4280002d FP BE Pri !#6 N9877 P2794 MEMBAR !#6 N9878 P2795 BLD 30 -1 FP BE Pri !#6 N9879 P2796 MEMBAR !#6 N9880 P2797 BSTC 21 0x4280002e FP BE Pri !#6 N9881 P2797 BSTC 22 0x4280002f FP BE Pri !#A N9880 N9881 !#6 N9882 P2797 BSTC 23 0x42800030 FP BE Pri !#6 N9883 P2798 MEMBAR !#6 N9884 P2799 BLD 0 -1 FP BE Pri !#6 N9885 P2799 BLD 1 -1 FP BE Pri !#A N9884 N9885 !#6 N9886 P2799 BLD 2 -1 FP BE Pri !#6 N9887 P2799 BLD 3 -1 FP BE Pri !#6 N9888 P2799 BLD 4 -1 FP BE Pri !#6 N9889 P2800 MEMBAR !#6 N9890 P2801 BLD 29 -1 FP BE Pri !#6 N9891 P2802 MEMBAR !#6 N9892 P2803 REPLACEMENT 31 Int BE Pri Loop_entry !#6 N9893 P2804 MEMBAR !#6 N9894 P2805 BLD 5 -1 FP BE Pri !#6 N9895 P2805 BLD 6 -1 FP BE Pri !#6 N9896 P2806 MEMBAR !#6 N9897 P2807 BSTC 21 0x42800031 FP BE Pri !#6 N9898 P2807 BSTC 22 0x42800032 FP BE Pri !#A N9897 N9898 !#6 N9899 P2807 BSTC 23 0x42800033 FP BE Pri !#6 N9900 P2808 MEMBAR !#6 N9901 P2809 MEMBAR !#6 N9902 P2810 REPLACEMENT 32 Int BE Pri !#6 N9903 P2811 MEMBAR !#6 N9904 P2812 BLD 0 -1 FP BE Sec !#6 N9905 P2812 BLD 1 -1 FP BE Sec !#A N9904 N9905 !#6 N9906 P2812 BLD 2 -1 FP BE Sec !#6 N9907 P2812 BLD 3 -1 FP BE Sec !#6 N9908 P2812 BLD 4 -1 FP BE Sec !#6 N9909 P2813 MEMBAR !#6 N9910 P2814 REPLACEMENT 31 Int BE Pri !#6 N9911 P2815 MEMBAR !#6 N9912 P2816 BLD 20 -1 FP BE Pri !#6 N9913 P2817 MEMBAR !#6 N9914 P2818 BLD 30 -1 FP BE Pri !#6 N9915 P2819 MEMBAR !#6 N9916 P2820 REPLACEMENT 6 Int BE Pri !#6 N9917 P2821 REPLACEMENT 27 Int BE Pri !#6 N9918 P2822 ST 3 0x3000003 Int BE Nuc !#6 N9919 P2823 PREFETCH 5 Int BE Pri !#6 N9920 P2824 MEMBAR !#6 N9921 P2825 BST 10 0x42800034 FP BE Pri !#6 N9922 P2826 MEMBAR !#6 N9923 P2827 BLD 28 -1 FP BE Sec !#6 N9924 P2828 MEMBAR !#6 N9925 P2829 BSTC 11 0x42800035 FP BE Sec !#6 N9926 P2829 BSTC 12 0x42800036 FP BE Sec !#A N9925 N9926 !#6 N9927 P2829 BSTC 13 0x42800037 FP BE Sec !#6 N9928 P2830 MEMBAR !#6 N9929 P2831 BLD 5 -1 FP BE Pri !#6 N9930 P2831 BLD 6 -1 FP BE Pri !#6 N9931 P2832 MEMBAR !#6 N9932 P2833 BLD 26 -1 FP BE Pri !#6 N9933 P2833 BLD 27 -1 FP BE Pri !#6 N9934 P2834 MEMBAR !#6 N9935 P2835 BST 0 0x42800038 FP BE Pri !#6 N9936 P2835 BST 1 0x42800039 FP BE Pri !#A N9935 N9936 !#6 N9937 P2835 BST 2 0x4280003a FP BE Pri !#6 N9938 P2835 BST 3 0x4280003b FP BE Pri !#6 N9939 P2835 BST 4 0x4280003c FP BE Pri !#6 N9940 P2836 MEMBAR !#6 N9941 P2837 BSTC 19 0x4280003d FP BE Pri !#6 N9942 P2838 MEMBAR !#6 N9943 P2839 MEMBAR !#6 N9944 P2840 BST 7 0x4280003e FP BE Pri !#6 N9945 P2841 MEMBAR !#6 N9946 P2842 BSTC 5 0x4280003f FP BE Pri !#6 N9947 P2842 BSTC 6 0x42800040 FP BE Pri !#6 N9948 P2843 MEMBAR !#6 N9949 P2844 PREFETCH 17 Int BE Sec !#6 N9950 P2845 MEMBAR !#6 N9951 P2846 BST 14 0x42800041 FP BE Sec !#6 N9952 P2847 MEMBAR !#6 N9953 P2848 BLD 7 -1 FP BE Pri !#6 N9954 P2849 MEMBAR !#6 N9955 P2850 ST 19 0x3000004 Int BE Pri !#6 N9956 P2851 MEMBAR !#6 N9957 P2852 BLD 17 -1 FP BE Pri !#6 N9958 P2853 MEMBAR !#6 N9959 P2854 BLD 21 -1 FP BE Pri !#6 N9960 P2854 BLD 22 -1 FP BE Pri !#A N9959 N9960 !#6 N9961 P2854 BLD 23 -1 FP BE Pri !#6 N9962 P2855 MEMBAR !#6 N9963 P2856 ST 18 0x3000005 Int BE Pri !#6 N9964 P2857 MEMBAR !#6 N9965 P2858 BSTC 18 0x42800042 FP BE Pri !#6 N9966 P2859 MEMBAR !#6 N9967 P2860 BST 31 0x42800043 FP BE Pri !#6 N9968 P2861 MEMBAR !#6 N9969 P2862 BST 21 0x42800044 FP BE Pri !#6 N9970 P2862 BST 22 0x42800045 FP BE Pri !#A N9969 N9970 !#6 N9971 P2862 BST 23 0x42800046 FP BE Pri !#6 N9972 P2863 MEMBAR !#6 N9973 P2864 BSTC 21 0x42800047 FP BE Pri !#6 N9974 P2864 BSTC 22 0x42800048 FP BE Pri !#A N9973 N9974 !#6 N9975 P2864 BSTC 23 0x42800049 FP BE Pri !#6 N9976 P2865 MEMBAR !#6 N9977 P2866 BSTC 14 0x4280004a FP BE Pri !#6 N9978 P2867 MEMBAR !#6 N9979 P2868 BST 5 0x4280004b FP BE Pri !#6 N9980 P2868 BST 6 0x4280004c FP BE Pri !#6 N9981 P2869 MEMBAR !#6 N9982 P2870 LD 22 -1 Int BE Sec !#6 N9983 P2871 LD 13 -1 FP BE Nuc !#6 N9984 P2872 MEMBAR !#6 N9985 P2873 BLD 24 -1 FP BE Pri !#6 N9986 P2873 BLD 25 -1 FP BE Pri !#6 N9987 P2874 MEMBAR !#6 N9988 P2875 BSTC 10 0x4280004d FP BE Pri !#6 N9989 P2876 MEMBAR !#6 N9990 P2877 REPLACEMENT 5 Int BE Nuc !#6 N9991 P2878 ST 19 0x4280004e FP BE Pri !#6 N9992 P2879 ST 3 0x4280004f FP BE Pri !#6 N9993 P2880 MEMBAR !#6 N9994 P2881 BST 26 0x42800050 FP BE Pri !#6 N9995 P2881 BST 27 0x42800051 FP BE Pri !#6 N9996 P2882 MEMBAR !#6 N9997 P2883 BLD 18 -1 FP BE Pri !#6 N9998 P2884 MEMBAR !#6 N9999 P2885 PREFETCH 28 Int BE Pri !#6 N10000 P2886 LD 33 -1 Int BE Pri !#6 N10001 P2887 ST 18 0x42800052 FP BE Sec !#6 N10002 P2888 MEMBAR !#6 N10003 P2889 BSTC 30 0x42800053 FP BE Pri !#6 N10004 P2890 MEMBAR !#6 N10005 P2891 BLD 24 -1 FP BE Pri !#6 N10006 P2891 BLD 25 -1 FP BE Pri !#6 N10007 P2892 MEMBAR !#6 N10008 P2893 LD 20 -1 FP BE Nuc !#6 N10009 P2894 REPLACEMENT 18 Int BE Pri !#6 N10010 P2895 IDC_FLIP 23 Int BE Pri !#6 N10011 P2896 MEMBAR !#6 N10012 P2897 BLD 20 -1 FP BE Sec !#6 N10013 P2898 MEMBAR !#6 N10014 P2899 REPLACEMENT 23 Int BE Pri !#6 N10015 P2900 LD 32 -1 Int BE Pri !#6 N10016 P2901 MEMBAR !#6 N10017 P2902 BST 0 0x42800054 FP BE Pri !#6 N10018 P2902 BST 1 0x42800055 FP BE Pri !#A N10017 N10018 !#6 N10019 P2902 BST 2 0x42800056 FP BE Pri !#6 N10020 P2902 BST 3 0x42800057 FP BE Pri !#6 N10021 P2902 BST 4 0x42800058 FP BE Pri !#6 N10022 P2903 MEMBAR !#6 N10023 P2904 BST 0 0x42800059 FP BE Pri !#6 N10024 P2904 BST 1 0x4280005a FP BE Pri !#A N10023 N10024 !#6 N10025 P2904 BST 2 0x4280005b FP BE Pri !#6 N10026 P2904 BST 3 0x4280005c FP BE Pri !#6 N10027 P2904 BST 4 0x4280005d FP BE Pri !#6 N10028 P2905 MEMBAR !#6 N10029 P2906 BLD 0 -1 FP BE Pri !#6 N10030 P2906 BLD 1 -1 FP BE Pri !#A N10029 N10030 !#6 N10031 P2906 BLD 2 -1 FP BE Pri !#6 N10032 P2906 BLD 3 -1 FP BE Pri !#6 N10033 P2906 BLD 4 -1 FP BE Pri !#6 N10034 P2907 MEMBAR !#6 N10035 P2908 BST 8 0x4280005e FP BE Pri !#6 N10036 P2908 BST 9 0x4280005f FP BE Pri !#6 N10037 P2909 MEMBAR !#6 N10038 P2910 PREFETCH 10 Int BE Pri !#6 N10039 P2911 REPLACEMENT 23 Int BE Pri !#6 N10040 P2912 ST 27 0x3000006 Int BE Nuc !#6 N10041 P2913 REPLACEMENT 2 Int BE Pri !#6 N10042 P2914 ST 9 0x42800060 FP BE Pri !#6 N10043 P2915 ST 30 0x3000007 Int BE Sec !#6 N10044 P2916 MEMBAR !#6 N10045 P2917 BLD 26 -1 FP BE Pri !#6 N10046 P2917 BLD 27 -1 FP BE Pri !#6 N10047 P2918 MEMBAR !#6 N10048 P2919 PREFETCH 24 Int BE Nuc !#6 N10049 P2920 ST 20 0x42800061 FP BE Pri !#6 N10050 P2921 MEMBAR !#6 N10051 P2922 BSTC 0 0x42800062 FP BE Pri !#6 N10052 P2922 BSTC 1 0x42800063 FP BE Pri !#A N10051 N10052 !#6 N10053 P2922 BSTC 2 0x42800064 FP BE Pri !#6 N10054 P2922 BSTC 3 0x42800065 FP BE Pri !#6 N10055 P2922 BSTC 4 0x42800066 FP BE Pri !#6 N10056 P2923 MEMBAR !#6 N10057 P2924 PREFETCH 32 Int BE Pri !#6 N10058 P2925 ST 0 0x42800067 FP BE Sec !#6 N10059 P2926 REPLACEMENT 0 Int BE Pri !#6 N10060 P2927 MEMBAR !#6 N10061 P2928 BLD 0 -1 FP BE Pri !#6 N10062 P2928 BLD 1 -1 FP BE Pri !#A N10061 N10062 !#6 N10063 P2928 BLD 2 -1 FP BE Pri !#6 N10064 P2928 BLD 3 -1 FP BE Pri !#6 N10065 P2928 BLD 4 -1 FP BE Pri !#6 N10066 P2929 MEMBAR !#6 N10067 P2930 LD 22 -1 FP BE Sec !#6 N10068 P2931 REPLACEMENT 9 Int BE Sec !#6 N10069 P2932 LD 26 -1 Int BE Pri !#6 N10070 P2933 PREFETCH 33 Int BE Nuc !#6 N10071 P2934 MEMBAR !#6 N10072 P2935 BST 11 0x42800068 FP BE Pri !#6 N10073 P2935 BST 12 0x42800069 FP BE Pri !#A N10072 N10073 !#6 N10074 P2935 BST 13 0x4280006a FP BE Pri !#6 N10075 P2936 MEMBAR !#6 N10076 P2937 LD 9 -1 Int BE Pri !#6 N10077 P2938 ST 29 0x4280006b FP BE Pri !#6 N10078 P2939 REPLACEMENT 1 Int BE Pri !#6 N10079 P2940 REPLACEMENT 25 Int BE Pri !#6 N10080 P2941 PREFETCH 12 Int BE Nuc !#6 N10081 P2942 MEMBAR !#6 N10082 P2943 BLD 0 -1 FP BE Pri !#6 N10083 P2943 BLD 1 -1 FP BE Pri !#A N10082 N10083 !#6 N10084 P2943 BLD 2 -1 FP BE Pri !#6 N10085 P2943 BLD 3 -1 FP BE Pri !#6 N10086 P2943 BLD 4 -1 FP BE Pri !#6 N10087 P2944 MEMBAR !#6 N10088 P2945 BLD 0 -1 FP BE Pri !#6 N10089 P2945 BLD 1 -1 FP BE Pri !#A N10088 N10089 !#6 N10090 P2945 BLD 2 -1 FP BE Pri !#6 N10091 P2945 BLD 3 -1 FP BE Pri !#6 N10092 P2945 BLD 4 -1 FP BE Pri !#6 N10093 P2946 MEMBAR !#6 N10094 P2947 BLD 28 -1 FP BE Sec !#6 N10095 P2948 MEMBAR !#6 N10096 P2949 LD 21 -1 FP BE Pri !#6 N10097 P2950 ST 10 0x4280006c FP BE Pri !#6 N10098 P2951 MEMBAR !#6 N10099 P2952 BLD 0 -1 FP BE Pri !#6 N10100 P2952 BLD 1 -1 FP BE Pri !#A N10099 N10100 !#6 N10101 P2952 BLD 2 -1 FP BE Pri !#6 N10102 P2952 BLD 3 -1 FP BE Pri !#6 N10103 P2952 BLD 4 -1 FP BE Pri !#6 N10104 P2953 MEMBAR !#6 N10105 P2954 BST 14 0x4280006d FP BE Pri !#6 N10106 P2955 MEMBAR !#6 N10107 P2956 BLD 21 -1 FP BE Pri !#6 N10108 P2956 BLD 22 -1 FP BE Pri !#A N10107 N10108 !#6 N10109 P2956 BLD 23 -1 FP BE Pri !#6 N10110 P2957 MEMBAR !#6 N10111 P2958 BLD 7 -1 FP BE Pri !#6 N10112 P2959 MEMBAR !#6 N10113 P2960 BST 20 0x4280006e FP BE Pri !#6 N10114 P2961 MEMBAR !#6 N10115 P2962 LD 15 -1 FP BE Sec !#6 N10116 P2963 MEMBAR !#6 N10117 P2964 BLD 33 -1 FP BE Pri !#6 N10118 P2965 MEMBAR !#6 N10119 P2966 BLD 28 -1 FP BE Sec !#6 N10120 P2967 MEMBAR !#6 N10121 P2968 PREFETCH 8 Int BE Pri !#6 N10122 P2969 MEMBAR !#6 N10123 P2970 BST 18 0x4280006f FP BE Sec !#6 N10124 P2971 MEMBAR !#6 N10125 P2972 BSTC 14 0x42800070 FP BE Pri !#6 N10126 P2973 MEMBAR !#6 N10127 P2974 BLD 0 -1 FP BE Pri !#6 N10128 P2974 BLD 1 -1 FP BE Pri !#A N10127 N10128 !#6 N10129 P2974 BLD 2 -1 FP BE Pri !#6 N10130 P2974 BLD 3 -1 FP BE Pri !#6 N10131 P2974 BLD 4 -1 FP BE Pri !#6 N10132 P2975 MEMBAR !#6 N10133 P2976 REPLACEMENT 30 Int BE Sec !#6 N10134 P2977 REPLACEMENT 3 Int BE Nuc !#6 N10135 P2978 ST 24 0x42800071 FP BE Pri !#6 N10136 P2979 ST 26 0x3000008 Int BE Nuc !#6 N10137 P2980 MEMBAR !#6 N10138 P2981 BST 14 0x42800072 FP BE Pri !#6 N10139 P2982 MEMBAR !#6 N10140 P2983 PREFETCH 16 Int BE Pri !#6 N10141 P2984 REPLACEMENT 19 Int BE Pri !#6 N10142 P2985 MEMBAR !#6 N10143 P2986 BST 10 0x42800073 FP BE Pri !#6 N10144 P2987 MEMBAR !#6 N10145 P2988 ST 5 0x42800074 FP BE Pri !#6 N10146 P2989 REPLACEMENT 14 Int BE Pri !#6 N10147 P2990 MEMBAR !#6 N10148 P2991 BST 11 0x42800075 FP BE Pri !#6 N10149 P2991 BST 12 0x42800076 FP BE Pri !#A N10148 N10149 !#6 N10150 P2991 BST 13 0x42800077 FP BE Pri !#6 N10151 P2992 MEMBAR !#6 N10152 P2993 PREFETCH 24 Int BE Pri !#6 N10153 P2994 MEMBAR !#6 N10154 P2995 BLD 18 -1 FP BE Pri !#6 N10155 P2996 MEMBAR !#6 N10156 P2997 BST 5 0x42800078 FP BE Pri !#6 N10157 P2997 BST 6 0x42800079 FP BE Pri !#6 N10158 P2998 MEMBAR !#6 N10159 P2999 BSTC 21 0x4280007a FP BE Pri !#6 N10160 P2999 BSTC 22 0x4280007b FP BE Pri !#A N10159 N10160 !#6 N10161 P2999 BSTC 23 0x4280007c FP BE Pri !#6 N10162 P3000 MEMBAR !#6 N10163 P3001 PREFETCH 19 Int BE Pri !#6 N10164 P3002 LD 14 -1 FP BE Pri !#6 N10165 P3003 REPLACEMENT 29 Int BE Pri !#6 N10166 P3004 MEMBAR !#6 N10167 P3005 BST 32 0x4280007d FP BE Pri !#6 N10168 P3006 MEMBAR !#6 N10169 P3007 PREFETCH 7 Int LE Pri !#6 N10170 P3008 MEMBAR !#6 N10171 P3009 BLD 10 -1 FP BE Sec !#6 N10172 P3010 MEMBAR !#6 N10173 P3011 BLD 21 -1 FP BE Pri !#6 N10174 P3011 BLD 22 -1 FP BE Pri !#A N10173 N10174 !#6 N10175 P3011 BLD 23 -1 FP BE Pri !#6 N10176 P3012 MEMBAR !#6 N10177 P3013 BSTC 26 0x4280007e FP BE Sec !#6 N10178 P3013 BSTC 27 0x4280007f FP BE Sec !#6 N10179 P3014 MEMBAR !#6 N10180 P3015 BLD 11 -1 FP BE Pri !#6 N10181 P3015 BLD 12 -1 FP BE Pri !#A N10180 N10181 !#6 N10182 P3015 BLD 13 -1 FP BE Pri !#6 N10183 P3016 MEMBAR !#6 N10184 P3017 LD 0 -1 FP BE Pri !#6 N10185 P3018 ST 19 0x3000009 Int BE Nuc !#6 N10186 P3019 MEMBAR !#6 N10187 P3020 BLD 21 -1 FP BE Pri !#6 N10188 P3020 BLD 22 -1 FP BE Pri !#A N10187 N10188 !#6 N10189 P3020 BLD 23 -1 FP BE Pri !#6 N10190 P3021 MEMBAR !#6 N10191 P3022 ST 31 0x42800080 FP BE Pri !#6 N10192 P3023 REPLACEMENT 23 Int BE Pri !#6 N10193 P3024 MEMBAR !#6 N10194 P3025 BLD 11 -1 FP BE Pri !#6 N10195 P3025 BLD 12 -1 FP BE Pri !#A N10194 N10195 !#6 N10196 P3025 BLD 13 -1 FP BE Pri !#6 N10197 P3026 MEMBAR !#6 N10198 P3027 REPLACEMENT 20 Int BE Pri !#6 N10199 P3028 REPLACEMENT 20 Int BE Nuc !#6 N10200 P3029 MEMBAR !#6 N10201 P3030 BST 5 0x42800081 FP BE Pri !#6 N10202 P3030 BST 6 0x42800082 FP BE Pri !#6 N10203 P3031 MEMBAR !#6 N10204 P3032 REPLACEMENT 12 Int BE Pri !#6 N10205 P3033 MEMBAR !#6 N10206 P3034 BLD 0 -1 FP BE Pri !#6 N10207 P3034 BLD 1 -1 FP BE Pri !#A N10206 N10207 !#6 N10208 P3034 BLD 2 -1 FP BE Pri !#6 N10209 P3034 BLD 3 -1 FP BE Pri !#6 N10210 P3034 BLD 4 -1 FP BE Pri !#6 N10211 P3035 MEMBAR !#6 N10212 P3036 PREFETCH 2 Int BE Pri !#6 N10213 P3037 LD 26 -1 Int BE Pri !#6 N10214 P3038 MEMBAR !#6 N10215 P3039 BLD 24 -1 FP BE Sec !#6 N10216 P3039 BLD 25 -1 FP BE Sec !#6 N10217 P3040 MEMBAR !#6 N10218 P3041 LD 24 -1 Int BE Pri !#6 N10219 P3042 REPLACEMENT 26 Int BE Nuc !#6 N10220 P3043 MEMBAR !#6 N10221 P3044 BLD 8 -1 FP BE Sec !#6 N10222 P3044 BLD 9 -1 FP BE Sec !#6 N10223 P3045 MEMBAR !#6 N10224 P3046 REPLACEMENT 8 Int BE Pri !#6 N10225 P3047 MEMBAR !#6 N10226 P3048 BSTC 26 0x42800083 FP BE Pri !#6 N10227 P3048 BSTC 27 0x42800084 FP BE Pri !#6 N10228 P3049 MEMBAR !#6 N10229 P3050 BLD 0 -1 FP BE Pri !#6 N10230 P3050 BLD 1 -1 FP BE Pri !#A N10229 N10230 !#6 N10231 P3050 BLD 2 -1 FP BE Pri !#6 N10232 P3050 BLD 3 -1 FP BE Pri !#6 N10233 P3050 BLD 4 -1 FP BE Pri !#6 N10234 P3051 MEMBAR !#6 N10235 P3052 PREFETCH 12 Int BE Pri !#6 N10236 P3053 MEMBAR !#6 N10237 P3054 BSTC 21 0x42800085 FP BE Pri !#6 N10238 P3054 BSTC 22 0x42800086 FP BE Pri !#A N10237 N10238 !#6 N10239 P3054 BSTC 23 0x42800087 FP BE Pri !#6 N10240 P3055 MEMBAR !#6 N10241 P3056 LD 31 -1 Int BE Nuc !#6 N10242 P3057 PREFETCH 7 Int BE Nuc !#6 N10243 P3058 REPLACEMENT 1 Int BE Pri !#6 N10244 P3059 MEMBAR !#6 N10245 P3060 BLD 16 -1 FP BE Pri !#6 N10246 P3061 MEMBAR !#6 N10247 P3062 BLD 29 -1 FP BE Pri !#6 N10248 P3063 MEMBAR !#6 N10249 P3064 PREFETCH 11 Int BE Pri !#6 N10250 P3065 REPLACEMENT 12 Int BE Pri !#6 N10251 P3066 MEMBAR !#6 N10252 P3067 BLD 24 -1 FP BE Pri !#6 N10253 P3067 BLD 25 -1 FP BE Pri !#6 N10254 P3068 MEMBAR !#6 N10255 P3069 REPLACEMENT 28 Int BE Nuc !#6 N10256 P3070 ST 25 0x42800088 FP BE Sec !#6 N10257 P3071 REPLACEMENT 14 Int BE Pri !#6 N10258 P3072 MEMBAR !#6 N10259 P3073 BST 8 0x42800089 FP BE Pri !#6 N10260 P3073 BST 9 0x4280008a FP BE Pri !#6 N10261 P3074 MEMBAR !#6 N10262 P3075 REPLACEMENT 15 Int BE Pri !#6 N10263 P3076 REPLACEMENT 7 Int BE Nuc !#6 N10264 P3077 MEMBAR !#6 N10265 P3078 BSTC 11 0x4280008b FP BE Pri !#6 N10266 P3078 BSTC 12 0x4280008c FP BE Pri !#A N10265 N10266 !#6 N10267 P3078 BSTC 13 0x4280008d FP BE Pri !#6 N10268 P3079 MEMBAR !#6 N10269 P3080 LD 31 -1 Int BE Sec !#6 N10270 P3081 LD 18 -1 FP BE Pri !#6 N10271 P3082 LD 16 -1 FP BE Sec !#6 N10272 P3083 MEMBAR !#6 N10273 P3084 BST 5 0x4280008e FP BE Pri !#6 N10274 P3084 BST 6 0x4280008f FP BE Pri !#6 N10275 P3085 MEMBAR !#6 N10276 P3086 BLD 24 -1 FP BE Pri !#6 N10277 P3086 BLD 25 -1 FP BE Pri !#6 N10278 P3087 MEMBAR !#6 N10279 P3088 IDC_FLIP 24 Int BE Pri !#6 N10280 P3089 MEMBAR !#6 N10281 P3090 BLD 15 -1 FP BE Pri !#6 N10282 P3091 MEMBAR !#6 N10283 P3092 BLD 16 -1 FP BE Pri !#6 N10284 P3093 MEMBAR !#6 N10285 P3094 REPLACEMENT 9 Int BE Pri !#6 N10286 P3095 MEMBAR !#6 N10287 P3096 BST 20 0x42800090 FP BE Pri !#6 N10288 P3097 MEMBAR !#6 N10289 P3098 ST 16 0x42800091 FP BE Sec !#6 N10290 P3099 LD 17 -1 Int BE Pri !#6 N10291 P3100 LD 23 -1 Int BE Pri !#6 N10292 P3101 IDC_FLIP 21 Int BE Pri !#6 N10293 P3102 MEMBAR !#6 N10294 P3103 BSTC 11 0x42800092 FP BE Pri !#6 N10295 P3103 BSTC 12 0x42800093 FP BE Pri !#A N10294 N10295 !#6 N10296 P3103 BSTC 13 0x42800094 FP BE Pri !#6 N10297 P3104 MEMBAR !#6 N10298 P3105 BSTC 29 0x42800095 FP BE Pri !#6 N10299 P3106 MEMBAR !#6 N10300 P3107 ST 21 0x42800096 FP BE Pri !#6 N10301 P3108 IDC_FLIP 21 Int BE Pri !#6 N10302 P3109 MEMBAR !#6 N10303 P3110 BSTC 0 0x42800097 FP BE Pri !#6 N10304 P3110 BSTC 1 0x42800098 FP BE Pri !#A N10303 N10304 !#6 N10305 P3110 BSTC 2 0x42800099 FP BE Pri !#6 N10306 P3110 BSTC 3 0x4280009a FP BE Pri !#6 N10307 P3110 BSTC 4 0x4280009b FP BE Pri !#6 N10308 P3111 MEMBAR !#6 N10309 P3112 LD 7 -1 Int LE Pri !#6 N10310 P3113 MEMBAR !#6 N10311 P3114 BLD 18 -1 FP BE Pri !#6 N10312 P3115 MEMBAR !#6 N10313 P3116 ST 14 0x4280009c FP BE Pri !#6 N10314 P3117 LD 13 -1 FP BE Sec !#6 N10315 P3118 MEMBAR !#6 N10316 P3119 BLD 0 -1 FP BE Pri !#6 N10317 P3119 BLD 1 -1 FP BE Pri !#A N10316 N10317 !#6 N10318 P3119 BLD 2 -1 FP BE Pri !#6 N10319 P3119 BLD 3 -1 FP BE Pri !#6 N10320 P3119 BLD 4 -1 FP BE Pri !#6 N10321 P3120 MEMBAR !#6 N10322 P3121 BST 0 0x4280009d FP BE Pri !#6 N10323 P3121 BST 1 0x4280009e FP BE Pri !#A N10322 N10323 !#6 N10324 P3121 BST 2 0x4280009f FP BE Pri !#6 N10325 P3121 BST 3 0x428000a0 FP BE Pri !#6 N10326 P3121 BST 4 0x428000a1 FP BE Pri !#6 N10327 P3122 MEMBAR !#6 N10328 P3123 BLD 30 -1 FP BE Pri !#6 N10329 P3124 MEMBAR !#6 N10330 P3125 BSTC 8 0x428000a2 FP BE Pri !#6 N10331 P3125 BSTC 9 0x428000a3 FP BE Pri !#6 N10332 P3126 MEMBAR !#6 N10333 P3127 REPLACEMENT 29 Int BE Pri !#6 N10334 P3128 REPLACEMENT 2 Int BE Pri !#6 N10335 P3129 MEMBAR !#6 N10336 P3130 BLD 26 -1 FP BE Pri !#6 N10337 P3130 BLD 27 -1 FP BE Pri !#6 N10338 P3131 MEMBAR !#6 N10339 P3132 BST 33 0x428000a4 FP BE Pri !#6 N10340 P3133 MEMBAR !#6 N10341 P3134 PREFETCH 31 Int BE Pri !#6 N10342 P3135 MEMBAR !#6 N10343 P3136 BLD 31 -1 FP BE Pri !#6 N10344 P3137 MEMBAR !#6 N10345 P3138 PREFETCH 22 Int BE Sec !#6 N10346 P3139 REPLACEMENT 5 Int BE Pri !#6 N10347 P3140 MEMBAR !#6 N10348 P3141 BLD 24 -1 FP BE Pri !#6 N10349 P3141 BLD 25 -1 FP BE Pri !#6 N10350 P3142 MEMBAR !#6 N10351 P3143 BSTC 21 0x428000a5 FP BE Sec !#6 N10352 P3143 BSTC 22 0x428000a6 FP BE Sec !#A N10351 N10352 !#6 N10353 P3143 BSTC 23 0x428000a7 FP BE Sec !#6 N10354 P3144 MEMBAR !#6 N10355 P3145 BSTC 24 0x428000a8 FP BE Pri !#6 N10356 P3145 BSTC 25 0x428000a9 FP BE Pri !#6 N10357 P3146 MEMBAR !#6 N10358 P3147 BLD 5 -1 FP BE Pri !#6 N10359 P3147 BLD 6 -1 FP BE Pri !#6 N10360 P3148 MEMBAR !#6 N10361 P3149 BST 32 0x428000aa FP BE Pri !#6 N10362 P3150 MEMBAR !#6 N10363 P3151 REPLACEMENT 24 Int BE Nuc !#6 N10364 P3152 ST 21 0x300000a Int BE Sec !#6 N10365 P3153 REPLACEMENT 31 Int BE Pri !#6 N10366 P3154 REPLACEMENT 21 Int BE Pri !#6 N10367 P3155 MEMBAR !#6 N10368 P3156 BLD 11 -1 FP BE Pri !#6 N10369 P3156 BLD 12 -1 FP BE Pri !#A N10368 N10369 !#6 N10370 P3156 BLD 13 -1 FP BE Pri !#6 N10371 P3157 MEMBAR !#6 N10372 P3158 LD 15 -1 Int BE Pri !#6 N10373 P3159 ST 1 0x428000ab FP BE Nuc !#6 N10374 P3160 MEMBAR !#6 N10375 P3161 BST 21 0x428000ac FP BE Pri !#6 N10376 P3161 BST 22 0x428000ad FP BE Pri !#A N10375 N10376 !#6 N10377 P3161 BST 23 0x428000ae FP BE Pri !#6 N10378 P3162 MEMBAR !#6 N10379 P3163 ST 4 0x300000b Int BE Pri !#6 N10380 P3164 MEMBAR !#6 N10381 P3165 BST 0 0x428000af FP BE Sec !#6 N10382 P3165 BST 1 0x428000b0 FP BE Sec !#A N10381 N10382 !#6 N10383 P3165 BST 2 0x428000b1 FP BE Sec !#6 N10384 P3165 BST 3 0x428000b2 FP BE Sec !#6 N10385 P3165 BST 4 0x428000b3 FP BE Sec !#6 N10386 P3166 MEMBAR !#6 N10387 P3167 REPLACEMENT 21 Int BE Pri !#6 N10388 P3168 LD 26 -1 Int BE Pri !#6 N10389 P3169 MEMBAR !#6 N10390 P3170 BLD 0 -1 FP BE Pri !#6 N10391 P3170 BLD 1 -1 FP BE Pri !#A N10390 N10391 !#6 N10392 P3170 BLD 2 -1 FP BE Pri !#6 N10393 P3170 BLD 3 -1 FP BE Pri !#6 N10394 P3170 BLD 4 -1 FP BE Pri !#6 N10395 P3171 MEMBAR !#6 N10396 P3172 PREFETCH 5 Int BE Pri !#6 N10397 P3173 REPLACEMENT 12 Int BE Pri !#6 N10398 P3174 REPLACEMENT 11 Int BE Sec !#6 N10399 P3175 PREFETCH 25 Int BE Sec !#6 N10400 P3176 MEMBAR !#6 N10401 P3177 BST 17 0x428000b4 FP BE Pri !#6 N10402 P3178 MEMBAR !#6 N10403 P3179 BLD 10 -1 FP BE Pri !#6 N10404 P3180 MEMBAR !#6 N10405 P3181 BST 15 0x428000b5 FP BE Pri !#6 N10406 P3182 MEMBAR !#6 N10407 P3183 ST 26 0x428000b6 FP BE Nuc !#6 N10408 P3184 MEMBAR !#6 N10409 P3185 BLD 11 -1 FP BE Pri !#6 N10410 P3185 BLD 12 -1 FP BE Pri !#A N10409 N10410 !#6 N10411 P3185 BLD 13 -1 FP BE Pri !#6 N10412 P3186 MEMBAR !#6 N10413 P3187 BLD 24 -1 FP BE Pri !#6 N10414 P3187 BLD 25 -1 FP BE Pri !#6 N10415 P3188 MEMBAR !#6 N10416 P3189 REPLACEMENT 27 Int BE Nuc !#6 N10417 P3190 MEMBAR !#6 N10418 P3191 BST 29 0x428000b7 FP BE Pri !#6 N10419 P3192 MEMBAR !#6 N10420 P3193 REPLACEMENT 10 Int BE Pri !#6 N10421 P3194 REPLACEMENT 7 Int BE Pri !#6 N10422 P3195 PREFETCH 30 Int BE Pri !#6 N10423 P3196 REPLACEMENT 33 Int BE Pri !#6 N10424 P3197 REPLACEMENT 13 Int BE Pri !#6 N10425 P3198 IDC_FLIP 13 Int BE Pri !#6 N10426 P3199 ST 29 0x428000b8 FP BE Pri !#6 N10427 P3200 FLUSHI 28 Int BE Pri !#6 N10428 P3201 PREFETCH 15 Int BE Pri !#6 N10429 P3202 REPLACEMENT 10 Int BE Sec !#6 N10430 P3203 REPLACEMENT 27 Int BE Sec !#6 N10431 P3204 IDC_FLIP 12 Int BE Pri !#6 N10432 P3205 LD 24 -1 Int BE Pri !#6 N10433 P3206 MEMBAR !#6 N10434 P3207 BLD 26 -1 FP BE Pri !#6 N10435 P3207 BLD 27 -1 FP BE Pri !#6 N10436 P3208 MEMBAR !#6 N10437 P3209 REPLACEMENT 3 Int BE Pri !#6 N10438 P3210 REPLACEMENT 30 Int BE Sec !#6 N10439 P3211 PREFETCH 12 Int BE Sec !#6 N10440 P3212 LD 1 -1 Int BE Pri !#6 N10441 P3213 REPLACEMENT 24 Int BE Pri !#6 N10442 P3214 ST 23 0x428000b9 FP BE Pri !#6 N10443 P3215 LD 26 -1 FP BE Pri !#6 N10444 P3216 ST 33 0x300000c Int BE Pri !#6 N10445 P3217 REPLACEMENT 12 Int BE Nuc !#6 N10446 P3218 MEMBAR !#6 N10447 P3219 BSTC 10 0x428000ba FP BE Pri !#6 N10448 P3220 MEMBAR !#6 N10449 P3221 BST 29 0x428000bb FP BE Pri !#6 N10450 P3222 MEMBAR !#6 N10451 P3223 BST 5 0x428000bc FP BE Pri !#6 N10452 P3223 BST 6 0x428000bd FP BE Pri !#6 N10453 P3224 MEMBAR !#6 N10454 P3225 BLD 14 -1 FP BE Pri !#6 N10455 P3226 MEMBAR !#6 N10456 P3227 REPLACEMENT 26 Int BE Pri !#6 N10457 P3228 REPLACEMENT 9 Int BE Nuc !#6 N10458 P3229 MEMBAR !#6 N10459 P3230 BSTC 17 0x428000be FP BE Pri !#6 N10460 P3231 MEMBAR !#6 N10461 P3232 BLD 32 -1 FP BE Pri !#6 N10462 P3233 MEMBAR !#6 N10463 P3234 BST 16 0x428000bf FP BE Pri !#6 N10464 P3235 MEMBAR !#6 N10465 P3236 ST 20 0x428000c0 FP BE Nuc !#6 N10466 P3237 MEMBAR !#6 N10467 P3238 BST 0 0x428000c1 FP BE Pri !#6 N10468 P3238 BST 1 0x428000c2 FP BE Pri !#A N10467 N10468 !#6 N10469 P3238 BST 2 0x428000c3 FP BE Pri !#6 N10470 P3238 BST 3 0x428000c4 FP BE Pri !#6 N10471 P3238 BST 4 0x428000c5 FP BE Pri !#6 N10472 P3239 MEMBAR !#6 N10473 P3240 ST 33 0x428000c6 FP BE Pri !#6 N10474 P3241 PREFETCH 22 Int BE Pri !#6 N10475 P3242 LD 14 -1 FP BE Pri !#6 N10476 P3243 REPLACEMENT 32 Int BE Pri !#6 N10477 P3244 PREFETCH 25 Int BE Sec !#6 N10478 P3245 MEMBAR !#6 N10479 P3246 BST 11 0x428000c7 FP BE Pri !#6 N10480 P3246 BST 12 0x428000c8 FP BE Pri !#A N10479 N10480 !#6 N10481 P3246 BST 13 0x428000c9 FP BE Pri !#6 N10482 P3247 MEMBAR !#6 N10483 P3248 REPLACEMENT 30 Int BE Pri !#6 N10484 P3249 LD 10 -1 Int BE Nuc !#6 N10485 P3250 ST 17 0x300000d Int BE Pri !#6 N10486 P3251 LD 4 -1 Int BE Sec !#6 N10487 P3252 LD 2 -1 FP BE Pri !#6 N10488 P3253 PREFETCH 15 Int BE Pri !#6 N10489 P3254 MEMBAR !#6 N10490 P3255 BLD 18 -1 FP BE Pri !#6 N10491 P3256 MEMBAR !#6 N10492 P3257 REPLACEMENT 16 Int BE Pri !#6 N10493 P3258 MEMBAR !#6 N10494 P3259 BSTC 24 0x428000ca FP BE Pri !#6 N10495 P3259 BSTC 25 0x428000cb FP BE Pri !#6 N10496 P3260 MEMBAR !#6 N10497 P3261 LD 21 -1 Int LE Pri !#6 N10498 P3262 MEMBAR !#6 N10499 P3263 BST 14 0x428000cc FP BE Pri !#6 N10500 P3264 MEMBAR !#6 N10501 P3265 REPLACEMENT 3 Int BE Sec !#6 N10502 P3266 ST 8 0x428000cd FP BE Pri !#6 N10503 P3267 ST 1 0x428000ce FP BE Sec !#6 N10504 P3268 MEMBAR !#6 N10505 P3269 BST 7 0x428000cf FP BE Pri !#6 N10506 P3270 MEMBAR !#6 N10507 P3271 BLD 26 -1 FP BE Pri !#6 N10508 P3271 BLD 27 -1 FP BE Pri !#6 N10509 P3272 MEMBAR !#6 N10510 P3273 BLD 30 -1 FP BE Pri !#6 N10511 P3274 MEMBAR !#6 N10512 P3275 BSTC 21 0x428000d0 FP BE Sec !#6 N10513 P3275 BSTC 22 0x428000d1 FP BE Sec !#A N10512 N10513 !#6 N10514 P3275 BSTC 23 0x428000d2 FP BE Sec !#6 N10515 P3276 MEMBAR !#6 N10516 P3277 LD 18 -1 FP BE Pri !#6 N10517 P3278 ST 15 0x428000d3 FP BE Pri !#6 N10518 P3279 PREFETCH 28 Int BE Pri !#6 N10519 P3280 PREFETCH 4 Int LE Sec !#6 N10520 P3281 MEMBAR !#6 N10521 P3282 BSTC 18 0x428000d4 FP BE Pri !#6 N10522 P3283 MEMBAR !#6 N10523 P3284 PREFETCH 31 Int BE Sec !#6 N10524 P3285 MEMBAR !#6 N10525 P3286 BLD 24 -1 FP BE Pri !#6 N10526 P3286 BLD 25 -1 FP BE Pri !#6 N10527 P3287 MEMBAR !#6 N10528 P3288 BSTC 30 0x428000d5 FP BE Sec !#6 N10529 P3289 MEMBAR !#6 N10530 P3290 BLD 5 -1 FP BE Sec !#6 N10531 P3290 BLD 6 -1 FP BE Sec !#6 N10532 P3291 MEMBAR !#6 N10533 P3292 BLD 20 -1 FP BE Pri !#6 N10534 P3293 MEMBAR !#6 N10535 P3294 BLD 24 -1 FP BE Pri !#6 N10536 P3294 BLD 25 -1 FP BE Pri !#6 N10537 P3295 MEMBAR !#6 N10538 P3296 BLD 28 -1 FP BE Pri !#6 N10539 P3297 MEMBAR !#6 N10540 P3298 ST 21 0x300000e Int BE Nuc !#6 N10541 P3299 REPLACEMENT 13 Int BE Pri !#6 N10542 P3300 MEMBAR !#6 N10543 P3301 BLD 29 -1 FP BE Pri !#6 N10544 P3302 MEMBAR !#6 N10545 P3303 BST 21 0x428000d6 FP BE Pri !#6 N10546 P3303 BST 22 0x428000d7 FP BE Pri !#A N10545 N10546 !#6 N10547 P3303 BST 23 0x428000d8 FP BE Pri !#6 N10548 P3304 MEMBAR !#6 N10549 P3305 BST 5 0x428000d9 FP BE Pri !#6 N10550 P3305 BST 6 0x428000da FP BE Pri !#6 N10551 P3306 MEMBAR !#6 N10552 P3307 ST 15 0x428000db FP BE Pri !#6 N10553 P3308 MEMBAR !#6 N10554 P3309 BST 16 0x428000dc FP BE Sec !#6 N10555 P3310 MEMBAR !#6 N10556 P3311 BLD 8 -1 FP BE Pri !#6 N10557 P3311 BLD 9 -1 FP BE Pri !#6 N10558 P3312 MEMBAR !#6 N10559 P3313 BST 19 0x428000dd FP BE Pri !#6 N10560 P3314 MEMBAR !#6 N10561 P3315 BLD 0 -1 FP BE Pri !#6 N10562 P3315 BLD 1 -1 FP BE Pri !#A N10561 N10562 !#6 N10563 P3315 BLD 2 -1 FP BE Pri !#6 N10564 P3315 BLD 3 -1 FP BE Pri !#6 N10565 P3315 BLD 4 -1 FP BE Pri !#6 N10566 P3316 MEMBAR !#6 N10567 P3317 ST 7 0x428000de FP BE Pri !#6 N10568 P3318 MEMBAR !#6 N10569 P3319 BSTC 0 0x428000df FP BE Pri !#6 N10570 P3319 BSTC 1 0x428000e0 FP BE Pri !#A N10569 N10570 !#6 N10571 P3319 BSTC 2 0x428000e1 FP BE Pri !#6 N10572 P3319 BSTC 3 0x428000e2 FP BE Pri !#6 N10573 P3319 BSTC 4 0x428000e3 FP BE Pri !#6 N10574 P3320 MEMBAR !#6 N10575 P3321 REPLACEMENT 7 Int BE Pri !#6 N10576 P3322 MEMBAR !#6 N10577 P3323 BSTC 28 0x428000e4 FP BE Pri !#6 N10578 P3324 MEMBAR !#6 N10579 P3325 BLD 0 -1 FP BE Pri !#6 N10580 P3325 BLD 1 -1 FP BE Pri !#A N10579 N10580 !#6 N10581 P3325 BLD 2 -1 FP BE Pri !#6 N10582 P3325 BLD 3 -1 FP BE Pri !#6 N10583 P3325 BLD 4 -1 FP BE Pri !#6 N10584 P3326 MEMBAR !#6 N10585 P3327 BSTC 8 0x428000e5 FP BE Pri !#6 N10586 P3327 BSTC 9 0x428000e6 FP BE Pri !#6 N10587 P3328 MEMBAR !#6 N10588 P3329 BLD 26 -1 FP BE Pri !#6 N10589 P3329 BLD 27 -1 FP BE Pri !#6 N10590 P3330 MEMBAR !#6 N10591 P3331 LD 17 -1 Int BE Sec !#6 N10592 P3332 MEMBAR !#6 N10593 P3333 BST 26 0x428000e7 FP BE Pri !#6 N10594 P3333 BST 27 0x428000e8 FP BE Pri !#6 N10595 P3334 MEMBAR !#6 N10596 P3335 FLUSHI 24 Int BE Pri !#6 N10597 P3336 REPLACEMENT 32 Int BE Pri !#6 N10598 P3337 PREFETCH 13 Int BE Sec !#6 N10599 P3338 MEMBAR !#6 N10600 P3339 BST 21 0x428000e9 FP BE Pri !#6 N10601 P3339 BST 22 0x428000ea FP BE Pri !#A N10600 N10601 !#6 N10602 P3339 BST 23 0x428000eb FP BE Pri !#6 N10603 P3340 MEMBAR !#6 N10604 P3341 BST 21 0x428000ec FP BE Pri !#6 N10605 P3341 BST 22 0x428000ed FP BE Pri !#A N10604 N10605 !#6 N10606 P3341 BST 23 0x428000ee FP BE Pri !#6 N10607 P3342 MEMBAR !#6 N10608 P3343 REPLACEMENT 12 Int BE Pri !#6 N10609 P3344 MEMBAR !#6 N10610 P3345 BLD 26 -1 FP BE Pri !#6 N10611 P3345 BLD 27 -1 FP BE Pri !#6 N10612 P3346 MEMBAR !#6 N10613 P3347 BLD 16 -1 FP BE Pri !#6 N10614 P3348 MEMBAR !#6 N10615 P3349 PREFETCH 31 Int BE Pri !#6 N10616 P3350 LD 25 -1 FP BE Pri !#6 N10617 P3351 MEMBAR !#6 N10618 P3352 BLD 21 -1 FP BE Pri !#6 N10619 P3352 BLD 22 -1 FP BE Pri !#A N10618 N10619 !#6 N10620 P3352 BLD 23 -1 FP BE Pri !#6 N10621 P3353 MEMBAR !#6 N10622 P3354 REPLACEMENT 7 Int BE Pri !#6 N10623 P3355 ST 22 0x300000f Int BE Pri !#6 N10624 P3356 PREFETCH 14 Int BE Nuc !#6 N10625 P3357 REPLACEMENT 27 Int BE Nuc !#6 N10626 P3358 REPLACEMENT 23 Int BE Sec !#6 N10627 P3359 MEMBAR !#6 N10628 P3360 BLD 24 -1 FP BE Pri !#6 N10629 P3360 BLD 25 -1 FP BE Pri !#6 N10630 P3361 MEMBAR !#6 N10631 P3362 LD 23 -1 Int BE Pri !#6 N10632 P3363 LD 16 -1 Int LE Nuc !#6 N10633 P3364 PREFETCH 19 Int BE Pri !#6 N10634 P3365 ST 26 0x3000010 Int BE Pri !#6 N10635 P3366 REPLACEMENT 23 Int BE Sec !#6 N10636 P3367 REPLACEMENT 17 Int BE Pri !#6 N10637 P3368 MEMBAR !#6 N10638 P3369 BST 11 0x428000ef FP BE Pri !#6 N10639 P3369 BST 12 0x428000f0 FP BE Pri !#A N10638 N10639 !#6 N10640 P3369 BST 13 0x428000f1 FP BE Pri !#6 N10641 P3370 MEMBAR !#6 N10642 P3371 BSTC 19 0x428000f2 FP BE Pri !#6 N10643 P3372 MEMBAR !#6 N10644 P3373 PREFETCH 16 Int BE Sec !#6 N10645 P3374 PREFETCH 19 Int BE Nuc !#6 N10646 P3375 MEMBAR !#6 N10647 P3376 BST 29 0x428000f3 FP BE Pri !#6 N10648 P3377 MEMBAR !#6 N10649 P3378 ST 3 0x428000f4 FP BE Sec !#6 N10650 P3379 REPLACEMENT 9 Int BE Pri !#6 N10651 P3380 REPLACEMENT 13 Int BE Pri !#6 N10652 P3381 MEMBAR !#6 N10653 P3382 BLD 11 -1 FP BE Pri !#6 N10654 P3382 BLD 12 -1 FP BE Pri !#A N10653 N10654 !#6 N10655 P3382 BLD 13 -1 FP BE Pri !#6 N10656 P3383 MEMBAR !#6 N10657 P3384 BLD 5 -1 FP BE Pri !#6 N10658 P3384 BLD 6 -1 FP BE Pri !#6 N10659 P3385 MEMBAR !#6 N10660 P3386 BLD 26 -1 FP BE Pri !#6 N10661 P3386 BLD 27 -1 FP BE Pri !#6 N10662 P3387 MEMBAR !#6 N10663 P3388 BLD 7 -1 FP BE Pri !#6 N10664 P3389 MEMBAR !#6 N10665 P3390 BLD 7 -1 FP BE Pri !#6 N10666 P3391 MEMBAR !#6 N10667 P3392 BLD 18 -1 FP BE Pri !#6 N10668 P3393 MEMBAR !#6 N10669 P3394 BLD 0 -1 FP BE Pri !#6 N10670 P3394 BLD 1 -1 FP BE Pri !#A N10669 N10670 !#6 N10671 P3394 BLD 2 -1 FP BE Pri !#6 N10672 P3394 BLD 3 -1 FP BE Pri !#6 N10673 P3394 BLD 4 -1 FP BE Pri !#6 N10674 P3395 MEMBAR !#6 N10675 P3396 MEMBAR !#6 N10676 P3397 BSTC 32 0x428000f5 FP BE Pri !#6 N10677 P3398 MEMBAR !#6 N10678 P3399 BST 17 0x428000f6 FP BE Pri !#6 N10679 P3400 MEMBAR !#6 N10680 P3401 BSTC 20 0x428000f7 FP BE Pri !#6 N10681 P3402 MEMBAR !#6 N10682 P3403 BLD 28 -1 FP BE Pri !#6 N10683 P3404 MEMBAR !#6 N10684 P3405 BLD 0 -1 FP BE Sec !#6 N10685 P3405 BLD 1 -1 FP BE Sec !#A N10684 N10685 !#6 N10686 P3405 BLD 2 -1 FP BE Sec !#6 N10687 P3405 BLD 3 -1 FP BE Sec !#6 N10688 P3405 BLD 4 -1 FP BE Sec !#6 N10689 P3406 MEMBAR !#6 N10690 P3407 BLD 29 -1 FP BE Pri !#6 N10691 P3408 MEMBAR !#6 N10692 P3409 ST 1 0x3000011 Int BE Pri !#6 N10693 P3410 ST 1 0x3000012 Int BE Sec !#6 N10694 P3411 REPLACEMENT 26 Int BE Pri !#6 N10695 P3412 MEMBAR !#6 N10696 P3413 BLD 11 -1 FP BE Pri !#6 N10697 P3413 BLD 12 -1 FP BE Pri !#A N10696 N10697 !#6 N10698 P3413 BLD 13 -1 FP BE Pri !#6 N10699 P3414 MEMBAR !#6 N10700 P3415 BST 15 0x428000f8 FP BE Pri !#6 N10701 P3416 MEMBAR !#6 N10702 P3417 BSTC 33 0x428000f9 FP BE Pri !#6 N10703 P3418 MEMBAR !#6 N10704 P3419 BSTC 8 0x428000fa FP BE Pri !#6 N10705 P3419 BSTC 9 0x428000fb FP BE Pri !#6 N10706 P3420 MEMBAR !#6 N10707 P3421 LD 9 -1 FP BE Sec !#6 N10708 P3422 MEMBAR !#6 N10709 P3423 BST 16 0x428000fc FP BE Pri !#6 N10710 P3424 MEMBAR !#6 N10711 P3425 ST 0 0x428000fd FP BE Nuc !#6 N10712 P3426 REPLACEMENT 31 Int BE Sec !#6 N10713 P3427 MEMBAR !#6 N10714 P3428 BSTC 21 0x428000fe FP BE Pri !#6 N10715 P3428 BSTC 22 0x428000ff FP BE Pri !#A N10714 N10715 !#6 N10716 P3428 BSTC 23 0x42800100 FP BE Pri !#6 N10717 P3429 MEMBAR !#6 N10718 P3430 BLD 10 -1 FP BE Pri !#6 N10719 P3431 MEMBAR !#6 N10720 P3432 BLD 11 -1 FP BE Pri !#6 N10721 P3432 BLD 12 -1 FP BE Pri !#A N10720 N10721 !#6 N10722 P3432 BLD 13 -1 FP BE Pri !#6 N10723 P3433 MEMBAR !#6 N10724 P3434 ST 25 0x42800101 FP BE Nuc !#6 N10725 P3435 LD 21 -1 Int BE Pri !#6 N10726 P3436 MEMBAR !#6 N10727 P3437 BST 21 0x42800102 FP BE Pri !#6 N10728 P3437 BST 22 0x42800103 FP BE Pri !#A N10727 N10728 !#6 N10729 P3437 BST 23 0x42800104 FP BE Pri !#6 N10730 P3438 MEMBAR !#6 N10731 P3439 BLD 19 -1 FP BE Pri !#6 N10732 P3440 MEMBAR !#6 N10733 P3441 PREFETCH 23 Int BE Nuc !#6 N10734 P3442 PREFETCH 16 Int BE Pri !#6 N10735 P3443 MEMBAR !#6 N10736 P3444 BST 21 0x42800105 FP BE Pri !#6 N10737 P3444 BST 22 0x42800106 FP BE Pri !#A N10736 N10737 !#6 N10738 P3444 BST 23 0x42800107 FP BE Pri !#6 N10739 P3445 MEMBAR !#6 N10740 P3446 BST 0 0x42800108 FP BE Pri !#6 N10741 P3446 BST 1 0x42800109 FP BE Pri !#A N10740 N10741 !#6 N10742 P3446 BST 2 0x4280010a FP BE Pri !#6 N10743 P3446 BST 3 0x4280010b FP BE Pri !#6 N10744 P3446 BST 4 0x4280010c FP BE Pri !#6 N10745 P3447 MEMBAR !#6 N10746 P3448 REPLACEMENT 11 Int BE Sec !#6 N10747 P3449 LD 3 -1 FP BE Pri !#6 N10748 P3450 ST 28 0x3000013 Int BE Pri !#6 N10749 P3451 LD 8 -1 Int LE Pri !#6 N10750 P3452 ST 6 0x4280010d FP BE Sec !#6 N10751 P3453 REPLACEMENT 6 Int BE Pri !#6 N10752 P3454 REPLACEMENT 1 Int BE Pri !#6 N10753 P3455 MEMBAR !#6 N10754 P3456 BSTC 0 0x4280010e FP BE Pri !#6 N10755 P3456 BSTC 1 0x4280010f FP BE Pri !#A N10754 N10755 !#6 N10756 P3456 BSTC 2 0x42800110 FP BE Pri !#6 N10757 P3456 BSTC 3 0x42800111 FP BE Pri !#6 N10758 P3456 BSTC 4 0x42800112 FP BE Pri !#6 N10759 P3457 MEMBAR !#6 N10760 P3458 BLD 8 -1 FP BE Pri !#6 N10761 P3458 BLD 9 -1 FP BE Pri !#6 N10762 P3459 MEMBAR !#6 N10763 P3460 ST 17 0x3000014 Int BE Nuc !#6 N10764 P3461 ST 32 0x42800113 FP BE Sec !#6 N10765 P3462 REPLACEMENT 17 Int BE Pri !#6 N10766 P3463 MEMBAR !#6 N10767 P3464 BSTC 11 0x42800114 FP BE Pri !#6 N10768 P3464 BSTC 12 0x42800115 FP BE Pri !#A N10767 N10768 !#6 N10769 P3464 BSTC 13 0x42800116 FP BE Pri !#6 N10770 P3465 MEMBAR !#6 N10771 P3466 BSTC 11 0x42800117 FP BE Pri !#6 N10772 P3466 BSTC 12 0x42800118 FP BE Pri !#A N10771 N10772 !#6 N10773 P3466 BSTC 13 0x42800119 FP BE Pri !#6 N10774 P3467 MEMBAR !#6 N10775 P3468 BSTC 11 0x4280011a FP BE Pri !#6 N10776 P3468 BSTC 12 0x4280011b FP BE Pri !#A N10775 N10776 !#6 N10777 P3468 BSTC 13 0x4280011c FP BE Pri !#6 N10778 P3469 MEMBAR !#6 N10779 P3470 LD 30 -1 Int BE Pri !#6 N10780 P3471 LD 26 -1 Int BE Pri !#6 N10781 P3472 MEMBAR !#6 N10782 P3473 BLD 21 -1 FP BE Pri !#6 N10783 P3473 BLD 22 -1 FP BE Pri !#A N10782 N10783 !#6 N10784 P3473 BLD 23 -1 FP BE Pri !#6 N10785 P3474 MEMBAR !#6 N10786 P3475 BSTC 11 0x4280011d FP BE Pri !#6 N10787 P3475 BSTC 12 0x4280011e FP BE Pri !#A N10786 N10787 !#6 N10788 P3475 BSTC 13 0x4280011f FP BE Pri !#6 N10789 P3476 MEMBAR !#6 N10790 P3477 BST 7 0x42800120 FP BE Sec !#6 N10791 P3478 MEMBAR !#6 N10792 P3479 BLD 11 -1 FP BE Sec !#6 N10793 P3479 BLD 12 -1 FP BE Sec !#A N10792 N10793 !#6 N10794 P3479 BLD 13 -1 FP BE Sec !#6 N10795 P3480 MEMBAR !#6 N10796 P3481 REPLACEMENT 13 Int BE Sec !#6 N10797 P3482 MEMBAR !#6 N10798 P3483 BST 21 0x42800121 FP BE Pri !#6 N10799 P3483 BST 22 0x42800122 FP BE Pri !#A N10798 N10799 !#6 N10800 P3483 BST 23 0x42800123 FP BE Pri !#6 N10801 P3484 MEMBAR !#6 N10802 P3485 REPLACEMENT 7 Int BE Nuc !#6 N10803 P3486 ST 24 0x42800124 FP BE Pri !#6 N10804 P3487 MEMBAR !#6 N10805 P3488 BLD 24 -1 FP BE Sec !#6 N10806 P3488 BLD 25 -1 FP BE Sec !#6 N10807 P3489 MEMBAR !#6 N10808 P3490 REPLACEMENT 8 Int BE Pri !#6 N10809 P3491 LD 3 -1 FP BE Sec !#6 N10810 P3492 REPLACEMENT 28 Int BE Pri !#6 N10811 P3493 REPLACEMENT 10 Int BE Sec !#6 N10812 P3494 PREFETCH 10 Int BE Nuc !#6 N10813 P3495 MEMBAR !#6 N10814 P3496 BSTC 21 0x42800125 FP BE Sec !#6 N10815 P3496 BSTC 22 0x42800126 FP BE Sec !#A N10814 N10815 !#6 N10816 P3496 BSTC 23 0x42800127 FP BE Sec !#6 N10817 P3497 MEMBAR !#6 N10818 P3498 BST 15 0x42800128 FP BE Pri !#6 N10819 P3499 MEMBAR !#6 N10820 P3500 BLD 19 -1 FP BE Pri !#6 N10821 P3501 MEMBAR !#6 N10822 P3502 ST 30 0x42800129 FP BE Pri !#6 N10823 P3503 ST 2 0x3000015 Int BE Pri !#6 N10824 P3504 MEMBAR !#6 N10825 P3505 BST 11 0x4280012a FP BE Pri !#6 N10826 P3505 BST 12 0x4280012b FP BE Pri !#A N10825 N10826 !#6 N10827 P3505 BST 13 0x4280012c FP BE Pri !#6 N10828 P3506 MEMBAR !#6 N10829 P3507 MEMBAR !#6 N10830 P3508 BST 10 0x4280012d FP BE Pri !#6 N10831 P3509 MEMBAR !#6 N10832 P3510 ST 4 0x3000016 Int BE Pri !#6 N10833 P3511 MEMBAR !#6 N10834 P3512 BST 21 0x4280012e FP BE Pri !#6 N10835 P3512 BST 22 0x4280012f FP BE Pri !#A N10834 N10835 !#6 N10836 P3512 BST 23 0x42800130 FP BE Pri !#6 N10837 P3513 MEMBAR !#6 N10838 P3514 BST 15 0x42800131 FP BE Pri !#6 N10839 P3515 MEMBAR !#6 N10840 P3516 BST 32 0x42800132 FP BE Pri !#6 N10841 P3517 MEMBAR !#6 N10842 P3518 BLD 10 -1 FP BE Pri !#6 N10843 P3519 MEMBAR !#6 N10844 P3520 LD 20 -1 Int BE Pri !#6 N10845 P3521 REPLACEMENT 27 Int BE Pri !#6 N10846 P3522 REPLACEMENT 33 Int BE Pri !#6 N10847 P3523 REPLACEMENT 19 Int BE Pri !#6 N10848 P3524 MEMBAR !#6 N10849 P3525 BST 17 0x42800133 FP BE Pri !#6 N10850 P3526 MEMBAR !#6 N10851 P3527 BSTC 24 0x42800134 FP BE Sec !#6 N10852 P3527 BSTC 25 0x42800135 FP BE Sec !#6 N10853 P3528 MEMBAR !#6 N10854 P3529 REPLACEMENT 25 Int BE Sec !#6 N10855 P3530 PREFETCH 6 Int BE Sec !#6 N10856 P3531 MEMBAR !#6 N10857 P3532 BLD 0 -1 FP BE Sec !#6 N10858 P3532 BLD 1 -1 FP BE Sec !#A N10857 N10858 !#6 N10859 P3532 BLD 2 -1 FP BE Sec !#6 N10860 P3532 BLD 3 -1 FP BE Sec !#6 N10861 P3532 BLD 4 -1 FP BE Sec !#6 N10862 P3533 MEMBAR !#6 N10863 P3534 ST 22 0x3000017 Int BE Pri !#6 N10864 P3535 MEMBAR !#6 N10865 P3536 BST 28 0x42800136 FP BE Pri !#6 N10866 P3537 MEMBAR !#6 N10867 P3538 LD 28 -1 Int BE Pri !#6 N10868 P3539 MEMBAR !#6 N10869 P3540 BST 11 0x42800137 FP BE Pri !#6 N10870 P3540 BST 12 0x42800138 FP BE Pri !#A N10869 N10870 !#6 N10871 P3540 BST 13 0x42800139 FP BE Pri !#6 N10872 P3541 MEMBAR !#6 N10873 P3542 BLD 24 -1 FP BE Pri !#6 N10874 P3542 BLD 25 -1 FP BE Pri !#6 N10875 P3543 MEMBAR !#6 N10876 P3544 LD 19 -1 FP BE Pri !#6 N10877 P3545 MEMBAR !#6 N10878 P3546 BST 7 0x4280013a FP BE Pri !#6 N10879 P3547 MEMBAR !#6 N10880 P3548 BSTC 21 0x4280013b FP BE Pri !#6 N10881 P3548 BSTC 22 0x4280013c FP BE Pri !#A N10880 N10881 !#6 N10882 P3548 BSTC 23 0x4280013d FP BE Pri !#6 N10883 P3549 MEMBAR !#6 N10884 P3550 LD 31 -1 Int BE Pri !#6 N10885 P3551 MEMBAR !#6 N10886 P3552 BLD 16 -1 FP BE Pri !#6 N10887 P3553 MEMBAR !#6 N10888 P3554 BSTC 32 0x4280013e FP BE Pri !#6 N10889 P3555 MEMBAR !#6 N10890 P3556 BLD 28 -1 FP BE Pri !#6 N10891 P3557 MEMBAR !#6 N10892 P3558 BST 21 0x4280013f FP BE Pri !#6 N10893 P3558 BST 22 0x42800140 FP BE Pri !#A N10892 N10893 !#6 N10894 P3558 BST 23 0x42800141 FP BE Pri !#6 N10895 P3559 MEMBAR !#6 N10896 P3560 BLD 24 -1 FP BE Pri !#6 N10897 P3560 BLD 25 -1 FP BE Pri !#6 N10898 P3561 MEMBAR !#6 N10899 P3562 LD 16 -1 Int BE Pri !#6 N10900 P3563 PREFETCH 26 Int BE Nuc !#6 N10901 P3564 LD 14 -1 FP BE Pri !#6 N10902 P3565 ST 9 0x42800142 FP BE Pri !#6 N10903 P3566 REPLACEMENT 3 Int BE Sec !#6 N10904 P3567 PREFETCH 4 Int BE Pri !#6 N10905 P3568 MEMBAR !#6 N10906 P3569 BSTC 15 0x42800143 FP BE Pri !#6 N10907 P3570 MEMBAR !#6 N10908 P3571 REPLACEMENT 19 Int BE Pri !#6 N10909 P3572 LD 8 -1 Int LE Pri !#6 N10910 P3573 REPLACEMENT 21 Int BE Pri !#6 N10911 P3574 MEMBAR !#6 N10912 P3575 BLD 28 -1 FP BE Pri !#6 N10913 P3576 MEMBAR !#6 N10914 P3577 BLD 26 -1 FP BE Pri !#6 N10915 P3577 BLD 27 -1 FP BE Pri !#6 N10916 P3578 MEMBAR !#6 N10917 P3579 FLUSHI 11 Int BE Pri !#6 N10918 P3580 MEMBAR !#6 N10919 P3581 BST 21 0x42800144 FP BE Pri !#6 N10920 P3581 BST 22 0x42800145 FP BE Pri !#A N10919 N10920 !#6 N10921 P3581 BST 23 0x42800146 FP BE Pri !#6 N10922 P3582 MEMBAR !#6 N10923 P3583 BLD 30 -1 FP BE Sec !#6 N10924 P3584 MEMBAR !#6 N10925 P3585 BLD 31 -1 FP BE Pri !#6 N10926 P3586 MEMBAR !#6 N10927 P3587 BST 16 0x42800147 FP BE Pri !#6 N10928 P3588 MEMBAR !#6 N10929 P3589 LD 5 -1 Int BE Pri !#6 N10930 P3590 PREFETCH 23 Int BE Sec !#6 N10931 P3591 REPLACEMENT 0 Int BE Pri !#6 N10932 P3592 LD 18 -1 Int BE Pri !#6 N10933 P3593 ST 0 0x3000018 Int BE Pri !#6 N10934 P3594 MEMBAR !#6 N10935 P3595 BLD 21 -1 FP BE Sec !#6 N10936 P3595 BLD 22 -1 FP BE Sec !#A N10935 N10936 !#6 N10937 P3595 BLD 23 -1 FP BE Sec !#6 N10938 P3596 MEMBAR !#6 N10939 P3597 BST 0 0x42800148 FP BE Pri !#6 N10940 P3597 BST 1 0x42800149 FP BE Pri !#A N10939 N10940 !#6 N10941 P3597 BST 2 0x4280014a FP BE Pri !#6 N10942 P3597 BST 3 0x4280014b FP BE Pri !#6 N10943 P3597 BST 4 0x4280014c FP BE Pri !#6 N10944 P3598 MEMBAR !#6 N10945 P3599 ST 28 0x4280014d FP BE Nuc !#6 N10946 P3600 MEMBAR !#6 N10947 P3601 BLD 21 -1 FP BE Pri !#6 N10948 P3601 BLD 22 -1 FP BE Pri !#A N10947 N10948 !#6 N10949 P3601 BLD 23 -1 FP BE Pri !#6 N10950 P3602 MEMBAR !#6 N10951 P3603 BST 26 0x4280014e FP BE Sec !#6 N10952 P3603 BST 27 0x4280014f FP BE Sec !#6 N10953 P3604 MEMBAR !#6 N10954 P3605 PREFETCH 24 Int BE Pri !#6 N10955 P3606 LD 6 -1 Int BE Pri !#6 N10956 P3607 ST 27 0x3000019 Int BE Pri !#6 N10957 P3608 MEMBAR !#6 N10958 P3609 BSTC 21 0x42800150 FP BE Pri !#6 N10959 P3609 BSTC 22 0x42800151 FP BE Pri !#A N10958 N10959 !#6 N10960 P3609 BSTC 23 0x42800152 FP BE Pri !#6 N10961 P3610 MEMBAR !#6 N10962 P3611 ST 19 0x42800153 FP BE Pri !#6 N10963 P3612 MEMBAR !#6 N10964 P3613 BLD 8 -1 FP BE Pri !#6 N10965 P3613 BLD 9 -1 FP BE Pri !#6 N10966 P3614 MEMBAR !#6 N10967 P3615 ST 27 0x42800154 FP BE Sec !#6 N10968 P3616 REPLACEMENT 5 Int BE Pri !#6 N10969 P3617 REPLACEMENT 1 Int BE Sec !#6 N10970 P3618 ST 28 0x300001a Int BE Pri !#6 N10971 P3619 ST 4 0x42800155 FP BE Pri !#6 N10972 P3620 ST 26 0x300001b Int BE Pri !#6 N10973 P3621 MEMBAR !#6 N10974 P3622 BSTC 0 0x42800156 FP BE Sec !#6 N10975 P3622 BSTC 1 0x42800157 FP BE Sec !#A N10974 N10975 !#6 N10976 P3622 BSTC 2 0x42800158 FP BE Sec !#6 N10977 P3622 BSTC 3 0x42800159 FP BE Sec !#6 N10978 P3622 BSTC 4 0x4280015a FP BE Sec !#6 N10979 P3623 MEMBAR !#6 N10980 P3624 REPLACEMENT 1 Int BE Sec !#6 N10981 P3625 REPLACEMENT 17 Int BE Pri !#6 N10982 P3626 MEMBAR !#6 N10983 P3627 BLD 16 -1 FP BE Sec !#6 N10984 P3628 MEMBAR !#6 N10985 P3629 BLD 7 -1 FP BE Pri !#6 N10986 P3630 MEMBAR !#6 N10987 P3631 BST 0 0x4280015b FP BE Pri !#6 N10988 P3631 BST 1 0x4280015c FP BE Pri !#A N10987 N10988 !#6 N10989 P3631 BST 2 0x4280015d FP BE Pri !#6 N10990 P3631 BST 3 0x4280015e FP BE Pri !#6 N10991 P3631 BST 4 0x4280015f FP BE Pri !#6 N10992 P3632 MEMBAR !#6 N10993 P3633 REPLACEMENT 8 Int BE Pri !#6 N10994 P3634 REPLACEMENT 15 Int BE Sec !#6 N10995 P3635 REPLACEMENT 12 Int BE Sec !#6 N10996 P3636 MEMBAR !#6 N10997 P3637 BLD 8 -1 FP BE Pri !#6 N10998 P3637 BLD 9 -1 FP BE Pri !#6 N10999 P3638 MEMBAR !#6 N11000 P3639 MEMBAR !#7 N11001 P3640 REPLACEMENT 27 Int BE Pri Loop_entry !#7 N11002 P3641 LD 16 -1 FP BE Pri !#7 N11003 P3642 ST 9 0x43000001 FP BE Pri !#7 N11004 P3643 ST 25 0x43000002 FP BE Sec !#7 N11005 P3644 PREFETCH 22 Int BE Pri !#7 N11006 P3645 LD 24 -1 Int BE Pri !#7 N11007 P3646 PREFETCH 2 Int LE Sec !#7 N11008 P3647 MEMBAR !#7 N11009 P3648 BLD 30 -1 FP BE Pri !#7 N11010 P3649 MEMBAR !#7 N11011 P3650 PREFETCH 12 Int BE Pri !#7 N11012 P3651 MEMBAR !#7 N11013 P3652 BST 31 0x43000003 FP BE Pri !#7 N11014 P3653 MEMBAR !#7 N11015 P3654 REPLACEMENT 4 Int BE Pri !#7 N11016 P3655 MEMBAR !#7 N11017 P3656 BLD 0 -1 FP BE Pri !#7 N11018 P3656 BLD 1 -1 FP BE Pri !#A N11017 N11018 !#7 N11019 P3656 BLD 2 -1 FP BE Pri !#7 N11020 P3656 BLD 3 -1 FP BE Pri !#7 N11021 P3656 BLD 4 -1 FP BE Pri !#7 N11022 P3657 MEMBAR !#7 N11023 P3658 BST 0 0x43000004 FP BE Pri !#7 N11024 P3658 BST 1 0x43000005 FP BE Pri !#A N11023 N11024 !#7 N11025 P3658 BST 2 0x43000006 FP BE Pri !#7 N11026 P3658 BST 3 0x43000007 FP BE Pri !#7 N11027 P3658 BST 4 0x43000008 FP BE Pri !#7 N11028 P3659 MEMBAR !#7 N11029 P3660 BST 7 0x43000009 FP BE Pri !#7 N11030 P3661 MEMBAR !#7 N11031 P3662 PREFETCH 22 Int BE Pri !#7 N11032 P3663 MEMBAR !#7 N11033 P3664 BLD 15 -1 FP BE Pri !#7 N11034 P3665 MEMBAR !#7 N11035 P3666 BSTC 30 0x4300000a FP BE Pri !#7 N11036 P3667 MEMBAR !#7 N11037 P3668 BLD 31 -1 FP BE Pri !#7 N11038 P3669 MEMBAR !#7 N11039 P3670 ST 4 0x3800001 Int BE Pri !#7 N11040 P3671 LD 9 -1 FP BE Sec !#7 N11041 P3672 ST 10 0x3800002 Int BE Pri !#7 N11042 P3673 REPLACEMENT 31 Int BE Pri !#7 N11043 P3674 REPLACEMENT 28 Int BE Pri !#7 N11044 P3675 MEMBAR !#7 N11045 P3676 BLD 18 -1 FP BE Pri !#7 N11046 P3677 MEMBAR !#7 N11047 P3678 LD 25 -1 FP BE Sec !#7 N11048 P3679 REPLACEMENT 14 Int BE Pri !#7 N11049 P3680 MEMBAR !#7 N11050 P3681 BLD 0 -1 FP BE Pri !#7 N11051 P3681 BLD 1 -1 FP BE Pri !#A N11050 N11051 !#7 N11052 P3681 BLD 2 -1 FP BE Pri !#7 N11053 P3681 BLD 3 -1 FP BE Pri !#7 N11054 P3681 BLD 4 -1 FP BE Pri !#7 N11055 P3682 MEMBAR !#7 N11056 P3683 REPLACEMENT 4 Int BE Sec !#7 N11057 P3684 LD 16 -1 Int BE Pri !#7 N11058 P3685 MEMBAR !#7 N11059 P3686 BLD 0 -1 FP BE Pri !#7 N11060 P3686 BLD 1 -1 FP BE Pri !#A N11059 N11060 !#7 N11061 P3686 BLD 2 -1 FP BE Pri !#7 N11062 P3686 BLD 3 -1 FP BE Pri !#7 N11063 P3686 BLD 4 -1 FP BE Pri !#7 N11064 P3687 MEMBAR !#7 N11065 P3688 BLD 20 -1 FP BE Pri !#7 N11066 P3689 MEMBAR !#7 N11067 P3690 BSTC 26 0x4300000b FP BE Sec !#7 N11068 P3690 BSTC 27 0x4300000c FP BE Sec !#7 N11069 P3691 MEMBAR !#7 N11070 P3692 BST 24 0x4300000d FP BE Pri !#7 N11071 P3692 BST 25 0x4300000e FP BE Pri !#7 N11072 P3693 MEMBAR !#7 N11073 P3694 BLD 28 -1 FP BE Pri !#7 N11074 P3695 MEMBAR !#7 N11075 P3696 BLD 0 -1 FP BE Pri !#7 N11076 P3696 BLD 1 -1 FP BE Pri !#A N11075 N11076 !#7 N11077 P3696 BLD 2 -1 FP BE Pri !#7 N11078 P3696 BLD 3 -1 FP BE Pri !#7 N11079 P3696 BLD 4 -1 FP BE Pri !#7 N11080 P3697 MEMBAR !#7 N11081 P3698 PREFETCH 9 Int BE Pri !#7 N11082 P3699 MEMBAR !#7 N11083 P3700 BLD 14 -1 FP BE Pri !#7 N11084 P3701 MEMBAR !#7 N11085 P3702 BST 30 0x4300000f FP BE Pri !#7 N11086 P3703 MEMBAR !#7 N11087 P3704 BLD 18 -1 FP BE Pri !#7 N11088 P3705 MEMBAR !#7 N11089 P3706 ST 24 0x3800003 Int BE Pri !#7 N11090 P3707 PREFETCH 28 Int BE Pri !#7 N11091 P3708 MEMBAR !#7 N11092 P3709 BLD 16 -1 FP BE Pri !#7 N11093 P3710 MEMBAR !#7 N11094 P3711 BST 30 0x43000010 FP BE Pri !#7 N11095 P3712 MEMBAR !#7 N11096 P3713 BLD 0 -1 FP BE Pri !#7 N11097 P3713 BLD 1 -1 FP BE Pri !#A N11096 N11097 !#7 N11098 P3713 BLD 2 -1 FP BE Pri !#7 N11099 P3713 BLD 3 -1 FP BE Pri !#7 N11100 P3713 BLD 4 -1 FP BE Pri !#7 N11101 P3714 MEMBAR !#7 N11102 P3715 REPLACEMENT 33 Int BE Pri !#7 N11103 P3716 MEMBAR !#7 N11104 P3717 BLD 31 -1 FP BE Pri !#7 N11105 P3718 MEMBAR !#7 N11106 P3719 PREFETCH 6 Int BE Pri !#7 N11107 P3720 MEMBAR !#7 N11108 P3721 BLD 0 -1 FP BE Pri !#7 N11109 P3721 BLD 1 -1 FP BE Pri !#A N11108 N11109 !#7 N11110 P3721 BLD 2 -1 FP BE Pri !#7 N11111 P3721 BLD 3 -1 FP BE Pri !#7 N11112 P3721 BLD 4 -1 FP BE Pri !#7 N11113 P3722 MEMBAR !#7 N11114 P3723 BLD 8 -1 FP BE Pri !#7 N11115 P3723 BLD 9 -1 FP BE Pri !#7 N11116 P3724 MEMBAR !#7 N11117 P3725 BLD 32 -1 FP BE Pri !#7 N11118 P3726 MEMBAR !#7 N11119 P3727 BSTC 7 0x43000011 FP BE Pri !#7 N11120 P3728 MEMBAR !#7 N11121 P3729 BLD 28 -1 FP BE Pri !#7 N11122 P3730 MEMBAR !#7 N11123 P3731 BSTC 0 0x43000012 FP BE Pri !#7 N11124 P3731 BSTC 1 0x43000013 FP BE Pri !#A N11123 N11124 !#7 N11125 P3731 BSTC 2 0x43000014 FP BE Pri !#7 N11126 P3731 BSTC 3 0x43000015 FP BE Pri !#7 N11127 P3731 BSTC 4 0x43000016 FP BE Pri !#7 N11128 P3732 MEMBAR !#7 N11129 P3733 BLD 5 -1 FP BE Pri !#7 N11130 P3733 BLD 6 -1 FP BE Pri !#7 N11131 P3734 MEMBAR !#7 N11132 P3735 REPLACEMENT 29 Int BE Pri !#7 N11133 P3736 REPLACEMENT 30 Int BE Pri !#7 N11134 P3737 MEMBAR !#7 N11135 P3738 BLD 19 -1 FP BE Pri !#7 N11136 P3739 MEMBAR !#7 N11137 P3740 LD 26 -1 FP BE Sec !#7 N11138 P3741 ST 19 0x43000017 FP BE Pri !#7 N11139 P3742 MEMBAR !#7 N11140 P3743 BLD 24 -1 FP BE Sec !#7 N11141 P3743 BLD 25 -1 FP BE Sec !#7 N11142 P3744 MEMBAR !#7 N11143 P3745 ST 5 0x43000018 FP BE Pri !#7 N11144 P3746 MEMBAR !#7 N11145 P3747 BLD 0 -1 FP BE Pri !#7 N11146 P3747 BLD 1 -1 FP BE Pri !#A N11145 N11146 !#7 N11147 P3747 BLD 2 -1 FP BE Pri !#7 N11148 P3747 BLD 3 -1 FP BE Pri !#7 N11149 P3747 BLD 4 -1 FP BE Pri !#7 N11150 P3748 MEMBAR !#7 N11151 P3749 ST 21 0x3800004 Int BE Pri !#7 N11152 P3750 MEMBAR !#7 N11153 P3751 BLD 0 -1 FP BE Pri !#7 N11154 P3751 BLD 1 -1 FP BE Pri !#A N11153 N11154 !#7 N11155 P3751 BLD 2 -1 FP BE Pri !#7 N11156 P3751 BLD 3 -1 FP BE Pri !#7 N11157 P3751 BLD 4 -1 FP BE Pri !#7 N11158 P3752 MEMBAR !#7 N11159 P3753 BSTC 18 0x43000019 FP BE Pri !#7 N11160 P3754 MEMBAR !#7 N11161 P3755 BLD 15 -1 FP BE Pri !#7 N11162 P3756 MEMBAR !#7 N11163 P3757 BST 17 0x4300001a FP BE Pri !#7 N11164 P3758 MEMBAR !#7 N11165 P3759 PREFETCH 14 Int BE Pri !#7 N11166 P3760 MEMBAR !#7 N11167 P3761 BST 0 0x4300001b FP BE Pri !#7 N11168 P3761 BST 1 0x4300001c FP BE Pri !#A N11167 N11168 !#7 N11169 P3761 BST 2 0x4300001d FP BE Pri !#7 N11170 P3761 BST 3 0x4300001e FP BE Pri !#7 N11171 P3761 BST 4 0x4300001f FP BE Pri !#7 N11172 P3762 MEMBAR !#7 N11173 P3763 REPLACEMENT 22 Int BE Pri !#7 N11174 P3764 MEMBAR !#7 N11175 P3765 BLD 0 -1 FP BE Pri !#7 N11176 P3765 BLD 1 -1 FP BE Pri !#A N11175 N11176 !#7 N11177 P3765 BLD 2 -1 FP BE Pri !#7 N11178 P3765 BLD 3 -1 FP BE Pri !#7 N11179 P3765 BLD 4 -1 FP BE Pri !#7 N11180 P3766 MEMBAR !#7 N11181 P3767 ST 11 0x3800005 Int BE Sec !#7 N11182 P3768 MEMBAR !#7 N11183 P3769 BSTC 20 0x43000020 FP BE Pri !#7 N11184 P3770 MEMBAR !#7 N11185 P3771 BLD 17 -1 FP BE Sec !#7 N11186 P3772 MEMBAR !#7 N11187 P3773 REPLACEMENT 22 Int BE Pri !#7 N11188 P3774 REPLACEMENT 27 Int BE Pri !#7 N11189 P3775 ST 28 0x43000021 FP BE Pri !#7 N11190 P3776 MEMBAR !#7 N11191 P3777 BLD 5 -1 FP BE Pri !#7 N11192 P3777 BLD 6 -1 FP BE Pri !#7 N11193 P3778 MEMBAR !#7 N11194 P3779 BST 29 0x43000022 FP BE Pri !#7 N11195 P3780 MEMBAR !#7 N11196 P3781 BST 8 0x43000023 FP BE Pri !#7 N11197 P3781 BST 9 0x43000024 FP BE Pri !#7 N11198 P3782 MEMBAR !#7 N11199 P3783 LD 32 -1 FP BE Pri !#7 N11200 P3784 LD 16 -1 FP BE Pri !#7 N11201 P3785 MEMBAR !#7 N11202 P3786 BSTC 24 0x43000025 FP BE Sec !#7 N11203 P3786 BSTC 25 0x43000026 FP BE Sec !#7 N11204 P3787 MEMBAR !#7 N11205 P3788 BST 16 0x43000027 FP BE Pri !#7 N11206 P3789 MEMBAR !#7 N11207 P3790 ST 12 0x3800006 Int BE Nuc !#7 N11208 P3791 ST 19 0x43000028 FP BE Pri !#7 N11209 P3792 REPLACEMENT 27 Int BE Sec !#7 N11210 P3793 LD 28 -1 FP BE Sec !#7 N11211 P3794 MEMBAR !#7 N11212 P3795 BSTC 7 0x43000029 FP BE Pri !#7 N11213 P3796 MEMBAR !#7 N11214 P3797 BLD 16 -1 FP BE Pri !#7 N11215 P3798 MEMBAR !#7 N11216 P3799 ST 24 0x3800007 Int BE Sec !#7 N11217 P3800 REPLACEMENT 13 Int BE Sec !#7 N11218 P3801 ST 5 0x4300002a FP BE Pri !#7 N11219 P3802 MEMBAR !#7 N11220 P3803 BLD 7 -1 FP BE Pri !#7 N11221 P3804 MEMBAR !#7 N11222 P3805 BLD 21 -1 FP BE Pri !#7 N11223 P3805 BLD 22 -1 FP BE Pri !#A N11222 N11223 !#7 N11224 P3805 BLD 23 -1 FP BE Pri !#7 N11225 P3806 MEMBAR !#7 N11226 P3807 LD 17 -1 Int BE Nuc !#7 N11227 P3808 REPLACEMENT 19 Int BE Pri !#7 N11228 P3809 LD 22 -1 Int BE Pri !#7 N11229 P3810 IDC_FLIP 15 Int BE Pri !#7 N11230 P3811 ST 24 0x3800008 Int BE Sec !#7 N11231 P3812 MEMBAR !#7 N11232 P3813 BSTC 28 0x4300002b FP BE Sec !#7 N11233 P3814 MEMBAR !#7 N11234 P3815 REPLACEMENT 16 Int BE Pri !#7 N11235 P3816 IDC_FLIP 2 Int BE Pri !#7 N11236 P3817 MEMBAR !#7 N11237 P3818 BST 0 0x4300002c FP BE Pri !#7 N11238 P3818 BST 1 0x4300002d FP BE Pri !#A N11237 N11238 !#7 N11239 P3818 BST 2 0x4300002e FP BE Pri !#7 N11240 P3818 BST 3 0x4300002f FP BE Pri !#7 N11241 P3818 BST 4 0x43000030 FP BE Pri !#7 N11242 P3819 MEMBAR !#7 N11243 P3820 PREFETCH 20 Int BE Pri !#7 N11244 P3821 MEMBAR !#7 N11245 P3822 BLD 5 -1 FP BE Pri !#7 N11246 P3822 BLD 6 -1 FP BE Pri !#7 N11247 P3823 MEMBAR !#7 N11248 P3824 LD 9 -1 Int BE Pri !#7 N11249 P3825 MEMBAR !#7 N11250 P3826 BSTC 29 0x43000031 FP BE Pri !#7 N11251 P3827 MEMBAR !#7 N11252 P3828 BLD 0 -1 FP BE Pri !#7 N11253 P3828 BLD 1 -1 FP BE Pri !#A N11252 N11253 !#7 N11254 P3828 BLD 2 -1 FP BE Pri !#7 N11255 P3828 BLD 3 -1 FP BE Pri !#7 N11256 P3828 BLD 4 -1 FP BE Pri !#7 N11257 P3829 MEMBAR !#7 N11258 P3830 BST 0 0x43000032 FP BE Pri !#7 N11259 P3830 BST 1 0x43000033 FP BE Pri !#A N11258 N11259 !#7 N11260 P3830 BST 2 0x43000034 FP BE Pri !#7 N11261 P3830 BST 3 0x43000035 FP BE Pri !#7 N11262 P3830 BST 4 0x43000036 FP BE Pri !#7 N11263 P3831 MEMBAR !#7 N11264 P3832 PREFETCH 11 Int BE Pri !#7 N11265 P3833 MEMBAR !#7 N11266 P3834 BLD 21 -1 FP BE Pri !#7 N11267 P3834 BLD 22 -1 FP BE Pri !#A N11266 N11267 !#7 N11268 P3834 BLD 23 -1 FP BE Pri !#7 N11269 P3835 MEMBAR !#7 N11270 P3836 BSTC 0 0x43000037 FP BE Pri !#7 N11271 P3836 BSTC 1 0x43000038 FP BE Pri !#A N11270 N11271 !#7 N11272 P3836 BSTC 2 0x43000039 FP BE Pri !#7 N11273 P3836 BSTC 3 0x4300003a FP BE Pri !#7 N11274 P3836 BSTC 4 0x4300003b FP BE Pri !#7 N11275 P3837 MEMBAR !#7 N11276 P3838 BLD 0 -1 FP BE Pri !#7 N11277 P3838 BLD 1 -1 FP BE Pri !#A N11276 N11277 !#7 N11278 P3838 BLD 2 -1 FP BE Pri !#7 N11279 P3838 BLD 3 -1 FP BE Pri !#7 N11280 P3838 BLD 4 -1 FP BE Pri !#7 N11281 P3839 MEMBAR !#7 N11282 P3840 LD 17 -1 FP BE Pri !#7 N11283 P3841 REPLACEMENT 21 Int BE Pri !#7 N11284 P3842 IDC_FLIP 17 Int BE Pri !#7 N11285 P3843 MEMBAR !#7 N11286 P3844 BST 21 0x4300003c FP BE Pri !#7 N11287 P3844 BST 22 0x4300003d FP BE Pri !#A N11286 N11287 !#7 N11288 P3844 BST 23 0x4300003e FP BE Pri !#7 N11289 P3845 MEMBAR !#7 N11290 P3846 LD 3 -1 Int BE Pri Loop_exit !#7 N11291 P3640 REPLACEMENT 27 Int BE Pri Loop_entry !#7 N11292 P3641 LD 16 -1 FP BE Pri !#7 N11293 P3642 ST 9 0x4300003f FP BE Pri !#7 N11294 P3643 ST 25 0x43000040 FP BE Sec !#7 N11295 P3644 PREFETCH 22 Int BE Pri !#7 N11296 P3645 LD 24 -1 Int BE Pri !#7 N11297 P3646 PREFETCH 2 Int LE Sec !#7 N11298 P3647 MEMBAR !#7 N11299 P3648 BLD 30 -1 FP BE Pri !#7 N11300 P3649 MEMBAR !#7 N11301 P3650 PREFETCH 12 Int BE Pri !#7 N11302 P3651 MEMBAR !#7 N11303 P3652 BST 31 0x43000041 FP BE Pri !#7 N11304 P3653 MEMBAR !#7 N11305 P3654 REPLACEMENT 4 Int BE Pri !#7 N11306 P3655 MEMBAR !#7 N11307 P3656 BLD 0 -1 FP BE Pri !#7 N11308 P3656 BLD 1 -1 FP BE Pri !#A N11307 N11308 !#7 N11309 P3656 BLD 2 -1 FP BE Pri !#7 N11310 P3656 BLD 3 -1 FP BE Pri !#7 N11311 P3656 BLD 4 -1 FP BE Pri !#7 N11312 P3657 MEMBAR !#7 N11313 P3658 BST 0 0x43000042 FP BE Pri !#7 N11314 P3658 BST 1 0x43000043 FP BE Pri !#A N11313 N11314 !#7 N11315 P3658 BST 2 0x43000044 FP BE Pri !#7 N11316 P3658 BST 3 0x43000045 FP BE Pri !#7 N11317 P3658 BST 4 0x43000046 FP BE Pri !#7 N11318 P3659 MEMBAR !#7 N11319 P3660 BST 7 0x43000047 FP BE Pri !#7 N11320 P3661 MEMBAR !#7 N11321 P3662 PREFETCH 22 Int BE Pri !#7 N11322 P3663 MEMBAR !#7 N11323 P3664 BLD 15 -1 FP BE Pri !#7 N11324 P3665 MEMBAR !#7 N11325 P3666 BSTC 30 0x43000048 FP BE Pri !#7 N11326 P3667 MEMBAR !#7 N11327 P3668 BLD 31 -1 FP BE Pri !#7 N11328 P3669 MEMBAR !#7 N11329 P3670 ST 4 0x3800009 Int BE Pri !#7 N11330 P3671 LD 9 -1 FP BE Sec !#7 N11331 P3672 ST 10 0x380000a Int BE Pri !#7 N11332 P3673 REPLACEMENT 31 Int BE Pri !#7 N11333 P3674 REPLACEMENT 28 Int BE Pri !#7 N11334 P3675 MEMBAR !#7 N11335 P3676 BLD 18 -1 FP BE Pri !#7 N11336 P3677 MEMBAR !#7 N11337 P3678 LD 25 -1 FP BE Sec !#7 N11338 P3679 REPLACEMENT 14 Int BE Pri !#7 N11339 P3680 MEMBAR !#7 N11340 P3681 BLD 0 -1 FP BE Pri !#7 N11341 P3681 BLD 1 -1 FP BE Pri !#A N11340 N11341 !#7 N11342 P3681 BLD 2 -1 FP BE Pri !#7 N11343 P3681 BLD 3 -1 FP BE Pri !#7 N11344 P3681 BLD 4 -1 FP BE Pri !#7 N11345 P3682 MEMBAR !#7 N11346 P3683 REPLACEMENT 4 Int BE Sec !#7 N11347 P3684 LD 16 -1 Int BE Pri !#7 N11348 P3685 MEMBAR !#7 N11349 P3686 BLD 0 -1 FP BE Pri !#7 N11350 P3686 BLD 1 -1 FP BE Pri !#A N11349 N11350 !#7 N11351 P3686 BLD 2 -1 FP BE Pri !#7 N11352 P3686 BLD 3 -1 FP BE Pri !#7 N11353 P3686 BLD 4 -1 FP BE Pri !#7 N11354 P3687 MEMBAR !#7 N11355 P3688 BLD 20 -1 FP BE Pri !#7 N11356 P3689 MEMBAR !#7 N11357 P3690 BSTC 26 0x43000049 FP BE Sec !#7 N11358 P3690 BSTC 27 0x4300004a FP BE Sec !#7 N11359 P3691 MEMBAR !#7 N11360 P3692 BST 24 0x4300004b FP BE Pri !#7 N11361 P3692 BST 25 0x4300004c FP BE Pri !#7 N11362 P3693 MEMBAR !#7 N11363 P3694 BLD 28 -1 FP BE Pri !#7 N11364 P3695 MEMBAR !#7 N11365 P3696 BLD 0 -1 FP BE Pri !#7 N11366 P3696 BLD 1 -1 FP BE Pri !#A N11365 N11366 !#7 N11367 P3696 BLD 2 -1 FP BE Pri !#7 N11368 P3696 BLD 3 -1 FP BE Pri !#7 N11369 P3696 BLD 4 -1 FP BE Pri !#7 N11370 P3697 MEMBAR !#7 N11371 P3698 PREFETCH 9 Int BE Pri !#7 N11372 P3699 MEMBAR !#7 N11373 P3700 BLD 14 -1 FP BE Pri !#7 N11374 P3701 MEMBAR !#7 N11375 P3702 BST 30 0x4300004d FP BE Pri !#7 N11376 P3703 MEMBAR !#7 N11377 P3704 BLD 18 -1 FP BE Pri !#7 N11378 P3705 MEMBAR !#7 N11379 P3706 ST 24 0x380000b Int BE Pri !#7 N11380 P3707 PREFETCH 28 Int BE Pri !#7 N11381 P3708 MEMBAR !#7 N11382 P3709 BLD 16 -1 FP BE Pri !#7 N11383 P3710 MEMBAR !#7 N11384 P3711 BST 30 0x4300004e FP BE Pri !#7 N11385 P3712 MEMBAR !#7 N11386 P3713 BLD 0 -1 FP BE Pri !#7 N11387 P3713 BLD 1 -1 FP BE Pri !#A N11386 N11387 !#7 N11388 P3713 BLD 2 -1 FP BE Pri !#7 N11389 P3713 BLD 3 -1 FP BE Pri !#7 N11390 P3713 BLD 4 -1 FP BE Pri !#7 N11391 P3714 MEMBAR !#7 N11392 P3715 REPLACEMENT 33 Int BE Pri !#7 N11393 P3716 MEMBAR !#7 N11394 P3717 BLD 31 -1 FP BE Pri !#7 N11395 P3718 MEMBAR !#7 N11396 P3719 PREFETCH 6 Int BE Pri !#7 N11397 P3720 MEMBAR !#7 N11398 P3721 BLD 0 -1 FP BE Pri !#7 N11399 P3721 BLD 1 -1 FP BE Pri !#A N11398 N11399 !#7 N11400 P3721 BLD 2 -1 FP BE Pri !#7 N11401 P3721 BLD 3 -1 FP BE Pri !#7 N11402 P3721 BLD 4 -1 FP BE Pri !#7 N11403 P3722 MEMBAR !#7 N11404 P3723 BLD 8 -1 FP BE Pri !#7 N11405 P3723 BLD 9 -1 FP BE Pri !#7 N11406 P3724 MEMBAR !#7 N11407 P3725 BLD 32 -1 FP BE Pri !#7 N11408 P3726 MEMBAR !#7 N11409 P3727 BSTC 7 0x4300004f FP BE Pri !#7 N11410 P3728 MEMBAR !#7 N11411 P3729 BLD 28 -1 FP BE Pri !#7 N11412 P3730 MEMBAR !#7 N11413 P3731 BSTC 0 0x43000050 FP BE Pri !#7 N11414 P3731 BSTC 1 0x43000051 FP BE Pri !#A N11413 N11414 !#7 N11415 P3731 BSTC 2 0x43000052 FP BE Pri !#7 N11416 P3731 BSTC 3 0x43000053 FP BE Pri !#7 N11417 P3731 BSTC 4 0x43000054 FP BE Pri !#7 N11418 P3732 MEMBAR !#7 N11419 P3733 BLD 5 -1 FP BE Pri !#7 N11420 P3733 BLD 6 -1 FP BE Pri !#7 N11421 P3734 MEMBAR !#7 N11422 P3735 REPLACEMENT 29 Int BE Pri !#7 N11423 P3736 REPLACEMENT 30 Int BE Pri !#7 N11424 P3737 MEMBAR !#7 N11425 P3738 BLD 19 -1 FP BE Pri !#7 N11426 P3739 MEMBAR !#7 N11427 P3740 LD 26 -1 FP BE Sec !#7 N11428 P3741 ST 19 0x43000055 FP BE Pri !#7 N11429 P3742 MEMBAR !#7 N11430 P3743 BLD 24 -1 FP BE Sec !#7 N11431 P3743 BLD 25 -1 FP BE Sec !#7 N11432 P3744 MEMBAR !#7 N11433 P3745 ST 5 0x43000056 FP BE Pri !#7 N11434 P3746 MEMBAR !#7 N11435 P3747 BLD 0 -1 FP BE Pri !#7 N11436 P3747 BLD 1 -1 FP BE Pri !#A N11435 N11436 !#7 N11437 P3747 BLD 2 -1 FP BE Pri !#7 N11438 P3747 BLD 3 -1 FP BE Pri !#7 N11439 P3747 BLD 4 -1 FP BE Pri !#7 N11440 P3748 MEMBAR !#7 N11441 P3749 ST 21 0x380000c Int BE Pri !#7 N11442 P3750 MEMBAR !#7 N11443 P3751 BLD 0 -1 FP BE Pri !#7 N11444 P3751 BLD 1 -1 FP BE Pri !#A N11443 N11444 !#7 N11445 P3751 BLD 2 -1 FP BE Pri !#7 N11446 P3751 BLD 3 -1 FP BE Pri !#7 N11447 P3751 BLD 4 -1 FP BE Pri !#7 N11448 P3752 MEMBAR !#7 N11449 P3753 BSTC 18 0x43000057 FP BE Pri !#7 N11450 P3754 MEMBAR !#7 N11451 P3755 BLD 15 -1 FP BE Pri !#7 N11452 P3756 MEMBAR !#7 N11453 P3757 BST 17 0x43000058 FP BE Pri !#7 N11454 P3758 MEMBAR !#7 N11455 P3759 PREFETCH 14 Int BE Pri !#7 N11456 P3760 MEMBAR !#7 N11457 P3761 BST 0 0x43000059 FP BE Pri !#7 N11458 P3761 BST 1 0x4300005a FP BE Pri !#A N11457 N11458 !#7 N11459 P3761 BST 2 0x4300005b FP BE Pri !#7 N11460 P3761 BST 3 0x4300005c FP BE Pri !#7 N11461 P3761 BST 4 0x4300005d FP BE Pri !#7 N11462 P3762 MEMBAR !#7 N11463 P3763 REPLACEMENT 22 Int BE Pri !#7 N11464 P3764 MEMBAR !#7 N11465 P3765 BLD 0 -1 FP BE Pri !#7 N11466 P3765 BLD 1 -1 FP BE Pri !#A N11465 N11466 !#7 N11467 P3765 BLD 2 -1 FP BE Pri !#7 N11468 P3765 BLD 3 -1 FP BE Pri !#7 N11469 P3765 BLD 4 -1 FP BE Pri !#7 N11470 P3766 MEMBAR !#7 N11471 P3767 ST 11 0x380000d Int BE Sec !#7 N11472 P3768 MEMBAR !#7 N11473 P3769 BSTC 20 0x4300005e FP BE Pri !#7 N11474 P3770 MEMBAR !#7 N11475 P3771 BLD 17 -1 FP BE Sec !#7 N11476 P3772 MEMBAR !#7 N11477 P3773 REPLACEMENT 22 Int BE Pri !#7 N11478 P3774 REPLACEMENT 27 Int BE Pri !#7 N11479 P3775 ST 28 0x4300005f FP BE Pri !#7 N11480 P3776 MEMBAR !#7 N11481 P3777 BLD 5 -1 FP BE Pri !#7 N11482 P3777 BLD 6 -1 FP BE Pri !#7 N11483 P3778 MEMBAR !#7 N11484 P3779 BST 29 0x43000060 FP BE Pri !#7 N11485 P3780 MEMBAR !#7 N11486 P3781 BST 8 0x43000061 FP BE Pri !#7 N11487 P3781 BST 9 0x43000062 FP BE Pri !#7 N11488 P3782 MEMBAR !#7 N11489 P3783 LD 32 -1 FP BE Pri !#7 N11490 P3784 LD 16 -1 FP BE Pri !#7 N11491 P3785 MEMBAR !#7 N11492 P3786 BSTC 24 0x43000063 FP BE Sec !#7 N11493 P3786 BSTC 25 0x43000064 FP BE Sec !#7 N11494 P3787 MEMBAR !#7 N11495 P3788 BST 16 0x43000065 FP BE Pri !#7 N11496 P3789 MEMBAR !#7 N11497 P3790 ST 12 0x380000e Int BE Nuc !#7 N11498 P3791 ST 19 0x43000066 FP BE Pri !#7 N11499 P3792 REPLACEMENT 27 Int BE Sec !#7 N11500 P3793 LD 28 -1 FP BE Sec !#7 N11501 P3794 MEMBAR !#7 N11502 P3795 BSTC 7 0x43000067 FP BE Pri !#7 N11503 P3796 MEMBAR !#7 N11504 P3797 BLD 16 -1 FP BE Pri !#7 N11505 P3798 MEMBAR !#7 N11506 P3799 ST 24 0x380000f Int BE Sec !#7 N11507 P3800 REPLACEMENT 13 Int BE Sec !#7 N11508 P3801 ST 5 0x43000068 FP BE Pri !#7 N11509 P3802 MEMBAR !#7 N11510 P3803 BLD 7 -1 FP BE Pri !#7 N11511 P3804 MEMBAR !#7 N11512 P3805 BLD 21 -1 FP BE Pri !#7 N11513 P3805 BLD 22 -1 FP BE Pri !#A N11512 N11513 !#7 N11514 P3805 BLD 23 -1 FP BE Pri !#7 N11515 P3806 MEMBAR !#7 N11516 P3807 LD 17 -1 Int BE Nuc !#7 N11517 P3808 REPLACEMENT 19 Int BE Pri !#7 N11518 P3809 LD 22 -1 Int BE Pri !#7 N11519 P3810 IDC_FLIP 15 Int BE Pri !#7 N11520 P3811 ST 24 0x3800010 Int BE Sec !#7 N11521 P3812 MEMBAR !#7 N11522 P3813 BSTC 28 0x43000069 FP BE Sec !#7 N11523 P3814 MEMBAR !#7 N11524 P3815 REPLACEMENT 16 Int BE Pri !#7 N11525 P3816 IDC_FLIP 2 Int BE Pri !#7 N11526 P3817 MEMBAR !#7 N11527 P3818 BST 0 0x4300006a FP BE Pri !#7 N11528 P3818 BST 1 0x4300006b FP BE Pri !#A N11527 N11528 !#7 N11529 P3818 BST 2 0x4300006c FP BE Pri !#7 N11530 P3818 BST 3 0x4300006d FP BE Pri !#7 N11531 P3818 BST 4 0x4300006e FP BE Pri !#7 N11532 P3819 MEMBAR !#7 N11533 P3820 PREFETCH 20 Int BE Pri !#7 N11534 P3821 MEMBAR !#7 N11535 P3822 BLD 5 -1 FP BE Pri !#7 N11536 P3822 BLD 6 -1 FP BE Pri !#7 N11537 P3823 MEMBAR !#7 N11538 P3824 LD 9 -1 Int BE Pri !#7 N11539 P3825 MEMBAR !#7 N11540 P3826 BSTC 29 0x4300006f FP BE Pri !#7 N11541 P3827 MEMBAR !#7 N11542 P3828 BLD 0 -1 FP BE Pri !#7 N11543 P3828 BLD 1 -1 FP BE Pri !#A N11542 N11543 !#7 N11544 P3828 BLD 2 -1 FP BE Pri !#7 N11545 P3828 BLD 3 -1 FP BE Pri !#7 N11546 P3828 BLD 4 -1 FP BE Pri !#7 N11547 P3829 MEMBAR !#7 N11548 P3830 BST 0 0x43000070 FP BE Pri !#7 N11549 P3830 BST 1 0x43000071 FP BE Pri !#A N11548 N11549 !#7 N11550 P3830 BST 2 0x43000072 FP BE Pri !#7 N11551 P3830 BST 3 0x43000073 FP BE Pri !#7 N11552 P3830 BST 4 0x43000074 FP BE Pri !#7 N11553 P3831 MEMBAR !#7 N11554 P3832 PREFETCH 11 Int BE Pri !#7 N11555 P3833 MEMBAR !#7 N11556 P3834 BLD 21 -1 FP BE Pri !#7 N11557 P3834 BLD 22 -1 FP BE Pri !#A N11556 N11557 !#7 N11558 P3834 BLD 23 -1 FP BE Pri !#7 N11559 P3835 MEMBAR !#7 N11560 P3836 BSTC 0 0x43000075 FP BE Pri !#7 N11561 P3836 BSTC 1 0x43000076 FP BE Pri !#A N11560 N11561 !#7 N11562 P3836 BSTC 2 0x43000077 FP BE Pri !#7 N11563 P3836 BSTC 3 0x43000078 FP BE Pri !#7 N11564 P3836 BSTC 4 0x43000079 FP BE Pri !#7 N11565 P3837 MEMBAR !#7 N11566 P3838 BLD 0 -1 FP BE Pri !#7 N11567 P3838 BLD 1 -1 FP BE Pri !#A N11566 N11567 !#7 N11568 P3838 BLD 2 -1 FP BE Pri !#7 N11569 P3838 BLD 3 -1 FP BE Pri !#7 N11570 P3838 BLD 4 -1 FP BE Pri !#7 N11571 P3839 MEMBAR !#7 N11572 P3840 LD 17 -1 FP BE Pri !#7 N11573 P3841 REPLACEMENT 21 Int BE Pri !#7 N11574 P3842 IDC_FLIP 17 Int BE Pri !#7 N11575 P3843 MEMBAR !#7 N11576 P3844 BST 21 0x4300007a FP BE Pri !#7 N11577 P3844 BST 22 0x4300007b FP BE Pri !#A N11576 N11577 !#7 N11578 P3844 BST 23 0x4300007c FP BE Pri !#7 N11579 P3845 MEMBAR !#7 N11580 P3846 LD 3 -1 Int BE Pri Loop_exit !#7 N11581 P3640 REPLACEMENT 27 Int BE Pri Loop_entry !#7 N11582 P3641 LD 16 -1 FP BE Pri !#7 N11583 P3642 ST 9 0x4300007d FP BE Pri !#7 N11584 P3643 ST 25 0x4300007e FP BE Sec !#7 N11585 P3644 PREFETCH 22 Int BE Pri !#7 N11586 P3645 LD 24 -1 Int BE Pri !#7 N11587 P3646 PREFETCH 2 Int LE Sec !#7 N11588 P3647 MEMBAR !#7 N11589 P3648 BLD 30 -1 FP BE Pri !#7 N11590 P3649 MEMBAR !#7 N11591 P3650 PREFETCH 12 Int BE Pri !#7 N11592 P3651 MEMBAR !#7 N11593 P3652 BST 31 0x4300007f FP BE Pri !#7 N11594 P3653 MEMBAR !#7 N11595 P3654 REPLACEMENT 4 Int BE Pri !#7 N11596 P3655 MEMBAR !#7 N11597 P3656 BLD 0 -1 FP BE Pri !#7 N11598 P3656 BLD 1 -1 FP BE Pri !#A N11597 N11598 !#7 N11599 P3656 BLD 2 -1 FP BE Pri !#7 N11600 P3656 BLD 3 -1 FP BE Pri !#7 N11601 P3656 BLD 4 -1 FP BE Pri !#7 N11602 P3657 MEMBAR !#7 N11603 P3658 BST 0 0x43000080 FP BE Pri !#7 N11604 P3658 BST 1 0x43000081 FP BE Pri !#A N11603 N11604 !#7 N11605 P3658 BST 2 0x43000082 FP BE Pri !#7 N11606 P3658 BST 3 0x43000083 FP BE Pri !#7 N11607 P3658 BST 4 0x43000084 FP BE Pri !#7 N11608 P3659 MEMBAR !#7 N11609 P3660 BST 7 0x43000085 FP BE Pri !#7 N11610 P3661 MEMBAR !#7 N11611 P3662 PREFETCH 22 Int BE Pri !#7 N11612 P3663 MEMBAR !#7 N11613 P3664 BLD 15 -1 FP BE Pri !#7 N11614 P3665 MEMBAR !#7 N11615 P3666 BSTC 30 0x43000086 FP BE Pri !#7 N11616 P3667 MEMBAR !#7 N11617 P3668 BLD 31 -1 FP BE Pri !#7 N11618 P3669 MEMBAR !#7 N11619 P3670 ST 4 0x3800011 Int BE Pri !#7 N11620 P3671 LD 9 -1 FP BE Sec !#7 N11621 P3672 ST 10 0x3800012 Int BE Pri !#7 N11622 P3673 REPLACEMENT 31 Int BE Pri !#7 N11623 P3674 REPLACEMENT 28 Int BE Pri !#7 N11624 P3675 MEMBAR !#7 N11625 P3676 BLD 18 -1 FP BE Pri !#7 N11626 P3677 MEMBAR !#7 N11627 P3678 LD 25 -1 FP BE Sec !#7 N11628 P3679 REPLACEMENT 14 Int BE Pri !#7 N11629 P3680 MEMBAR !#7 N11630 P3681 BLD 0 -1 FP BE Pri !#7 N11631 P3681 BLD 1 -1 FP BE Pri !#A N11630 N11631 !#7 N11632 P3681 BLD 2 -1 FP BE Pri !#7 N11633 P3681 BLD 3 -1 FP BE Pri !#7 N11634 P3681 BLD 4 -1 FP BE Pri !#7 N11635 P3682 MEMBAR !#7 N11636 P3683 REPLACEMENT 4 Int BE Sec !#7 N11637 P3684 LD 16 -1 Int BE Pri !#7 N11638 P3685 MEMBAR !#7 N11639 P3686 BLD 0 -1 FP BE Pri !#7 N11640 P3686 BLD 1 -1 FP BE Pri !#A N11639 N11640 !#7 N11641 P3686 BLD 2 -1 FP BE Pri !#7 N11642 P3686 BLD 3 -1 FP BE Pri !#7 N11643 P3686 BLD 4 -1 FP BE Pri !#7 N11644 P3687 MEMBAR !#7 N11645 P3688 BLD 20 -1 FP BE Pri !#7 N11646 P3689 MEMBAR !#7 N11647 P3690 BSTC 26 0x43000087 FP BE Sec !#7 N11648 P3690 BSTC 27 0x43000088 FP BE Sec !#7 N11649 P3691 MEMBAR !#7 N11650 P3692 BST 24 0x43000089 FP BE Pri !#7 N11651 P3692 BST 25 0x4300008a FP BE Pri !#7 N11652 P3693 MEMBAR !#7 N11653 P3694 BLD 28 -1 FP BE Pri !#7 N11654 P3695 MEMBAR !#7 N11655 P3696 BLD 0 -1 FP BE Pri !#7 N11656 P3696 BLD 1 -1 FP BE Pri !#A N11655 N11656 !#7 N11657 P3696 BLD 2 -1 FP BE Pri !#7 N11658 P3696 BLD 3 -1 FP BE Pri !#7 N11659 P3696 BLD 4 -1 FP BE Pri !#7 N11660 P3697 MEMBAR !#7 N11661 P3698 PREFETCH 9 Int BE Pri !#7 N11662 P3699 MEMBAR !#7 N11663 P3700 BLD 14 -1 FP BE Pri !#7 N11664 P3701 MEMBAR !#7 N11665 P3702 BST 30 0x4300008b FP BE Pri !#7 N11666 P3703 MEMBAR !#7 N11667 P3704 BLD 18 -1 FP BE Pri !#7 N11668 P3705 MEMBAR !#7 N11669 P3706 ST 24 0x3800013 Int BE Pri !#7 N11670 P3707 PREFETCH 28 Int BE Pri !#7 N11671 P3708 MEMBAR !#7 N11672 P3709 BLD 16 -1 FP BE Pri !#7 N11673 P3710 MEMBAR !#7 N11674 P3711 BST 30 0x4300008c FP BE Pri !#7 N11675 P3712 MEMBAR !#7 N11676 P3713 BLD 0 -1 FP BE Pri !#7 N11677 P3713 BLD 1 -1 FP BE Pri !#A N11676 N11677 !#7 N11678 P3713 BLD 2 -1 FP BE Pri !#7 N11679 P3713 BLD 3 -1 FP BE Pri !#7 N11680 P3713 BLD 4 -1 FP BE Pri !#7 N11681 P3714 MEMBAR !#7 N11682 P3715 REPLACEMENT 33 Int BE Pri !#7 N11683 P3716 MEMBAR !#7 N11684 P3717 BLD 31 -1 FP BE Pri !#7 N11685 P3718 MEMBAR !#7 N11686 P3719 PREFETCH 6 Int BE Pri !#7 N11687 P3720 MEMBAR !#7 N11688 P3721 BLD 0 -1 FP BE Pri !#7 N11689 P3721 BLD 1 -1 FP BE Pri !#A N11688 N11689 !#7 N11690 P3721 BLD 2 -1 FP BE Pri !#7 N11691 P3721 BLD 3 -1 FP BE Pri !#7 N11692 P3721 BLD 4 -1 FP BE Pri !#7 N11693 P3722 MEMBAR !#7 N11694 P3723 BLD 8 -1 FP BE Pri !#7 N11695 P3723 BLD 9 -1 FP BE Pri !#7 N11696 P3724 MEMBAR !#7 N11697 P3725 BLD 32 -1 FP BE Pri !#7 N11698 P3726 MEMBAR !#7 N11699 P3727 BSTC 7 0x4300008d FP BE Pri !#7 N11700 P3728 MEMBAR !#7 N11701 P3729 BLD 28 -1 FP BE Pri !#7 N11702 P3730 MEMBAR !#7 N11703 P3731 BSTC 0 0x4300008e FP BE Pri !#7 N11704 P3731 BSTC 1 0x4300008f FP BE Pri !#A N11703 N11704 !#7 N11705 P3731 BSTC 2 0x43000090 FP BE Pri !#7 N11706 P3731 BSTC 3 0x43000091 FP BE Pri !#7 N11707 P3731 BSTC 4 0x43000092 FP BE Pri !#7 N11708 P3732 MEMBAR !#7 N11709 P3733 BLD 5 -1 FP BE Pri !#7 N11710 P3733 BLD 6 -1 FP BE Pri !#7 N11711 P3734 MEMBAR !#7 N11712 P3735 REPLACEMENT 29 Int BE Pri !#7 N11713 P3736 REPLACEMENT 30 Int BE Pri !#7 N11714 P3737 MEMBAR !#7 N11715 P3738 BLD 19 -1 FP BE Pri !#7 N11716 P3739 MEMBAR !#7 N11717 P3740 LD 26 -1 FP BE Sec !#7 N11718 P3741 ST 19 0x43000093 FP BE Pri !#7 N11719 P3742 MEMBAR !#7 N11720 P3743 BLD 24 -1 FP BE Sec !#7 N11721 P3743 BLD 25 -1 FP BE Sec !#7 N11722 P3744 MEMBAR !#7 N11723 P3745 ST 5 0x43000094 FP BE Pri !#7 N11724 P3746 MEMBAR !#7 N11725 P3747 BLD 0 -1 FP BE Pri !#7 N11726 P3747 BLD 1 -1 FP BE Pri !#A N11725 N11726 !#7 N11727 P3747 BLD 2 -1 FP BE Pri !#7 N11728 P3747 BLD 3 -1 FP BE Pri !#7 N11729 P3747 BLD 4 -1 FP BE Pri !#7 N11730 P3748 MEMBAR !#7 N11731 P3749 ST 21 0x3800014 Int BE Pri !#7 N11732 P3750 MEMBAR !#7 N11733 P3751 BLD 0 -1 FP BE Pri !#7 N11734 P3751 BLD 1 -1 FP BE Pri !#A N11733 N11734 !#7 N11735 P3751 BLD 2 -1 FP BE Pri !#7 N11736 P3751 BLD 3 -1 FP BE Pri !#7 N11737 P3751 BLD 4 -1 FP BE Pri !#7 N11738 P3752 MEMBAR !#7 N11739 P3753 BSTC 18 0x43000095 FP BE Pri !#7 N11740 P3754 MEMBAR !#7 N11741 P3755 BLD 15 -1 FP BE Pri !#7 N11742 P3756 MEMBAR !#7 N11743 P3757 BST 17 0x43000096 FP BE Pri !#7 N11744 P3758 MEMBAR !#7 N11745 P3759 PREFETCH 14 Int BE Pri !#7 N11746 P3760 MEMBAR !#7 N11747 P3761 BST 0 0x43000097 FP BE Pri !#7 N11748 P3761 BST 1 0x43000098 FP BE Pri !#A N11747 N11748 !#7 N11749 P3761 BST 2 0x43000099 FP BE Pri !#7 N11750 P3761 BST 3 0x4300009a FP BE Pri !#7 N11751 P3761 BST 4 0x4300009b FP BE Pri !#7 N11752 P3762 MEMBAR !#7 N11753 P3763 REPLACEMENT 22 Int BE Pri !#7 N11754 P3764 MEMBAR !#7 N11755 P3765 BLD 0 -1 FP BE Pri !#7 N11756 P3765 BLD 1 -1 FP BE Pri !#A N11755 N11756 !#7 N11757 P3765 BLD 2 -1 FP BE Pri !#7 N11758 P3765 BLD 3 -1 FP BE Pri !#7 N11759 P3765 BLD 4 -1 FP BE Pri !#7 N11760 P3766 MEMBAR !#7 N11761 P3767 ST 11 0x3800015 Int BE Sec !#7 N11762 P3768 MEMBAR !#7 N11763 P3769 BSTC 20 0x4300009c FP BE Pri !#7 N11764 P3770 MEMBAR !#7 N11765 P3771 BLD 17 -1 FP BE Sec !#7 N11766 P3772 MEMBAR !#7 N11767 P3773 REPLACEMENT 22 Int BE Pri !#7 N11768 P3774 REPLACEMENT 27 Int BE Pri !#7 N11769 P3775 ST 28 0x4300009d FP BE Pri !#7 N11770 P3776 MEMBAR !#7 N11771 P3777 BLD 5 -1 FP BE Pri !#7 N11772 P3777 BLD 6 -1 FP BE Pri !#7 N11773 P3778 MEMBAR !#7 N11774 P3779 BST 29 0x4300009e FP BE Pri !#7 N11775 P3780 MEMBAR !#7 N11776 P3781 BST 8 0x4300009f FP BE Pri !#7 N11777 P3781 BST 9 0x430000a0 FP BE Pri !#7 N11778 P3782 MEMBAR !#7 N11779 P3783 LD 32 -1 FP BE Pri !#7 N11780 P3784 LD 16 -1 FP BE Pri !#7 N11781 P3785 MEMBAR !#7 N11782 P3786 BSTC 24 0x430000a1 FP BE Sec !#7 N11783 P3786 BSTC 25 0x430000a2 FP BE Sec !#7 N11784 P3787 MEMBAR !#7 N11785 P3788 BST 16 0x430000a3 FP BE Pri !#7 N11786 P3789 MEMBAR !#7 N11787 P3790 ST 12 0x3800016 Int BE Nuc !#7 N11788 P3791 ST 19 0x430000a4 FP BE Pri !#7 N11789 P3792 REPLACEMENT 27 Int BE Sec !#7 N11790 P3793 LD 28 -1 FP BE Sec !#7 N11791 P3794 MEMBAR !#7 N11792 P3795 BSTC 7 0x430000a5 FP BE Pri !#7 N11793 P3796 MEMBAR !#7 N11794 P3797 BLD 16 -1 FP BE Pri !#7 N11795 P3798 MEMBAR !#7 N11796 P3799 ST 24 0x3800017 Int BE Sec !#7 N11797 P3800 REPLACEMENT 13 Int BE Sec !#7 N11798 P3801 ST 5 0x430000a6 FP BE Pri !#7 N11799 P3802 MEMBAR !#7 N11800 P3803 BLD 7 -1 FP BE Pri !#7 N11801 P3804 MEMBAR !#7 N11802 P3805 BLD 21 -1 FP BE Pri !#7 N11803 P3805 BLD 22 -1 FP BE Pri !#A N11802 N11803 !#7 N11804 P3805 BLD 23 -1 FP BE Pri !#7 N11805 P3806 MEMBAR !#7 N11806 P3807 LD 17 -1 Int BE Nuc !#7 N11807 P3808 REPLACEMENT 19 Int BE Pri !#7 N11808 P3809 LD 22 -1 Int BE Pri !#7 N11809 P3810 IDC_FLIP 15 Int BE Pri !#7 N11810 P3811 ST 24 0x3800018 Int BE Sec !#7 N11811 P3812 MEMBAR !#7 N11812 P3813 BSTC 28 0x430000a7 FP BE Sec !#7 N11813 P3814 MEMBAR !#7 N11814 P3815 REPLACEMENT 16 Int BE Pri !#7 N11815 P3816 IDC_FLIP 2 Int BE Pri !#7 N11816 P3817 MEMBAR !#7 N11817 P3818 BST 0 0x430000a8 FP BE Pri !#7 N11818 P3818 BST 1 0x430000a9 FP BE Pri !#A N11817 N11818 !#7 N11819 P3818 BST 2 0x430000aa FP BE Pri !#7 N11820 P3818 BST 3 0x430000ab FP BE Pri !#7 N11821 P3818 BST 4 0x430000ac FP BE Pri !#7 N11822 P3819 MEMBAR !#7 N11823 P3820 PREFETCH 20 Int BE Pri !#7 N11824 P3821 MEMBAR !#7 N11825 P3822 BLD 5 -1 FP BE Pri !#7 N11826 P3822 BLD 6 -1 FP BE Pri !#7 N11827 P3823 MEMBAR !#7 N11828 P3824 LD 9 -1 Int BE Pri !#7 N11829 P3825 MEMBAR !#7 N11830 P3826 BSTC 29 0x430000ad FP BE Pri !#7 N11831 P3827 MEMBAR !#7 N11832 P3828 BLD 0 -1 FP BE Pri !#7 N11833 P3828 BLD 1 -1 FP BE Pri !#A N11832 N11833 !#7 N11834 P3828 BLD 2 -1 FP BE Pri !#7 N11835 P3828 BLD 3 -1 FP BE Pri !#7 N11836 P3828 BLD 4 -1 FP BE Pri !#7 N11837 P3829 MEMBAR !#7 N11838 P3830 BST 0 0x430000ae FP BE Pri !#7 N11839 P3830 BST 1 0x430000af FP BE Pri !#A N11838 N11839 !#7 N11840 P3830 BST 2 0x430000b0 FP BE Pri !#7 N11841 P3830 BST 3 0x430000b1 FP BE Pri !#7 N11842 P3830 BST 4 0x430000b2 FP BE Pri !#7 N11843 P3831 MEMBAR !#7 N11844 P3832 PREFETCH 11 Int BE Pri !#7 N11845 P3833 MEMBAR !#7 N11846 P3834 BLD 21 -1 FP BE Pri !#7 N11847 P3834 BLD 22 -1 FP BE Pri !#A N11846 N11847 !#7 N11848 P3834 BLD 23 -1 FP BE Pri !#7 N11849 P3835 MEMBAR !#7 N11850 P3836 BSTC 0 0x430000b3 FP BE Pri !#7 N11851 P3836 BSTC 1 0x430000b4 FP BE Pri !#A N11850 N11851 !#7 N11852 P3836 BSTC 2 0x430000b5 FP BE Pri !#7 N11853 P3836 BSTC 3 0x430000b6 FP BE Pri !#7 N11854 P3836 BSTC 4 0x430000b7 FP BE Pri !#7 N11855 P3837 MEMBAR !#7 N11856 P3838 BLD 0 -1 FP BE Pri !#7 N11857 P3838 BLD 1 -1 FP BE Pri !#A N11856 N11857 !#7 N11858 P3838 BLD 2 -1 FP BE Pri !#7 N11859 P3838 BLD 3 -1 FP BE Pri !#7 N11860 P3838 BLD 4 -1 FP BE Pri !#7 N11861 P3839 MEMBAR !#7 N11862 P3840 LD 17 -1 FP BE Pri !#7 N11863 P3841 REPLACEMENT 21 Int BE Pri !#7 N11864 P3842 IDC_FLIP 17 Int BE Pri !#7 N11865 P3843 MEMBAR !#7 N11866 P3844 BST 21 0x430000b8 FP BE Pri !#7 N11867 P3844 BST 22 0x430000b9 FP BE Pri !#A N11866 N11867 !#7 N11868 P3844 BST 23 0x430000ba FP BE Pri !#7 N11869 P3845 MEMBAR !#7 N11870 P3846 LD 3 -1 Int BE Pri Loop_exit !#7 N11871 P3640 REPLACEMENT 27 Int BE Pri Loop_entry !#7 N11872 P3641 LD 16 -1 FP BE Pri !#7 N11873 P3642 ST 9 0x430000bb FP BE Pri !#7 N11874 P3643 ST 25 0x430000bc FP BE Sec !#7 N11875 P3644 PREFETCH 22 Int BE Pri !#7 N11876 P3645 LD 24 -1 Int BE Pri !#7 N11877 P3646 PREFETCH 2 Int LE Sec !#7 N11878 P3647 MEMBAR !#7 N11879 P3648 BLD 30 -1 FP BE Pri !#7 N11880 P3649 MEMBAR !#7 N11881 P3650 PREFETCH 12 Int BE Pri !#7 N11882 P3651 MEMBAR !#7 N11883 P3652 BST 31 0x430000bd FP BE Pri !#7 N11884 P3653 MEMBAR !#7 N11885 P3654 REPLACEMENT 4 Int BE Pri !#7 N11886 P3655 MEMBAR !#7 N11887 P3656 BLD 0 -1 FP BE Pri !#7 N11888 P3656 BLD 1 -1 FP BE Pri !#A N11887 N11888 !#7 N11889 P3656 BLD 2 -1 FP BE Pri !#7 N11890 P3656 BLD 3 -1 FP BE Pri !#7 N11891 P3656 BLD 4 -1 FP BE Pri !#7 N11892 P3657 MEMBAR !#7 N11893 P3658 BST 0 0x430000be FP BE Pri !#7 N11894 P3658 BST 1 0x430000bf FP BE Pri !#A N11893 N11894 !#7 N11895 P3658 BST 2 0x430000c0 FP BE Pri !#7 N11896 P3658 BST 3 0x430000c1 FP BE Pri !#7 N11897 P3658 BST 4 0x430000c2 FP BE Pri !#7 N11898 P3659 MEMBAR !#7 N11899 P3660 BST 7 0x430000c3 FP BE Pri !#7 N11900 P3661 MEMBAR !#7 N11901 P3662 PREFETCH 22 Int BE Pri !#7 N11902 P3663 MEMBAR !#7 N11903 P3664 BLD 15 -1 FP BE Pri !#7 N11904 P3665 MEMBAR !#7 N11905 P3666 BSTC 30 0x430000c4 FP BE Pri !#7 N11906 P3667 MEMBAR !#7 N11907 P3668 BLD 31 -1 FP BE Pri !#7 N11908 P3669 MEMBAR !#7 N11909 P3670 ST 4 0x3800019 Int BE Pri !#7 N11910 P3671 LD 9 -1 FP BE Sec !#7 N11911 P3672 ST 10 0x380001a Int BE Pri !#7 N11912 P3673 REPLACEMENT 31 Int BE Pri !#7 N11913 P3674 REPLACEMENT 28 Int BE Pri !#7 N11914 P3675 MEMBAR !#7 N11915 P3676 BLD 18 -1 FP BE Pri !#7 N11916 P3677 MEMBAR !#7 N11917 P3678 LD 25 -1 FP BE Sec !#7 N11918 P3679 REPLACEMENT 14 Int BE Pri !#7 N11919 P3680 MEMBAR !#7 N11920 P3681 BLD 0 -1 FP BE Pri !#7 N11921 P3681 BLD 1 -1 FP BE Pri !#A N11920 N11921 !#7 N11922 P3681 BLD 2 -1 FP BE Pri !#7 N11923 P3681 BLD 3 -1 FP BE Pri !#7 N11924 P3681 BLD 4 -1 FP BE Pri !#7 N11925 P3682 MEMBAR !#7 N11926 P3683 REPLACEMENT 4 Int BE Sec !#7 N11927 P3684 LD 16 -1 Int BE Pri !#7 N11928 P3685 MEMBAR !#7 N11929 P3686 BLD 0 -1 FP BE Pri !#7 N11930 P3686 BLD 1 -1 FP BE Pri !#A N11929 N11930 !#7 N11931 P3686 BLD 2 -1 FP BE Pri !#7 N11932 P3686 BLD 3 -1 FP BE Pri !#7 N11933 P3686 BLD 4 -1 FP BE Pri !#7 N11934 P3687 MEMBAR !#7 N11935 P3688 BLD 20 -1 FP BE Pri !#7 N11936 P3689 MEMBAR !#7 N11937 P3690 BSTC 26 0x430000c5 FP BE Sec !#7 N11938 P3690 BSTC 27 0x430000c6 FP BE Sec !#7 N11939 P3691 MEMBAR !#7 N11940 P3692 BST 24 0x430000c7 FP BE Pri !#7 N11941 P3692 BST 25 0x430000c8 FP BE Pri !#7 N11942 P3693 MEMBAR !#7 N11943 P3694 BLD 28 -1 FP BE Pri !#7 N11944 P3695 MEMBAR !#7 N11945 P3696 BLD 0 -1 FP BE Pri !#7 N11946 P3696 BLD 1 -1 FP BE Pri !#A N11945 N11946 !#7 N11947 P3696 BLD 2 -1 FP BE Pri !#7 N11948 P3696 BLD 3 -1 FP BE Pri !#7 N11949 P3696 BLD 4 -1 FP BE Pri !#7 N11950 P3697 MEMBAR !#7 N11951 P3698 PREFETCH 9 Int BE Pri !#7 N11952 P3699 MEMBAR !#7 N11953 P3700 BLD 14 -1 FP BE Pri !#7 N11954 P3701 MEMBAR !#7 N11955 P3702 BST 30 0x430000c9 FP BE Pri !#7 N11956 P3703 MEMBAR !#7 N11957 P3704 BLD 18 -1 FP BE Pri !#7 N11958 P3705 MEMBAR !#7 N11959 P3706 ST 24 0x380001b Int BE Pri !#7 N11960 P3707 PREFETCH 28 Int BE Pri !#7 N11961 P3708 MEMBAR !#7 N11962 P3709 BLD 16 -1 FP BE Pri !#7 N11963 P3710 MEMBAR !#7 N11964 P3711 BST 30 0x430000ca FP BE Pri !#7 N11965 P3712 MEMBAR !#7 N11966 P3713 BLD 0 -1 FP BE Pri !#7 N11967 P3713 BLD 1 -1 FP BE Pri !#A N11966 N11967 !#7 N11968 P3713 BLD 2 -1 FP BE Pri !#7 N11969 P3713 BLD 3 -1 FP BE Pri !#7 N11970 P3713 BLD 4 -1 FP BE Pri !#7 N11971 P3714 MEMBAR !#7 N11972 P3715 REPLACEMENT 33 Int BE Pri !#7 N11973 P3716 MEMBAR !#7 N11974 P3717 BLD 31 -1 FP BE Pri !#7 N11975 P3718 MEMBAR !#7 N11976 P3719 PREFETCH 6 Int BE Pri !#7 N11977 P3720 MEMBAR !#7 N11978 P3721 BLD 0 -1 FP BE Pri !#7 N11979 P3721 BLD 1 -1 FP BE Pri !#A N11978 N11979 !#7 N11980 P3721 BLD 2 -1 FP BE Pri !#7 N11981 P3721 BLD 3 -1 FP BE Pri !#7 N11982 P3721 BLD 4 -1 FP BE Pri !#7 N11983 P3722 MEMBAR !#7 N11984 P3723 BLD 8 -1 FP BE Pri !#7 N11985 P3723 BLD 9 -1 FP BE Pri !#7 N11986 P3724 MEMBAR !#7 N11987 P3725 BLD 32 -1 FP BE Pri !#7 N11988 P3726 MEMBAR !#7 N11989 P3727 BSTC 7 0x430000cb FP BE Pri !#7 N11990 P3728 MEMBAR !#7 N11991 P3729 BLD 28 -1 FP BE Pri !#7 N11992 P3730 MEMBAR !#7 N11993 P3731 BSTC 0 0x430000cc FP BE Pri !#7 N11994 P3731 BSTC 1 0x430000cd FP BE Pri !#A N11993 N11994 !#7 N11995 P3731 BSTC 2 0x430000ce FP BE Pri !#7 N11996 P3731 BSTC 3 0x430000cf FP BE Pri !#7 N11997 P3731 BSTC 4 0x430000d0 FP BE Pri !#7 N11998 P3732 MEMBAR !#7 N11999 P3733 BLD 5 -1 FP BE Pri !#7 N12000 P3733 BLD 6 -1 FP BE Pri !#7 N12001 P3734 MEMBAR !#7 N12002 P3735 REPLACEMENT 29 Int BE Pri !#7 N12003 P3736 REPLACEMENT 30 Int BE Pri !#7 N12004 P3737 MEMBAR !#7 N12005 P3738 BLD 19 -1 FP BE Pri !#7 N12006 P3739 MEMBAR !#7 N12007 P3740 LD 26 -1 FP BE Sec !#7 N12008 P3741 ST 19 0x430000d1 FP BE Pri !#7 N12009 P3742 MEMBAR !#7 N12010 P3743 BLD 24 -1 FP BE Sec !#7 N12011 P3743 BLD 25 -1 FP BE Sec !#7 N12012 P3744 MEMBAR !#7 N12013 P3745 ST 5 0x430000d2 FP BE Pri !#7 N12014 P3746 MEMBAR !#7 N12015 P3747 BLD 0 -1 FP BE Pri !#7 N12016 P3747 BLD 1 -1 FP BE Pri !#A N12015 N12016 !#7 N12017 P3747 BLD 2 -1 FP BE Pri !#7 N12018 P3747 BLD 3 -1 FP BE Pri !#7 N12019 P3747 BLD 4 -1 FP BE Pri !#7 N12020 P3748 MEMBAR !#7 N12021 P3749 ST 21 0x380001c Int BE Pri !#7 N12022 P3750 MEMBAR !#7 N12023 P3751 BLD 0 -1 FP BE Pri !#7 N12024 P3751 BLD 1 -1 FP BE Pri !#A N12023 N12024 !#7 N12025 P3751 BLD 2 -1 FP BE Pri !#7 N12026 P3751 BLD 3 -1 FP BE Pri !#7 N12027 P3751 BLD 4 -1 FP BE Pri !#7 N12028 P3752 MEMBAR !#7 N12029 P3753 BSTC 18 0x430000d3 FP BE Pri !#7 N12030 P3754 MEMBAR !#7 N12031 P3755 BLD 15 -1 FP BE Pri !#7 N12032 P3756 MEMBAR !#7 N12033 P3757 BST 17 0x430000d4 FP BE Pri !#7 N12034 P3758 MEMBAR !#7 N12035 P3759 PREFETCH 14 Int BE Pri !#7 N12036 P3760 MEMBAR !#7 N12037 P3761 BST 0 0x430000d5 FP BE Pri !#7 N12038 P3761 BST 1 0x430000d6 FP BE Pri !#A N12037 N12038 !#7 N12039 P3761 BST 2 0x430000d7 FP BE Pri !#7 N12040 P3761 BST 3 0x430000d8 FP BE Pri !#7 N12041 P3761 BST 4 0x430000d9 FP BE Pri !#7 N12042 P3762 MEMBAR !#7 N12043 P3763 REPLACEMENT 22 Int BE Pri !#7 N12044 P3764 MEMBAR !#7 N12045 P3765 BLD 0 -1 FP BE Pri !#7 N12046 P3765 BLD 1 -1 FP BE Pri !#A N12045 N12046 !#7 N12047 P3765 BLD 2 -1 FP BE Pri !#7 N12048 P3765 BLD 3 -1 FP BE Pri !#7 N12049 P3765 BLD 4 -1 FP BE Pri !#7 N12050 P3766 MEMBAR !#7 N12051 P3767 ST 11 0x380001d Int BE Sec !#7 N12052 P3768 MEMBAR !#7 N12053 P3769 BSTC 20 0x430000da FP BE Pri !#7 N12054 P3770 MEMBAR !#7 N12055 P3771 BLD 17 -1 FP BE Sec !#7 N12056 P3772 MEMBAR !#7 N12057 P3773 REPLACEMENT 22 Int BE Pri !#7 N12058 P3774 REPLACEMENT 27 Int BE Pri !#7 N12059 P3775 ST 28 0x430000db FP BE Pri !#7 N12060 P3776 MEMBAR !#7 N12061 P3777 BLD 5 -1 FP BE Pri !#7 N12062 P3777 BLD 6 -1 FP BE Pri !#7 N12063 P3778 MEMBAR !#7 N12064 P3779 BST 29 0x430000dc FP BE Pri !#7 N12065 P3780 MEMBAR !#7 N12066 P3781 BST 8 0x430000dd FP BE Pri !#7 N12067 P3781 BST 9 0x430000de FP BE Pri !#7 N12068 P3782 MEMBAR !#7 N12069 P3783 LD 32 -1 FP BE Pri !#7 N12070 P3784 LD 16 -1 FP BE Pri !#7 N12071 P3785 MEMBAR !#7 N12072 P3786 BSTC 24 0x430000df FP BE Sec !#7 N12073 P3786 BSTC 25 0x430000e0 FP BE Sec !#7 N12074 P3787 MEMBAR !#7 N12075 P3788 BST 16 0x430000e1 FP BE Pri !#7 N12076 P3789 MEMBAR !#7 N12077 P3790 ST 12 0x380001e Int BE Nuc !#7 N12078 P3791 ST 19 0x430000e2 FP BE Pri !#7 N12079 P3792 REPLACEMENT 27 Int BE Sec !#7 N12080 P3793 LD 28 -1 FP BE Sec !#7 N12081 P3794 MEMBAR !#7 N12082 P3795 BSTC 7 0x430000e3 FP BE Pri !#7 N12083 P3796 MEMBAR !#7 N12084 P3797 BLD 16 -1 FP BE Pri !#7 N12085 P3798 MEMBAR !#7 N12086 P3799 ST 24 0x380001f Int BE Sec !#7 N12087 P3800 REPLACEMENT 13 Int BE Sec !#7 N12088 P3801 ST 5 0x430000e4 FP BE Pri !#7 N12089 P3802 MEMBAR !#7 N12090 P3803 BLD 7 -1 FP BE Pri !#7 N12091 P3804 MEMBAR !#7 N12092 P3805 BLD 21 -1 FP BE Pri !#7 N12093 P3805 BLD 22 -1 FP BE Pri !#A N12092 N12093 !#7 N12094 P3805 BLD 23 -1 FP BE Pri !#7 N12095 P3806 MEMBAR !#7 N12096 P3807 LD 17 -1 Int BE Nuc !#7 N12097 P3808 REPLACEMENT 19 Int BE Pri !#7 N12098 P3809 LD 22 -1 Int BE Pri !#7 N12099 P3810 IDC_FLIP 15 Int BE Pri !#7 N12100 P3811 ST 24 0x3800020 Int BE Sec !#7 N12101 P3812 MEMBAR !#7 N12102 P3813 BSTC 28 0x430000e5 FP BE Sec !#7 N12103 P3814 MEMBAR !#7 N12104 P3815 REPLACEMENT 16 Int BE Pri !#7 N12105 P3816 IDC_FLIP 2 Int BE Pri !#7 N12106 P3817 MEMBAR !#7 N12107 P3818 BST 0 0x430000e6 FP BE Pri !#7 N12108 P3818 BST 1 0x430000e7 FP BE Pri !#A N12107 N12108 !#7 N12109 P3818 BST 2 0x430000e8 FP BE Pri !#7 N12110 P3818 BST 3 0x430000e9 FP BE Pri !#7 N12111 P3818 BST 4 0x430000ea FP BE Pri !#7 N12112 P3819 MEMBAR !#7 N12113 P3820 PREFETCH 20 Int BE Pri !#7 N12114 P3821 MEMBAR !#7 N12115 P3822 BLD 5 -1 FP BE Pri !#7 N12116 P3822 BLD 6 -1 FP BE Pri !#7 N12117 P3823 MEMBAR !#7 N12118 P3824 LD 9 -1 Int BE Pri !#7 N12119 P3825 MEMBAR !#7 N12120 P3826 BSTC 29 0x430000eb FP BE Pri !#7 N12121 P3827 MEMBAR !#7 N12122 P3828 BLD 0 -1 FP BE Pri !#7 N12123 P3828 BLD 1 -1 FP BE Pri !#A N12122 N12123 !#7 N12124 P3828 BLD 2 -1 FP BE Pri !#7 N12125 P3828 BLD 3 -1 FP BE Pri !#7 N12126 P3828 BLD 4 -1 FP BE Pri !#7 N12127 P3829 MEMBAR !#7 N12128 P3830 BST 0 0x430000ec FP BE Pri !#7 N12129 P3830 BST 1 0x430000ed FP BE Pri !#A N12128 N12129 !#7 N12130 P3830 BST 2 0x430000ee FP BE Pri !#7 N12131 P3830 BST 3 0x430000ef FP BE Pri !#7 N12132 P3830 BST 4 0x430000f0 FP BE Pri !#7 N12133 P3831 MEMBAR !#7 N12134 P3832 PREFETCH 11 Int BE Pri !#7 N12135 P3833 MEMBAR !#7 N12136 P3834 BLD 21 -1 FP BE Pri !#7 N12137 P3834 BLD 22 -1 FP BE Pri !#A N12136 N12137 !#7 N12138 P3834 BLD 23 -1 FP BE Pri !#7 N12139 P3835 MEMBAR !#7 N12140 P3836 BSTC 0 0x430000f1 FP BE Pri !#7 N12141 P3836 BSTC 1 0x430000f2 FP BE Pri !#A N12140 N12141 !#7 N12142 P3836 BSTC 2 0x430000f3 FP BE Pri !#7 N12143 P3836 BSTC 3 0x430000f4 FP BE Pri !#7 N12144 P3836 BSTC 4 0x430000f5 FP BE Pri !#7 N12145 P3837 MEMBAR !#7 N12146 P3838 BLD 0 -1 FP BE Pri !#7 N12147 P3838 BLD 1 -1 FP BE Pri !#A N12146 N12147 !#7 N12148 P3838 BLD 2 -1 FP BE Pri !#7 N12149 P3838 BLD 3 -1 FP BE Pri !#7 N12150 P3838 BLD 4 -1 FP BE Pri !#7 N12151 P3839 MEMBAR !#7 N12152 P3840 LD 17 -1 FP BE Pri !#7 N12153 P3841 REPLACEMENT 21 Int BE Pri !#7 N12154 P3842 IDC_FLIP 17 Int BE Pri !#7 N12155 P3843 MEMBAR !#7 N12156 P3844 BST 21 0x430000f6 FP BE Pri !#7 N12157 P3844 BST 22 0x430000f7 FP BE Pri !#A N12156 N12157 !#7 N12158 P3844 BST 23 0x430000f8 FP BE Pri !#7 N12159 P3845 MEMBAR !#7 N12160 P3846 LD 3 -1 Int BE Pri Loop_exit !#7 N12161 P3640 REPLACEMENT 27 Int BE Pri Loop_entry !#7 N12162 P3641 LD 16 -1 FP BE Pri !#7 N12163 P3642 ST 9 0x430000f9 FP BE Pri !#7 N12164 P3643 ST 25 0x430000fa FP BE Sec !#7 N12165 P3644 PREFETCH 22 Int BE Pri !#7 N12166 P3645 LD 24 -1 Int BE Pri !#7 N12167 P3646 PREFETCH 2 Int LE Sec !#7 N12168 P3647 MEMBAR !#7 N12169 P3648 BLD 30 -1 FP BE Pri !#7 N12170 P3649 MEMBAR !#7 N12171 P3650 PREFETCH 12 Int BE Pri !#7 N12172 P3651 MEMBAR !#7 N12173 P3652 BST 31 0x430000fb FP BE Pri !#7 N12174 P3653 MEMBAR !#7 N12175 P3654 REPLACEMENT 4 Int BE Pri !#7 N12176 P3655 MEMBAR !#7 N12177 P3656 BLD 0 -1 FP BE Pri !#7 N12178 P3656 BLD 1 -1 FP BE Pri !#A N12177 N12178 !#7 N12179 P3656 BLD 2 -1 FP BE Pri !#7 N12180 P3656 BLD 3 -1 FP BE Pri !#7 N12181 P3656 BLD 4 -1 FP BE Pri !#7 N12182 P3657 MEMBAR !#7 N12183 P3658 BST 0 0x430000fc FP BE Pri !#7 N12184 P3658 BST 1 0x430000fd FP BE Pri !#A N12183 N12184 !#7 N12185 P3658 BST 2 0x430000fe FP BE Pri !#7 N12186 P3658 BST 3 0x430000ff FP BE Pri !#7 N12187 P3658 BST 4 0x43000100 FP BE Pri !#7 N12188 P3659 MEMBAR !#7 N12189 P3660 BST 7 0x43000101 FP BE Pri !#7 N12190 P3661 MEMBAR !#7 N12191 P3662 PREFETCH 22 Int BE Pri !#7 N12192 P3663 MEMBAR !#7 N12193 P3664 BLD 15 -1 FP BE Pri !#7 N12194 P3665 MEMBAR !#7 N12195 P3666 BSTC 30 0x43000102 FP BE Pri !#7 N12196 P3667 MEMBAR !#7 N12197 P3668 BLD 31 -1 FP BE Pri !#7 N12198 P3669 MEMBAR !#7 N12199 P3670 ST 4 0x3800021 Int BE Pri !#7 N12200 P3671 LD 9 -1 FP BE Sec !#7 N12201 P3672 ST 10 0x3800022 Int BE Pri !#7 N12202 P3673 REPLACEMENT 31 Int BE Pri !#7 N12203 P3674 REPLACEMENT 28 Int BE Pri !#7 N12204 P3675 MEMBAR !#7 N12205 P3676 BLD 18 -1 FP BE Pri !#7 N12206 P3677 MEMBAR !#7 N12207 P3678 LD 25 -1 FP BE Sec !#7 N12208 P3679 REPLACEMENT 14 Int BE Pri !#7 N12209 P3680 MEMBAR !#7 N12210 P3681 BLD 0 -1 FP BE Pri !#7 N12211 P3681 BLD 1 -1 FP BE Pri !#A N12210 N12211 !#7 N12212 P3681 BLD 2 -1 FP BE Pri !#7 N12213 P3681 BLD 3 -1 FP BE Pri !#7 N12214 P3681 BLD 4 -1 FP BE Pri !#7 N12215 P3682 MEMBAR !#7 N12216 P3683 REPLACEMENT 4 Int BE Sec !#7 N12217 P3684 LD 16 -1 Int BE Pri !#7 N12218 P3685 MEMBAR !#7 N12219 P3686 BLD 0 -1 FP BE Pri !#7 N12220 P3686 BLD 1 -1 FP BE Pri !#A N12219 N12220 !#7 N12221 P3686 BLD 2 -1 FP BE Pri !#7 N12222 P3686 BLD 3 -1 FP BE Pri !#7 N12223 P3686 BLD 4 -1 FP BE Pri !#7 N12224 P3687 MEMBAR !#7 N12225 P3688 BLD 20 -1 FP BE Pri !#7 N12226 P3689 MEMBAR !#7 N12227 P3690 BSTC 26 0x43000103 FP BE Sec !#7 N12228 P3690 BSTC 27 0x43000104 FP BE Sec !#7 N12229 P3691 MEMBAR !#7 N12230 P3692 BST 24 0x43000105 FP BE Pri !#7 N12231 P3692 BST 25 0x43000106 FP BE Pri !#7 N12232 P3693 MEMBAR !#7 N12233 P3694 BLD 28 -1 FP BE Pri !#7 N12234 P3695 MEMBAR !#7 N12235 P3696 BLD 0 -1 FP BE Pri !#7 N12236 P3696 BLD 1 -1 FP BE Pri !#A N12235 N12236 !#7 N12237 P3696 BLD 2 -1 FP BE Pri !#7 N12238 P3696 BLD 3 -1 FP BE Pri !#7 N12239 P3696 BLD 4 -1 FP BE Pri !#7 N12240 P3697 MEMBAR !#7 N12241 P3698 PREFETCH 9 Int BE Pri !#7 N12242 P3699 MEMBAR !#7 N12243 P3700 BLD 14 -1 FP BE Pri !#7 N12244 P3701 MEMBAR !#7 N12245 P3702 BST 30 0x43000107 FP BE Pri !#7 N12246 P3703 MEMBAR !#7 N12247 P3704 BLD 18 -1 FP BE Pri !#7 N12248 P3705 MEMBAR !#7 N12249 P3706 ST 24 0x3800023 Int BE Pri !#7 N12250 P3707 PREFETCH 28 Int BE Pri !#7 N12251 P3708 MEMBAR !#7 N12252 P3709 BLD 16 -1 FP BE Pri !#7 N12253 P3710 MEMBAR !#7 N12254 P3711 BST 30 0x43000108 FP BE Pri !#7 N12255 P3712 MEMBAR !#7 N12256 P3713 BLD 0 -1 FP BE Pri !#7 N12257 P3713 BLD 1 -1 FP BE Pri !#A N12256 N12257 !#7 N12258 P3713 BLD 2 -1 FP BE Pri !#7 N12259 P3713 BLD 3 -1 FP BE Pri !#7 N12260 P3713 BLD 4 -1 FP BE Pri !#7 N12261 P3714 MEMBAR !#7 N12262 P3715 REPLACEMENT 33 Int BE Pri !#7 N12263 P3716 MEMBAR !#7 N12264 P3717 BLD 31 -1 FP BE Pri !#7 N12265 P3718 MEMBAR !#7 N12266 P3719 PREFETCH 6 Int BE Pri !#7 N12267 P3720 MEMBAR !#7 N12268 P3721 BLD 0 -1 FP BE Pri !#7 N12269 P3721 BLD 1 -1 FP BE Pri !#A N12268 N12269 !#7 N12270 P3721 BLD 2 -1 FP BE Pri !#7 N12271 P3721 BLD 3 -1 FP BE Pri !#7 N12272 P3721 BLD 4 -1 FP BE Pri !#7 N12273 P3722 MEMBAR !#7 N12274 P3723 BLD 8 -1 FP BE Pri !#7 N12275 P3723 BLD 9 -1 FP BE Pri !#7 N12276 P3724 MEMBAR !#7 N12277 P3725 BLD 32 -1 FP BE Pri !#7 N12278 P3726 MEMBAR !#7 N12279 P3727 BSTC 7 0x43000109 FP BE Pri !#7 N12280 P3728 MEMBAR !#7 N12281 P3729 BLD 28 -1 FP BE Pri !#7 N12282 P3730 MEMBAR !#7 N12283 P3731 BSTC 0 0x4300010a FP BE Pri !#7 N12284 P3731 BSTC 1 0x4300010b FP BE Pri !#A N12283 N12284 !#7 N12285 P3731 BSTC 2 0x4300010c FP BE Pri !#7 N12286 P3731 BSTC 3 0x4300010d FP BE Pri !#7 N12287 P3731 BSTC 4 0x4300010e FP BE Pri !#7 N12288 P3732 MEMBAR !#7 N12289 P3733 BLD 5 -1 FP BE Pri !#7 N12290 P3733 BLD 6 -1 FP BE Pri !#7 N12291 P3734 MEMBAR !#7 N12292 P3735 REPLACEMENT 29 Int BE Pri !#7 N12293 P3736 REPLACEMENT 30 Int BE Pri !#7 N12294 P3737 MEMBAR !#7 N12295 P3738 BLD 19 -1 FP BE Pri !#7 N12296 P3739 MEMBAR !#7 N12297 P3740 LD 26 -1 FP BE Sec !#7 N12298 P3741 ST 19 0x4300010f FP BE Pri !#7 N12299 P3742 MEMBAR !#7 N12300 P3743 BLD 24 -1 FP BE Sec !#7 N12301 P3743 BLD 25 -1 FP BE Sec !#7 N12302 P3744 MEMBAR !#7 N12303 P3745 ST 5 0x43000110 FP BE Pri !#7 N12304 P3746 MEMBAR !#7 N12305 P3747 BLD 0 -1 FP BE Pri !#7 N12306 P3747 BLD 1 -1 FP BE Pri !#A N12305 N12306 !#7 N12307 P3747 BLD 2 -1 FP BE Pri !#7 N12308 P3747 BLD 3 -1 FP BE Pri !#7 N12309 P3747 BLD 4 -1 FP BE Pri !#7 N12310 P3748 MEMBAR !#7 N12311 P3749 ST 21 0x3800024 Int BE Pri !#7 N12312 P3750 MEMBAR !#7 N12313 P3751 BLD 0 -1 FP BE Pri !#7 N12314 P3751 BLD 1 -1 FP BE Pri !#A N12313 N12314 !#7 N12315 P3751 BLD 2 -1 FP BE Pri !#7 N12316 P3751 BLD 3 -1 FP BE Pri !#7 N12317 P3751 BLD 4 -1 FP BE Pri !#7 N12318 P3752 MEMBAR !#7 N12319 P3753 BSTC 18 0x43000111 FP BE Pri !#7 N12320 P3754 MEMBAR !#7 N12321 P3755 BLD 15 -1 FP BE Pri !#7 N12322 P3756 MEMBAR !#7 N12323 P3757 BST 17 0x43000112 FP BE Pri !#7 N12324 P3758 MEMBAR !#7 N12325 P3759 PREFETCH 14 Int BE Pri !#7 N12326 P3760 MEMBAR !#7 N12327 P3761 BST 0 0x43000113 FP BE Pri !#7 N12328 P3761 BST 1 0x43000114 FP BE Pri !#A N12327 N12328 !#7 N12329 P3761 BST 2 0x43000115 FP BE Pri !#7 N12330 P3761 BST 3 0x43000116 FP BE Pri !#7 N12331 P3761 BST 4 0x43000117 FP BE Pri !#7 N12332 P3762 MEMBAR !#7 N12333 P3763 REPLACEMENT 22 Int BE Pri !#7 N12334 P3764 MEMBAR !#7 N12335 P3765 BLD 0 -1 FP BE Pri !#7 N12336 P3765 BLD 1 -1 FP BE Pri !#A N12335 N12336 !#7 N12337 P3765 BLD 2 -1 FP BE Pri !#7 N12338 P3765 BLD 3 -1 FP BE Pri !#7 N12339 P3765 BLD 4 -1 FP BE Pri !#7 N12340 P3766 MEMBAR !#7 N12341 P3767 ST 11 0x3800025 Int BE Sec !#7 N12342 P3768 MEMBAR !#7 N12343 P3769 BSTC 20 0x43000118 FP BE Pri !#7 N12344 P3770 MEMBAR !#7 N12345 P3771 BLD 17 -1 FP BE Sec !#7 N12346 P3772 MEMBAR !#7 N12347 P3773 REPLACEMENT 22 Int BE Pri !#7 N12348 P3774 REPLACEMENT 27 Int BE Pri !#7 N12349 P3775 ST 28 0x43000119 FP BE Pri !#7 N12350 P3776 MEMBAR !#7 N12351 P3777 BLD 5 -1 FP BE Pri !#7 N12352 P3777 BLD 6 -1 FP BE Pri !#7 N12353 P3778 MEMBAR !#7 N12354 P3779 BST 29 0x4300011a FP BE Pri !#7 N12355 P3780 MEMBAR !#7 N12356 P3781 BST 8 0x4300011b FP BE Pri !#7 N12357 P3781 BST 9 0x4300011c FP BE Pri !#7 N12358 P3782 MEMBAR !#7 N12359 P3783 LD 32 -1 FP BE Pri !#7 N12360 P3784 LD 16 -1 FP BE Pri !#7 N12361 P3785 MEMBAR !#7 N12362 P3786 BSTC 24 0x4300011d FP BE Sec !#7 N12363 P3786 BSTC 25 0x4300011e FP BE Sec !#7 N12364 P3787 MEMBAR !#7 N12365 P3788 BST 16 0x4300011f FP BE Pri !#7 N12366 P3789 MEMBAR !#7 N12367 P3790 ST 12 0x3800026 Int BE Nuc !#7 N12368 P3791 ST 19 0x43000120 FP BE Pri !#7 N12369 P3792 REPLACEMENT 27 Int BE Sec !#7 N12370 P3793 LD 28 -1 FP BE Sec !#7 N12371 P3794 MEMBAR !#7 N12372 P3795 BSTC 7 0x43000121 FP BE Pri !#7 N12373 P3796 MEMBAR !#7 N12374 P3797 BLD 16 -1 FP BE Pri !#7 N12375 P3798 MEMBAR !#7 N12376 P3799 ST 24 0x3800027 Int BE Sec !#7 N12377 P3800 REPLACEMENT 13 Int BE Sec !#7 N12378 P3801 ST 5 0x43000122 FP BE Pri !#7 N12379 P3802 MEMBAR !#7 N12380 P3803 BLD 7 -1 FP BE Pri !#7 N12381 P3804 MEMBAR !#7 N12382 P3805 BLD 21 -1 FP BE Pri !#7 N12383 P3805 BLD 22 -1 FP BE Pri !#A N12382 N12383 !#7 N12384 P3805 BLD 23 -1 FP BE Pri !#7 N12385 P3806 MEMBAR !#7 N12386 P3807 LD 17 -1 Int BE Nuc !#7 N12387 P3808 REPLACEMENT 19 Int BE Pri !#7 N12388 P3809 LD 22 -1 Int BE Pri !#7 N12389 P3810 IDC_FLIP 15 Int BE Pri !#7 N12390 P3811 ST 24 0x3800028 Int BE Sec !#7 N12391 P3812 MEMBAR !#7 N12392 P3813 BSTC 28 0x43000123 FP BE Sec !#7 N12393 P3814 MEMBAR !#7 N12394 P3815 REPLACEMENT 16 Int BE Pri !#7 N12395 P3816 IDC_FLIP 2 Int BE Pri !#7 N12396 P3817 MEMBAR !#7 N12397 P3818 BST 0 0x43000124 FP BE Pri !#7 N12398 P3818 BST 1 0x43000125 FP BE Pri !#A N12397 N12398 !#7 N12399 P3818 BST 2 0x43000126 FP BE Pri !#7 N12400 P3818 BST 3 0x43000127 FP BE Pri !#7 N12401 P3818 BST 4 0x43000128 FP BE Pri !#7 N12402 P3819 MEMBAR !#7 N12403 P3820 PREFETCH 20 Int BE Pri !#7 N12404 P3821 MEMBAR !#7 N12405 P3822 BLD 5 -1 FP BE Pri !#7 N12406 P3822 BLD 6 -1 FP BE Pri !#7 N12407 P3823 MEMBAR !#7 N12408 P3824 LD 9 -1 Int BE Pri !#7 N12409 P3825 MEMBAR !#7 N12410 P3826 BSTC 29 0x43000129 FP BE Pri !#7 N12411 P3827 MEMBAR !#7 N12412 P3828 BLD 0 -1 FP BE Pri !#7 N12413 P3828 BLD 1 -1 FP BE Pri !#A N12412 N12413 !#7 N12414 P3828 BLD 2 -1 FP BE Pri !#7 N12415 P3828 BLD 3 -1 FP BE Pri !#7 N12416 P3828 BLD 4 -1 FP BE Pri !#7 N12417 P3829 MEMBAR !#7 N12418 P3830 BST 0 0x4300012a FP BE Pri !#7 N12419 P3830 BST 1 0x4300012b FP BE Pri !#A N12418 N12419 !#7 N12420 P3830 BST 2 0x4300012c FP BE Pri !#7 N12421 P3830 BST 3 0x4300012d FP BE Pri !#7 N12422 P3830 BST 4 0x4300012e FP BE Pri !#7 N12423 P3831 MEMBAR !#7 N12424 P3832 PREFETCH 11 Int BE Pri !#7 N12425 P3833 MEMBAR !#7 N12426 P3834 BLD 21 -1 FP BE Pri !#7 N12427 P3834 BLD 22 -1 FP BE Pri !#A N12426 N12427 !#7 N12428 P3834 BLD 23 -1 FP BE Pri !#7 N12429 P3835 MEMBAR !#7 N12430 P3836 BSTC 0 0x4300012f FP BE Pri !#7 N12431 P3836 BSTC 1 0x43000130 FP BE Pri !#A N12430 N12431 !#7 N12432 P3836 BSTC 2 0x43000131 FP BE Pri !#7 N12433 P3836 BSTC 3 0x43000132 FP BE Pri !#7 N12434 P3836 BSTC 4 0x43000133 FP BE Pri !#7 N12435 P3837 MEMBAR !#7 N12436 P3838 BLD 0 -1 FP BE Pri !#7 N12437 P3838 BLD 1 -1 FP BE Pri !#A N12436 N12437 !#7 N12438 P3838 BLD 2 -1 FP BE Pri !#7 N12439 P3838 BLD 3 -1 FP BE Pri !#7 N12440 P3838 BLD 4 -1 FP BE Pri !#7 N12441 P3839 MEMBAR !#7 N12442 P3840 LD 17 -1 FP BE Pri !#7 N12443 P3841 REPLACEMENT 21 Int BE Pri !#7 N12444 P3842 IDC_FLIP 17 Int BE Pri !#7 N12445 P3843 MEMBAR !#7 N12446 P3844 BST 21 0x43000134 FP BE Pri !#7 N12447 P3844 BST 22 0x43000135 FP BE Pri !#A N12446 N12447 !#7 N12448 P3844 BST 23 0x43000136 FP BE Pri !#7 N12449 P3845 MEMBAR !#7 N12450 P3846 LD 3 -1 Int BE Pri Loop_exit !#7 N12451 P3847 MEMBAR