// ========== Copyright Header Begin ========================================== // // OpenSPARC T2 Processor File: core_qual_pm.diaglist // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved // 4150 Network Circle, Santa Clara, California 95054, U.S.A. // // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; version 2 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // // For the avoidance of doubt, and except that if any non-GPL license // choice is available it will apply instead, Sun elects to use only // the General Public License version 2 (GPLv2) at this time for any // software where a choice of GPL license versions is made // available with the language indicating that GPLv2 or any later version // may be used, or where a choice of which version of the GPL is applied is // otherwise unspecified. // // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, // CA 95054 USA or visit www.sun.com if you need additional information or // have any questions. // // ========== Copyright Header End ============================================ //Core0_2bank //FAILS OOB // //e2_st_atomic_8t8b_core0_2bank n2_st_atomic_8t8b.s // mpgen_dynamic_caches_core0_2bank mpgen_dynamic_caches.s mpgen_dynamic_pwr_mgmt_core0_2bank mpgen_dynamic_pwr_mgmt.s mpgen_tso_all_banks_core0_2bank mpgen_tso_all_banks.s mpgen_tso_ba_one_bank_core0_2bank mpgen_tso_ba_one_bank.s mpgen_tso_ba_all_banks_core0_2bank mpgen_tso_ba_all_banks.s mpgen_tso_atomic_all_banks_core0_2bank mpgen_tso_atomic_all_banks.s tlu_fcrand05_ind_14_core0_2bank tlu_fcrand05_ind_14.s //FAILS OOB //fcrand05_rand_88_core0_2bank fcrand05_rand_88.s -midas_args=-DMULTIPASS=1 //FAILS OOB //fcrand05_rand_4_core0_2bank fcrand05_rand_4.s -midas_args=-DMULTIPASS=1 //Core0_4bank n2_st_atomic_8t8b_core0_4bank n2_st_atomic_8t8b.s mpgen_dynamic_caches_core0_4bank mpgen_dynamic_caches.s mpgen_dynamic_pwr_mgmt_core0_4bank mpgen_dynamic_pwr_mgmt.s mpgen_tso_all_banks_core0_4bank mpgen_tso_all_banks.s mpgen_tso_ba_one_bank_core0_4bank mpgen_tso_ba_one_bank.s mpgen_tso_ba_all_banks_core0_4bank mpgen_tso_ba_all_banks.s mpgen_tso_atomic_all_banks_core0_4bank mpgen_tso_atomic_all_banks.s //FAILS TIMEOUT //tlu_fcrand05_ind_14_core0_4bank tlu_fcrand05_ind_14.s //FAILS OOB //fcrand05_rand_88_core0_4bank fcrand05_rand_88.s -midas_args=-DMULTIPASS=1 //FAILS ESR //fcrand05_rand_4_core0_4bank fcrand05_rand_4.s -midas_args=-DMULTIPASS=1 //Core1_2bank //FAILS OOB // //n2_st_atomic_8t8b_core1_2bank n2_st_atomic_8t8b.s // mpgen_dynamic_caches_core1_2bank mpgen_dynamic_caches.s mpgen_dynamic_pwr_mgmt_core1_2bank mpgen_dynamic_pwr_mgmt.s mpgen_tso_all_banks_core1_2bank mpgen_tso_all_banks.s mpgen_tso_ba_one_bank_core1_2bank mpgen_tso_ba_one_bank.s mpgen_tso_ba_all_banks_core1_2bank mpgen_tso_ba_all_banks.s mpgen_tso_atomic_all_banks_core1_2bank mpgen_tso_atomic_all_banks.s tlu_fcrand05_ind_14_core1_2bank tlu_fcrand05_ind_14.s //FAILS OOB //fcrand05_rand_88_core1_2bank fcrand05_rand_88.s -midas_args=-DMULTIPASS=1 //FAILS ESR //fcrand05_rand_4_core1_2bank fcrand05_rand_4.s -midas_args=-DMULTIPASS=1 //Core1_4bank n2_st_atomic_8t8b_core1_4bank n2_st_atomic_64t.s mpgen_dynamic_caches_core1_4bank mpgen_dynamic_caches.s mpgen_dynamic_pwr_mgmt_core1_4bank mpgen_dynamic_pwr_mgmt.s mpgen_tso_all_banks_core1_4bank mpgen_tso_all_banks.s mpgen_tso_ba_one_bank_core1_4bank mpgen_tso_ba_one_bank.s mpgen_tso_ba_all_banks_core1_4bank mpgen_tso_ba_all_banks.s mpgen_tso_atomic_all_banks_core1_4bank mpgen_tso_atomic_all_banks.s tlu_fcrand05_ind_14_core1_4bank tlu_fcrand05_ind_14.s //FAILS OOB //fcrand05_rand_88_core1_4bank fcrand05_rand_88.s -midas_args=-DMULTIPASS=1 //FAILS ESR //fcrand05_rand_4_core1_4bank fcrand05_rand_4.s -midas_args=-DMULTIPASS=1 //Core1_8bank n2_st_atomic_8t8b_core1_8bank n2_st_atomic_64t.s mpgen_dynamic_caches_core1_8bank mpgen_dynamic_caches.s mpgen_dynamic_pwr_mgmt_core1_8bank mpgen_dynamic_pwr_mgmt.s mpgen_tso_all_banks_core1_8bank mpgen_tso_all_banks.s mpgen_tso_ba_one_bank_core1_8bank mpgen_tso_ba_one_bank.s mpgen_tso_ba_all_banks_core1_8bank mpgen_tso_ba_all_banks.s mpgen_tso_atomic_all_banks_core1_8bank mpgen_tso_atomic_all_banks.s tlu_fcrand05_ind_14_core1_8bank tlu_fcrand05_ind_14.s //FAILS OOB //fcrand05_rand_88_core1_8bank fcrand05_rand_88.s -midas_args=-DMULTIPASS=1 //FAILS ESR //fcrand05_rand_4_core1_8bank fcrand05_rand_4.s -midas_args=-DMULTIPASS=1 //Core1257_4bank n2_st_atomic_8t8b_core1257_4bank n2_st_atomic_64t.s //UNFINISHED //mpgen_dynamic_caches_core1257_4bank mpgen_dynamic_caches.s //mpgen_dynamic_pwr_mgmt_core1257_4bank mpgen_dynamic_pwr_mgmt.s mpgen_tso_all_banks_core1257_4bank mpgen_tso_all_banks.s //mpgen_tso_ba_one_bank_core1257_4bank mpgen_tso_ba_one_bank.s mpgen_tso_ba_all_banks_core1257_4bank mpgen_tso_ba_all_banks.s mpgen_tso_atomic_all_banks_core1257_4bank mpgen_tso_atomic_all_banks.s tlu_fcrand05_ind_14_core1257_4bank tlu_fcrand05_ind_14.s //FAILS OOB //fcrand05_rand_88_core1257_4bank fcrand05_rand_88.s -midas_args=-DMULTIPASS=1 //FAILS ESR //fcrand05_rand_4_core1257_4bank fcrand05_rand_4.s -midas_args=-DMULTIPASS=1