// ========== Copyright Header Begin ========================================== // // OpenSPARC T2 Processor File: FcNiuQual.diaglist // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved // 4150 Network Circle, Santa Clara, California 95054, U.S.A. // // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; version 2 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // // For the avoidance of doubt, and except that if any non-GPL license // choice is available it will apply instead, Sun elects to use only // the General Public License version 2 (GPLv2) at this time for any // software where a choice of GPL license versions is made // available with the language indicating that GPLv2 or any later version // may be used, or where a choice of which version of the GPL is applied is // otherwise unspecified. // // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, // CA 95054 USA or visit www.sun.com if you need additional information or // have any questions. // // ========== Copyright Header End ============================================ // **************************************************************************** // NIU PIO Read & Write // **************************************************************************** // FcNiuPioWrRd basic_niu_pio_mask.s -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1 // // **************************************************************************** // **************************************************************************** // 10G -> MAC0 -> NIU Tx. // **************************************************************************** // FcNiu10GMac0Tx FcNiuBasicTx.s FcNiuTx_DMA15_PktCnt25_PktLen_Gather FcNiuBasicTx.s FcNiuTx_DMA15_PktCnt25_PktLen_Gather_Xlate FcNiuBasicTx.s // // **************************************************************************** // **************************************************************************** // 10G -> MAC0 -> NIU Rx. // **************************************************************************** // FcNiu10GMac0Rx FcNiuBasicRx_sweep1.s FcNiuRx_DMA1 FcNiuBasicRx_sweep1.s FcNiuRx_DMA1_Xlate FcNiuBasicRx_sweep1.s // // **************************************************************************** // **************************************************************************** // 10G -> MAC1 -> NIU Tx. // **************************************************************************** // FcNiu10GMac1Tx FcNiuBasicTx.s FcNiuTx_McPort1_DMA15_PktCnt25_PktLen_Gather FcNiuBasicTx.s // // **************************************************************************** // **************************************************************************** // 10G -> MAC1 -> NIU Rx. // **************************************************************************** // FcNiu10GMac1Rx FcNiuBasicRx_sweep1.s // // **************************************************************************** // **************************************************************************** // NIU Tx + Rx (Multi-threaded). // **************************************************************************** // FcNiuBasicTxRx FcNiuBasicTxRx.s // // ****************************************************************************