// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: fc8_mode.diaglist
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
<sys(mode8) name=sys(mode8)>
<sys(all)>


//Add sas later

//Core1 
<runargs  -nosas -vcs_run -vcs_run_args=+l2esr_mon_off  -vcs_run_args=+core_set_mask=02 >

cores1_allbanks_atomic allcores_allbanks_atomic.s -midas_args=-DCMP_THREAD_START=0x0100 -finish_mask=0100 -vcs_run_args=+threads=0100

allbanks_cores1 allbanks_allcores.s -midas_args=-DCMP_THREAD_START=0xff00 -finish_mask=ff00 -vcs_run_args=+threads=ff00

</runargs>

//Core2 
<runargs  -nosas -vcs_run -vcs_run_args=+l2esr_mon_off  -vcs_run_args=+core_set_mask=04  >

cores2_allbanks_atomic allcores_allbanks_atomic.s -midas_args=-DCMP_THREAD_START=0x010000 -finish_mask=010000 -vcs_run_args=+threads=010000

allbanks_cores2 allbanks_allcores.s -midas_args=-DCMP_THREAD_START=0xff0000 -finish_mask=ff0000 -vcs_run_args=+threads=ff0000
</runargs>

//Core3 
<runargs  -nosas -vcs_run -vcs_run_args=+l2esr_mon_off  -vcs_run_args=+core_set_mask=08>

cores3_allbanks_atomic allcores_allbanks_atomic.s -midas_args=-DCMP_THREAD_START=0x01000000 -finish_mask=01000000

allbanks_cores3 allbanks_allcores.s -midas_args=-DCMP_THREAD_START=0xff000000 -finish_mask=ff000000 -vcs_run_args=+threads=ff000000
</runargs>

//Core4 
<runargs  -nosas -vcs_run -vcs_run_args=+l2esr_mon_off  -vcs_run_args=+core_set_mask=10  >

cores4_allbanks_atomic allcores_allbanks_atomic.s -midas_args=-DCMP_THREAD_START=0x0000000100000000 -finish_mask=0000000100000000 -vcs_run_args=+threads=0000000100000000

allbanks_cores4 allbanks_allcores.s -midas_args=-DCMP_THREAD_START=0xff00000000 -finish_mask=ff00000000 -vcs_run_args=+threads=ff00000000
</runargs>

//Core5 
<runargs  -nosas -vcs_run -vcs_run_args=+l2esr_mon_off  -vcs_run_args=+core_set_mask=20  >

cores5_allbanks_atomic allcores_allbanks_atomic.s -midas_args=-DCMP_THREAD_START=0x0000010000000000 -finish_mask=0000010000000000 -vcs_run_args=+threads=0000010000000000

allbanks_cores5 allbanks_allcores.s -midas_args=-DCMP_THREAD_START=0xff0000000000 -finish_mask=ff0000000000 -vcs_run_args=+threads=ff0000000000

</runargs>
//Core 6
<runargs  -nosas -vcs_run -vcs_run_args=+l2esr_mon_off  -vcs_run_args=+core_set_mask=40  >

cores6_allbanks_atomic allcores_allbanks_atomic.s -midas_args=-DCMP_THREAD_START=0x0001000000000000 -finish_mask=0001000000000000 -vcs_run_args=+threads=0001000000000000

allbanks_cores6 allbanks_allcores.s  -midas_args=-DCMP_THREAD_START=0xff000000000000 -finish_mask=ff000000000000 -vcs_run_args=+threads=ff000000000000
</runargs>

//Core 7 
<runargs  -nosas -vcs_run -vcs_run_args=+l2esr_mon_off  -vcs_run_args=+core_set_mask=80  >

cores7_allbanks_atomic allcores_allbanks_atomic.s -midas_args=-DCMP_THREAD_START=0x0100000000000000 -finish_mask=0100000000000000

allbanks_cores7 allbanks_allcores.s  -midas_args=-DCMP_THREAD_START=0xff00000000000000 -finish_mask=ff00000000000000 -vcs_run_args=+threads=ff00000000000000
</runargs>


//L2 Partial Bank 01
<runargs  -nosas -vcs_run   -vcs_run_args=+bank_set_mask=1 -vcs_run_args=+l2esr_mon_off  -vcs_run_args=+core_set_mask=03  >

memop_ccx_packets_pm01       memop_ccx_packets.s

memop_word_byte_mask_pm01    memop_word_byte_mask.s

allcores_allbanks_atomic_pm01   allcores_allbanks_atomic.s

n2_l2_fc_bank0_wayb_f_ldx_pm01 n2_l2_fc_bank0_wayb_f_ldx.s

n2_l2_fc_bank1_wayb_f_ldx_pm01 n2_l2_fc_bank1_wayb_f_ldx.s

</runargs>

//L2 Partial Bank 23
<runargs  -nosas -vcs_run   -vcs_run_args=+bank_set_mask=2 -vcs_run_args=+l2esr_mon_off  -vcs_run_args=+core_set_mask=03  >

memop_ccx_packets_pm23       memop_ccx_packets.s

memop_word_byte_mask_pm23    memop_word_byte_mask.s

allcores_allbanks_atomic_pm23   allcores_allbanks_atomic.s

n2_l2_fc_bank2_wayb_f_ldx_pm23 n2_l2_fc_bank2_wayb_f_ldx.s

n2_l2_fc_bank3_wayb_f_ldx_pm23 n2_l2_fc_bank3_wayb_f_ldx.s

</runargs>

//L2 Partial Bank 45 
<runargs  -nosas -vcs_run   -vcs_run_args=+bank_set_mask=4 -vcs_run_args=+l2esr_mon_off  -vcs_run_args=+core_set_mask=03  >

memop_ccx_packets_pm45       memop_ccx_packets.s

memop_word_byte_mask_pm45    memop_word_byte_mask.s

allcores_allbanks_atomic_pm45   allcores_allbanks_atomic.s

n2_l2_fc_bank4_wayb_f_ldx_pm45 n2_l2_fc_bank4_wayb_f_ldx.s

n2_l2_fc_bank5_wayb_f_ldx_pm45 n2_l2_fc_bank5_wayb_f_ldx.s

</runargs>

//L2 Partial Bank 67
<runargs  -nosas -vcs_run   -vcs_run_args=+bank_set_mask=8 -vcs_run_args=+l2esr_mon_off  -vcs_run_args=+core_set_mask=03  >

memop_ccx_packets_pm67       memop_ccx_packets.s

memop_word_byte_mask_pm67    memop_word_byte_mask.s

allcores_allbanks_atomic_pm67   allcores_allbanks_atomic.s

n2_l2_fc_bank6_wayb_f_ldx_pm67 n2_l2_fc_bank6_wayb_f_ldx.s

n2_l2_fc_bank7_wayb_f_ldx_pm67 n2_l2_fc_bank7_wayb_f_ldx.s

</runargs>

//L2 Partial Bank 01 23
<runargs  -nosas -vcs_run   -vcs_run_args=+bank_set_mask=3 -vcs_run_args=+l2esr_mon_off  -vcs_run_args=+core_set_mask=03  >

memop_ccx_packets_pm0123       memop_ccx_packets.s

memop_word_byte_mask_pm0123    memop_word_byte_mask.s

allcores_allbanks_atomic_pm0123   allcores_allbanks_atomic.s

n2_l2_fc_bank0_wayb_f_ldx_pm0123 n2_l2_fc_bank0_wayb_f_ldx.s

n2_l2_fc_bank2_wayb_f_ldx_pm0123 n2_l2_fc_bank2_wayb_f_ldx.s

</runargs>

//L2 Partial Bank 01 45
<runargs  -nosas -vcs_run   -vcs_run_args=+bank_set_mask=5 -vcs_run_args=+l2esr_mon_off  -vcs_run_args=+core_set_mask=03  >

memop_ccx_packets_pm0145       memop_ccx_packets.s

memop_word_byte_mask_pm0145    memop_word_byte_mask.s

allcores_allbanks_atomic_pm0145   allcores_allbanks_atomic.s

n2_l2_fc_bank0_wayb_f_ldx_pm0145 n2_l2_fc_bank0_wayb_f_ldx.s

n2_l2_fc_bank5_wayb_f_ldx_pm0145 n2_l2_fc_bank5_wayb_f_ldx.s

</runargs>

//L2 Partial Bank 01 67
<runargs  -nosas -vcs_run   -vcs_run_args=+bank_set_mask=9 -vcs_run_args=+l2esr_mon_off  -vcs_run_args=+core_set_mask=0f  >

memop_ccx_packets_pm0167       memop_ccx_packets.s

memop_word_byte_mask_pm0167    memop_word_byte_mask.s

allcores_allbanks_atomic_pm0167   allcores_allbanks_atomic.s

n2_l2_fc_bank6_wayb_f_ldx_pm0167 n2_l2_fc_bank6_wayb_f_ldx.s

n2_l2_fc_bank1_wayb_f_ldx_pm0167 n2_l2_fc_bank1_wayb_f_ldx.s

</runargs>

//L2 Partial Bank 23 45
<runargs  -nosas -vcs_run   -vcs_run_args=+bank_set_mask=6 -vcs_run_args=+l2esr_mon_off  -vcs_run_args=+core_set_mask=0f  >

memop_ccx_packets_pm2345       memop_ccx_packets.s

memop_word_byte_mask_pm2345    memop_word_byte_mask.s

allcores_allbanks_atomic_pm2345   allcores_allbanks_atomic.s

n2_l2_fc_bank3_wayb_f_ldx_pm2345 n2_l2_fc_bank3_wayb_f_ldx.s

n2_l2_fc_bank5_wayb_f_ldx_pm2345 n2_l2_fc_bank5_wayb_f_ldx.s

</runargs>

//L2 Partial Bank 23 67
<runargs  -nosas -vcs_run   -vcs_run_args=+bank_set_mask=a -vcs_run_args=+l2esr_mon_off  -vcs_run_args=+core_set_mask=03  >

memop_ccx_packets_pm2367       memop_ccx_packets.s

memop_word_byte_mask_pm2367    memop_word_byte_mask.s

allcores_allbanks_atomic_pm2367   allcores_allbanks_atomic.s

n2_l2_fc_bank2_wayb_f_ldx_pm2367 n2_l2_fc_bank2_wayb_f_ldx.s

n2_l2_fc_bank7_wayb_f_ldx_pm2367 n2_l2_fc_bank7_wayb_f_ldx.s

</runargs>

//L2 Partial Bank 45 67

<runargs  -nosas -vcs_run   -vcs_run_args=+bank_set_mask=c -vcs_run_args=+l2esr_mon_off  -vcs_run_args=+core_set_mask=03  >

memop_ccx_packets_pm4567       memop_ccx_packets.s

memop_word_byte_mask_pm4567    memop_word_byte_mask.s

allcores_allbanks_atomic_pm4567   allcores_allbanks_atomic.s

n2_l2_fc_bank6_wayb_f_ldx_pm4567 n2_l2_fc_bank6_wayb_f_ldx.s

n2_l2_fc_bank5_wayb_f_ldx_pm4567 n2_l2_fc_bank5_wayb_f_ldx.s

</runargs>

</sys(all)>

<sys(daily)>

<runargs  -nosas -vcs_run   -vcs_run_args=+bank_set_mask=c -vcs_run_args=+l2esr_mon_off  -vcs_run_args=+core_set_mask=03  >

memop_ccx_packets_pm4567       memop_ccx_packets.s
allcores_allbanks_atomic_pm4567   allcores_allbanks_atomic.s

</runargs>
</sys(daily)>



</sys(mode8)>