// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: fc_dbp.diaglist
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
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// ========== Copyright Header End ============================================
<sys(tcu_no_tck) name=sys(tcu_no_tck)>
<runargs  -midas_args=-DINC_SOC_ERR_TRAPS -midas_args=-DCREGS_L2_ERR_EN_REG_CEEN=0 -midas_args=-DCREGS_L2_ERR_EN_REG_NCEEN=0 -vcs_run_args=+ios_0in_ras_chk_off >
      tcu_csr_regs_rw tcu_csr_regs_rw.s -nosas
      tcu_regs_asi       tcu_regs_asi.s
      tcu_regs_l2        tcu_regs_l2.s
      tcu_regs_peu       tcu_regs_peu.s
      tcu_regs_soc       tcu_regs_soc.s
      tcu_regs_bist      tcu_regs_bist.s -nosas
</runargs>

<runargs  -midas_args=-DINC_SOC_ERR_TRAPS -midas_args=-DCREGS_L2_ERR_EN_REG_CEEN=0 -midas_args=-DCREGS_L2_ERR_EN_REG_NCEEN=0 -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+MCU_REG_DEFAULT_VAL -vcs_run_args=+NO_MCU_CSR_SLAM>
      tcu_regs_dram      tcu_regs_dram.s      -nofast_boot
      tcu_regs_dram_2    tcu_regs_dram_2.s    -nofast_boot
      tcu_regs_dram_piu  tcu_regs_dram_piu.s  -nofast_boot
</runargs>

</sys(tcu_no_tck)>


///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////

<sys(dbg) name=sys(dbg)>
<runargs -vcs_run_args=-DL2_7 -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_errmon_off -max_cycle=+50000 -nosas -vcs_run_args=+mcu_fmon_disable -vcs_run_args=+mcu_errmon_disable -vcs_run_args=+DISABLE_L2_CHECKER -vcs_run_args=+BOOT_CODE_FINISH=13000000 -vcs_run_args=+TIMEOUT=10000 -vcs_run_args=+PEU_TEST>
Debug_Event_Mcu_Ctl2	 Debug_Event_Mcu2.s
</runargs>

<runargs -nosas -midas_args=-DINC_SOC_ERR_TRAPS -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_mon_off -vcs_run_args=+l2cpx_errmon_off -max_cycle=+100000 -midas_args=-DCREGS_L2_ERR_EN_REG_CEEN=0 -midas_args=-DCREGS_L2_ERR_EN_REG_NCEEN=0 -vcs_run_args=+ios_0in_ras_chk_off>
Debug_Event_L2_PABank0  Debug_Event_L2PaBank.s -midas_args=-DMCU0
Debug_Event_L2_PABank2  Debug_Event_L2PaBank.s -midas_args=-DMCU1
Debug_Event_L2_PABank4  Debug_Event_L2PaBank.s -midas_args=-DMCU2
Debug_Event_L2_PABank6  Debug_Event_L2PaBank.s -midas_args=-DMCU3
Debug_Event_L2_PABank1  Debug_Event_L2PaBankOdd.s -midas_args=-DMCU0
Debug_Event_L2_PABank3  Debug_Event_L2PaBankOdd.s -midas_args=-DMCU1
Debug_Event_L2_PABank5  Debug_Event_L2PaBankOdd.s -midas_args=-DMCU2
Debug_Event_L2_PABank7  Debug_Event_L2PaBankOdd.s -midas_args=-DMCU3
</runargs>




<runargs -nosas -midas_args=-DINC_SOC_ERR_TRAPS -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_mon_off -vcs_run_args=+l2cpx_errmon_off -max_cycle=+100000 -midas_args=-DCREGS_L2_ERR_EN_REG_CEEN=0 -midas_args=-DCREGS_L2_ERR_EN_REG_NCEEN=0 -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+DISABLE_L2_CHECKER>
Debug_Event_Mcu_Ctl0     Debug_Event_Mcu.s   -midas_args=-DMCU0
Debug_Event_Mcu_Ctl1     Debug_Event_Mcu.s   -midas_args=-DMCU1
Debug_Event_Mcu_Ctl2     Debug_Event_Mcu.s   -midas_args=-DMCU2
Debug_Event_Mcu_Ctl3     Debug_Event_Mcu.s   -midas_args=-DMCU3
</runargs>

<runargs  -nosas -midas_args=-DINC_SOC_ERR_TRAPS -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_mon_off -vcs_run_args=+l2cpx_errmon_off -max_cycle=+100000 -midas_args=-DCREGS_L2_ERR_EN_REG_CEEN=0 -midas_args=-DCREGS_L2_ERR_EN_REG_NCEEN=0 -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+DISABLE_L2_CHECKER>
Debug_Event_L2Bank0     Debug_Event_L2.s  -midas_args=-DL2_0 -midas_args=-DMCU0
Debug_Event_L2Bank2     Debug_Event_L2.s  -midas_args=-DL2_2 -midas_args=-DMCU1
Debug_Event_L2Bank4     Debug_Event_L2.s  -midas_args=-DL2_4 -midas_args=-DMCU2
Debug_Event_L2Bank6     Debug_Event_L2.s  -midas_args=-DL2_6 -midas_args=-DMCU3
</runargs>


<runargs  -nosas -midas_args=-DINC_SOC_ERR_TRAPS -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_mon_off -vcs_run_args=+l2cpx_errmon_off -max_cycle=+100000 -midas_args=-DCREGS_L2_ERR_EN_REG_CEEN=0 -midas_args=-DCREGS_L2_ERR_EN_REG_NCEEN=0 -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+DISABLE_L2_CHECKER>
Debug_Event_L2Bank1     Debug_Event_L2Odd.s  -midas_args=-DMCU0
Debug_Event_L2Bank3     Debug_Event_L2Odd.s  -midas_args=-DMCU1
Debug_Event_L2Bank5     Debug_Event_L2Odd.s  -midas_args=-DMCU2
Debug_Event_L2Bank7     Debug_Event_L2Odd.s  -midas_args=-DMCU3
</runargs>




<runargs -vcs_run_args=+PEU_TEST -vcs_run_args=+DISABLE_L2_CHECKER -vcs_run_args=+mcu_errmon_disable -vcs_run_args=+mcu_fmon_disable -vcs_run_args=+l2cpx_errmon_off -max_cycle=+50000 -nosas -vcs_run_args=+l2esr_mon_off -midas_args=-DL2_0 -vcs_run_args=+ios_0in_ras_chk_off>
Debug_CoreSoc_Soc      Debug_CoreSoc_Soc.s
Debug_Tester_Soc       Debug_Tester_Soc.s
Debug_Event_L2pa       Debug_Event_L2_Pa.s
</runargs>

<runargs -vcs_run_args=+PEU_TEST -midas_args=-DERR_FIELD=NcuCtagUe -vcs_run_args=+ios_0in_ras_chk_off -midas_args=-DCMP_THREAD_START=0x3 -finish_mask=2>
Debug_Event_Soc	   	 Debug_Event_Soc.s
</runargs>

<runargs -vcs_run_args=+0in_no_statistics -fast_boot -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_errmon_off -nosas -vcs_run_args=+mcu_fmon_disable -vcs_run_args=+mcu_errmon_disable  -vcs_run_args=+DISABLE_L2_CHECKER -drm_type=rgrs -tg_seed=1 -sas -vcs_run_args=+PEU_TEST>
Debug_Pciex_Obs	    Debug_Pciex_Mode.s
</runargs>

#ifndef FC_NO_NIU_T2
<runargs -nosas -midas_args=-DINC_SOC_ERR_TRAPS -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_mon_off -vcs_run_args=+l2cpx_errmon_off -max_cycle=+100000 -midas_args=-DCREGS_L2_ERR_EN_REG_CEEN=0 -midas_args=-DCREGS_L2_ERR_EN_REG_NCEEN=0 -midas_args=-DMCU1 -vcs_run_args=+ios_0in_ras_chk_off>
//Debug_Niu_Obs	Debug_Niu_Mode.s
</runargs>
#endif

<runargs -midas_args=-DERR_FIELD=SiiNiuCtagCe -vcs_run_args=+ios_0in_ras_chk_off -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1 -vcs_run_args=+MAC_SPEED0=10000 -vcs_run_args=+MAC_SPEED1=10000 -vcs_run_args=+GET_MAC_PORTS=0 -vcs_run_args=+PCS_SERDES -vcs_run_args=+displaySysRdWr -vcs_run_args=+ORIG_META -vcs_run_args=+TX_TEST -midas_args=-DTX_TEST -midas_args=-DMAC_SPEED0=10000 -midas_args=-DMAC_SPEED1=10000 -midas_args=-DPCS_SERDES -vcs_run_args=+PEU_TEST -vcs_run_args=+ENABLE_PCIE_LINK_TRAINING -midas_args=-DENABLE_PCIE_LINK_TRAINING -nosas>
Debug_Quiscen_Mode	 Debug_Quiscen_Mode.s
</runargs>

<runargs -midas_args=-DERR_FIELD=SiiNiuCtagCe -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1 -vcs_run_args=+MAC_SPEED0=10000 -vcs_run_args=+MAC_SPEED1=10000 -vcs_run_args=+GET_MAC_PORTS=0 -vcs_run_args=+PCS_SERDES -vcs_run_args=+displaySysRdWr -vcs_run_args=+ORIG_META -vcs_run_args=+TX_TEST -midas_args=-DTX_TEST -midas_args=-DMAC_SPEED0=10000 -midas_args=-DMAC_SPEED1=10000 -midas_args=-DPCS_SERDES -vcs_run_args=+PEU_TEST -vcs_run_args=+ENABLE_PCIE_LINK_TRAINING -midas_args=-DENABLE_PCIE_LINK_TRAINING  -vcs_run_args=+ios_0in_ras_chk_off -nosas> 
Debug_Repeatable_Mode	Debug_Niu_Repeatable.s
</runargs>

<runargs -nouse_cdms_iver -vcs_run_args=+0in_no_statistics -fast_boot -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_errmon_off -nosas -vcs_run_args=+mcu_fmon_disable -vcs_run_args=+mcu_errmon_disable -vcs_run_args=+DISABLE_L2_CHECKER  -tg_seed=1  -sas -vcs_run_args=+PEU_TEST>
Debug_Dmu_Quiscen	 Debug_Dmu_Quiscen.s
</runargs>

<runargs -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1 -vcs_run_args=+MAC_SPEED0=10000 -vcs_run_args=+MAC_SPEED1=10000  -vcs_run_args=+GET_MAC_PORTS=0 -vcs_run_args=+PCS_SERDES -vcs_run_args=+displaySysRdWr -vcs_run_args=+ORIG_META -vcs_run_args=+TX_TEST -midas_args=-DTX_TEST -midas_args=-DMAC_SPEED0=10000 -midas_args=-DMAC_SPEED1=10000 -midas_args=-DPCS_SERDES -vcs_run_args=+PEU_TEST -vcs_run_args=+ENABLE_PCIE_LINK_TRAINING -midas_args=-DENABLE_PCIE_LINK_TRAINING -midas_args=-DERR_FIELD=SiiDmuDParity -vcs_run_args=+DISABLE_L2_CHECKER -vcs_run_args=+ios_0in_ras_chk_off>
Debug_Event_Dmu 	Debug_Event_Dmu.s
</runargs>

</sys(dbg)>