// ========== Copyright Header Begin ========================================== // // OpenSPARC T2 Processor File: spc_fast_axis.diaglist // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved // 4150 Network Circle, Santa Clara, California 95054, U.S.A. // // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; version 2 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // // For the avoidance of doubt, and except that if any non-GPL license // choice is available it will apply instead, Sun elects to use only // the General Public License version 2 (GPLv2) at this time for any // software where a choice of GPL license versions is made // available with the language indicating that GPLv2 or any later version // may be used, or where a choice of which version of the GPL is applied is // otherwise unspecified. // // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, // CA 95054 USA or visit www.sun.com if you need additional information or // have any questions. // // ========== Copyright Header End ============================================ // seed locked to 1 for regression ldst_sync_fc0 ldst_sync_fc0.s ldst_sync_fc1 ldst_sync_fc1.s -vcs_run_args=+inval_rate=500 isa3_scratchpad_f2 isa3_scratchpad_f2.s isa3_mmu_21_52_f1 isa3_mmu_21_52_f1.s isa3_scratchpad_f2_4u isa3_scratchpad_f2.s -midas_args=-ttefmt=sun4u isa3_mmu_21_52_f1_4u isa3_mmu_21_52_f1.s -midas_args=-ttefmt=sun4u tlu_rand01_ind_04 tlu_rand01_ind_04.s tlu_rand02_ind_05 tlu_rand02_ind_05.s tlu_rand02_ind_03 tlu_rand02_ind_03.s isa3_basic0_f0 isa3_basic0_f0.s //isa3_fsr0_f0 isa3_fsr0_f0.s //isa3_window0_f0 isa3_window0_f0.s isa3_flushw_fc0 isa3_flushw_fc0.s kaos_01_07_2004_1 kaos_01_07_2004_1.s -midas_args=-allow_tsb_conflicts // review later to -vcs_run_args=+thread=all //isa3_basic_idtlb1_nohw isa3_basic_idtlb1.s -midas_args=-DNOHWTW //isa3_basic_idtlb4_nohw isa3_basic_idtlb4.s -midas_args=-DNOHWTW //isa3_basic_idtlb1 isa3_basic_idtlb1.s //isa3_basic_idtlb4 isa3_basic_idtlb4.s //isa3_basic_idtlb4_4u isa3_basic_idtlb4.s -midas_args=-ttefmt=sun4u //isa3_basic_idtlb4_nohw_4u isa3_basic_idtlb4.s -midas_args=-DNOHWTW -midas_args=-ttefmt=sun4u //isa3_spu_ma_gf2m_modadd isa3_spu_ma_gf2m_modadd.s //isa3_spu_ma_modred isa3_spu_ma_modred.s //isa3_spu_ma_modmul isa3_spu_ma_modmul.s //isa3_spu_cwq_tcp isa3_spu_cwq_tcp.s // -tg_seed=1