// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pm_mcu.diaglist
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
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// ========== Copyright Header End ============================================
<sys(mcu_pm) name=sys(mcu_pm)>
<sys(pm_all)>

<sys(pm_mcu)>

<runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+TIMEOUT=10000 -vcs_run_args=+8_FBDIMMS -midas_args=-DSYNC_THREADS -vcs_run_args=+mon+mcu_fmon=1=1 -vcs_run_args=+debug -vcs_run_args=+gchkr_off>


//Core0_2bank
<runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=1 -midas_args=-DCMP_THREAD_START=0x01 -finish_mask=01 -vcs_run_args=+STACK_DIMM>
n2_pm_mcu_cmda_Core0_2Bank	n2_pm_mcu_cmda_2bank.s
</runargs>

<runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=1 -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff >
<runargs -midas_args=-DL2_DIRECT_MAP>

n2_pm_mcu_all_th_wr_Core0_2bank_Bank0	  n2_pm_mcu_all_th_wr.s             -midas_args=-DBANK0 
n2_pm_mcu_all_th_rd_Core0_2bank_Bank0     n2_pm_mcu_all_th_rd.s             -midas_args=-DBANK0	
n2_pm_mcu_all_th_wrrd_Core0_2bank_Bank0   n2_pm_mcu_all_th_wrrd.s           -midas_args=-DBANK0
n2_pm_mcu_diff_th_wr_rd_Core0_2bank_Bank0 n2_pm_mcu_diff_th_wr_rd.s         -midas_args=-DBANK0

n2_pm_mcu_all_th_wr_Core0_2bank_Bank1     n2_pm_mcu_all_th_wr.s             -midas_args=-DBANK1
n2_pm_mcu_all_th_rd_Core0_2bank_Bank1     n2_pm_mcu_all_th_rd.s             -midas_args=-DBANK1
n2_pm_mcu_all_th_wrrd_Core0_2bank_Bank1   n2_pm_mcu_all_th_wrrd.s           -midas_args=-DBANK1
n2_pm_mcu_diff_th_wr_rd_Core0_2bank_Bank1 n2_pm_mcu_diff_th_wr_rd.s         -midas_args=-DBANK1

n2_pm_all_dimm_Core0_2bank_B0       n2_pm_all_dimm.s -midas_args=-DPM_2BANK   -midas_args=-DBANK0
n2_pm_all_dimm_Core0_2bank_B1       n2_pm_all_dimm.s -midas_args=-DPM_2BANK   -midas_args=-DBANK1

n2_pm_all_dimm_rdwr_Core0_2bank_B0  n2_pm_all_dimm_rdwr.s -midas_args=-DPM_2BANK   -midas_args=-DBANK0
n2_pm_all_dimm_rdwr_Core0_2bank_B1  n2_pm_all_dimm_rdwr.s -midas_args=-DPM_2BANK   -midas_args=-DBANK1

n2_pm_all_dimm_rdwr_2_Core0_2bank_B0  n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_2BANK   -midas_args=-DBANK0
n2_pm_all_dimm_rdwr_2_Core0_2bank_B1  n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_2BANK   -midas_args=-DBANK1

n2_pm_all_dimm_rdwr_3_Core0_2bank  n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_2BANK 
n2_pm_all_dimm_rdwr_4_Core0_2bank  n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_2BANK

n2_pm_all_dimm_rdwr_5_Core0_2bank  n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_2BANK
n2_pm_all_dimm_rdwr_6_Core0_2bank  n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_2BANK
			
// fails DBU; n2_mcu_0_all_bcopy_all_banks_Core0_2bank n2_mcu_0_all_bcopy_all_banks.s  
</runargs>

n2_pm_all_dimm_rdwr_3_Core0_2bank_way  n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_2BANK
n2_pm_all_dimm_rdwr_4_Core0_2bank_way  n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_2BANK

n2_pm_all_dimm_rdwr_5_Core0_2bank_way  n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_2BANK      
n2_pm_all_dimm_rdwr_6_Core0_2bank_way  n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_2BANK      
</runargs>


//Core0_4bank
<runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=3 -midas_args=-DCMP_THREAD_START=0x01 -finish_mask=01 -vcs_run_args=+STACK_DIMM>
n2_pm_mcu_cmda_Core0_4Bank	n2_pm_mcu_cmda_4bank.s
</runargs>

<runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=3 -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff >
<runargs -midas_args=-DL2_DIRECT_MAP>
n2_pm_mcu_all_th_wr_Core0_4bank_Bank0     n2_pm_mcu_all_th_wr.s             -midas_args=-DBANK0
n2_pm_mcu_all_th_rd_Core0_4bank_Bank0     n2_pm_mcu_all_th_rd.s             -midas_args=-DBANK0
n2_pm_mcu_all_th_wrrd_Core0_4bank_Bank0   n2_pm_mcu_all_th_wrrd.s           -midas_args=-DBANK0
n2_pm_mcu_diff_th_wr_rd_Core0_4bank_Bank0 n2_pm_mcu_diff_th_wr_rd.s         -midas_args=-DBANK0

n2_pm_mcu_all_th_wr_Core0_4bank_Bank1     n2_pm_mcu_all_th_wr.s             -midas_args=-DBANK1
n2_pm_mcu_all_th_rd_Core0_4bank_Bank1     n2_pm_mcu_all_th_rd.s             -midas_args=-DBANK1
n2_pm_mcu_all_th_wrrd_Core0_4bank_Bank1   n2_pm_mcu_all_th_wrrd.s           -midas_args=-DBANK1
n2_pm_mcu_diff_th_wr_rd_Core0_4bank_Bank1 n2_pm_mcu_diff_th_wr_rd.s         -midas_args=-DBANK1

n2_pm_all_dimm_Core0_4bank_B0       n2_pm_all_dimm.s -midas_args=-DPM_4BANK   -midas_args=-DBANK0
n2_pm_all_dimm_Core0_4bank_B1       n2_pm_all_dimm.s -midas_args=-DPM_4BANK   -midas_args=-DBANK1

n2_pm_all_dimm_rdwr_Core0_4bank_B0  n2_pm_all_dimm_rdwr.s -midas_args=-DPM_4BANK   -midas_args=-DBANK0
n2_pm_all_dimm_rdwr_Core0_4bank_B1  n2_pm_all_dimm_rdwr.s -midas_args=-DPM_4BANK   -midas_args=-DBANK1

n2_pm_all_dimm_rdwr_2_Core0_4bank_B0  n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_4BANK   -midas_args=-DBANK0
n2_pm_all_dimm_rdwr_2_Core0_4bank_B1  n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_4BANK   -midas_args=-DBANK1

n2_pm_all_dimm_rdwr_5_Core0_4bank  n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_4BANK
n2_pm_all_dimm_rdwr_6_Core0_4bank  n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_4BANK

n2_mcu_0_all_bcopy_all_banks_Core0_4bank n2_mcu_0_all_bcopy_all_banks.s  
</runargs>

n2_pm_all_dimm_rdwr_3_Core0_4bank_way  n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_4BANK
n2_pm_all_dimm_rdwr_4_Core0_4bank_way  n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_4BANK

n2_pm_all_dimm_rdwr_5_Core0_4bank_way  n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_4BANK
n2_pm_all_dimm_rdwr_6_Core0_4bank_way  n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_4BANK
</runargs>

//Core1_2bank
<runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=1 -midas_args=-DCMP_THREAD_START=0x0100 -finish_mask=0100 -vcs_run_args=+STACK_DIMM>
n2_pm_mcu_cmda_Core1_2Bank	n2_pm_mcu_cmda_2bank.s
</runargs>

<runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=1 -midas_args=-DCMP_THREAD_START=0xff00 -finish_mask=ff00 >
<runargs -midas_args=-DL2_DIRECT_MAP>
n2_pm_mcu_all_th_wr_Core1_2bank_Bank0     n2_pm_mcu_all_th_wr.s             -midas_args=-DBANK0
n2_pm_mcu_all_th_rd_Core1_2bank_Bank0     n2_pm_mcu_all_th_rd.s             -midas_args=-DBANK0
n2_pm_mcu_all_th_wrrd_Core1_2bank_Bank0   n2_pm_mcu_all_th_wrrd.s           -midas_args=-DBANK0
n2_pm_mcu_diff_th_wr_rd_Core1_2bank_Bank0 n2_pm_mcu_diff_th_wr_rd.s         -midas_args=-DBANK0

n2_pm_mcu_all_th_wr_Core1_2bank_Bank1     n2_pm_mcu_all_th_wr.s             -midas_args=-DBANK1
n2_pm_mcu_all_th_rd_Core1_2bank_Bank1     n2_pm_mcu_all_th_rd.s             -midas_args=-DBANK1
n2_pm_mcu_all_th_wrrd_Core1_2bank_Bank1   n2_pm_mcu_all_th_wrrd.s           -midas_args=-DBANK1
n2_pm_mcu_diff_th_wr_rd_Core1_2bank_Bank1 n2_pm_mcu_diff_th_wr_rd.s         -midas_args=-DBANK1

n2_pm_all_dimm_Core1_2bank_B0	    n2_pm_all_dimm.s -midas_args=-DPM_2BANK   -midas_args=-DBANK0
n2_pm_all_dimm_Core1_2bank_B1	    n2_pm_all_dimm.s -midas_args=-DPM_2BANK   -midas_args=-DBANK1

n2_pm_all_dimm_rdwr_Core1_2bank_B0  n2_pm_all_dimm_rdwr.s -midas_args=-DPM_2BANK   -midas_args=-DBANK0
n2_pm_all_dimm_rdwr_Core1_2bank_B1  n2_pm_all_dimm_rdwr.s -midas_args=-DPM_2BANK   -midas_args=-DBANK1

n2_pm_all_dimm_rdwr_2_Core1_2bank_B0  n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_2BANK   -midas_args=-DBANK0
n2_pm_all_dimm_rdwr_2_Core1_2bank_B1  n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_2BANK   -midas_args=-DBANK1

n2_pm_all_dimm_rdwr_3_Core1_2bank  n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_2BANK 
n2_pm_all_dimm_rdwr_4_Core1_2bank  n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_2BANK

n2_pm_all_dimm_rdwr_5_Core1_2bank  n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_2BANK
n2_pm_all_dimm_rdwr_6_Core1_2bank  n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_2BANK

// fails DBU; n2_mcu_0_all_bcopy_all_banks_Core1_2bank n2_mcu_0_all_bcopy_all_banks.s
</runargs>

n2_pm_all_dimm_rdwr_3_Core1_2bank_way  n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_2BANK
n2_pm_all_dimm_rdwr_4_Core1_2bank_way  n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_2BANK

n2_pm_all_dimm_rdwr_5_Core1_2bank_way  n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_2BANK
n2_pm_all_dimm_rdwr_6_Core1_2bank_way  n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_2BANK
</runargs>

//Core1_4bank
<runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=3 -midas_args=-DCMP_THREAD_START=0x0100 -finish_mask=0100  -vcs_run_args=+STACK_DIMM>
n2_pm_mcu_cmda_Core1_4Bank	n2_pm_mcu_cmda_4bank.s
</runargs>

<runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=3 -midas_args=-DCMP_THREAD_START=0xff00 -finish_mask=ff00 >
<runargs -midas_args=-DL2_DIRECT_MAP>
n2_pm_mcu_all_th_wr_Core1_4bank_Bank0     n2_pm_mcu_all_th_wr.s             -midas_args=-DBANK0
n2_pm_mcu_all_th_rd_Core1_4bank_Bank0     n2_pm_mcu_all_th_rd.s             -midas_args=-DBANK0
n2_pm_mcu_all_th_wrrd_Core1_4bank_Bank0   n2_pm_mcu_all_th_wrrd.s           -midas_args=-DBANK0
n2_pm_mcu_diff_th_wr_rd_Core1_4bank_Bank0 n2_pm_mcu_diff_th_wr_rd.s         -midas_args=-DBANK0

n2_pm_mcu_all_th_wr_Core1_4bank_Bank1     n2_pm_mcu_all_th_wr.s             -midas_args=-DBANK1
n2_pm_mcu_all_th_rd_Core1_4bank_Bank1     n2_pm_mcu_all_th_rd.s             -midas_args=-DBANK1
n2_pm_mcu_all_th_wrrd_Core1_4bank_Bank1   n2_pm_mcu_all_th_wrrd.s           -midas_args=-DBANK1
n2_pm_mcu_diff_th_wr_rd_Core1_4bank_Bank1 n2_pm_mcu_diff_th_wr_rd.s         -midas_args=-DBANK1

n2_pm_all_dimm_Core1_4bank_B0       n2_pm_all_dimm.s -midas_args=-DPM_4BANK   -midas_args=-DBANK0
n2_pm_all_dimm_Core1_4bank_B1       n2_pm_all_dimm.s -midas_args=-DPM_4BANK   -midas_args=-DBANK1               

n2_pm_all_dimm_rdwr_Core1_4bank_B0  n2_pm_all_dimm_rdwr.s -midas_args=-DPM_4BANK   -midas_args=-DBANK0
n2_pm_all_dimm_rdwr_Core1_4bank_B1  n2_pm_all_dimm_rdwr.s -midas_args=-DPM_4BANK   -midas_args=-DBANK1

n2_pm_all_dimm_rdwr_2_Core1_4bank_B0  n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_4BANK   -midas_args=-DBANK0
n2_pm_all_dimm_rdwr_2_Core1_4bank_B1  n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_4BANK   -midas_args=-DBANK1

n2_pm_all_dimm_rdwr_3_Core1_4bank  n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_4BANK
n2_pm_all_dimm_rdwr_4_Core1_4bank  n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_4BANK

n2_pm_all_dimm_rdwr_5_Core1_4bank  n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_4BANK
n2_pm_all_dimm_rdwr_6_Core1_4bank  n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_4BANK

n2_mcu_0_all_bcopy_all_banks_Core1_4bank n2_mcu_0_all_bcopy_all_banks.s
</runargs>

n2_pm_all_dimm_rdwr_3_Core1_4bank_way  n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_4BANK
n2_pm_all_dimm_rdwr_4_Core1_4bank_way  n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_4BANK

n2_pm_all_dimm_rdwr_5_Core1_4bank_way  n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_4BANK
n2_pm_all_dimm_rdwr_6_Core1_4bank_way  n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_4BANK
</runargs>

//Core1_8bank
<runargs -vcs_run_args=+core_set_mask=02 -midas_args=-DCMP_THREAD_START=0x0100 -finish_mask=0100 -vcs_run_args=+STACK_DIMM>
n2_pm_mcu_cmda_Core1_8Bank	n2_pm_mcu_cmda_8bank.s
</runargs>

<runargs -vcs_run_args=+core_set_mask=02 -midas_args=-DCMP_THREAD_START=0xff00 -finish_mask=ff00 -midas_args=-DL2_DIRECT_MAP>
<runargs -midas_args=-DL2_DIRECT_MAP>
n2_pm_mcu_all_th_wr_Core1_8bank_Bank0     n2_pm_mcu_all_th_wr.s             -midas_args=-DBANK0
n2_pm_mcu_all_th_rd_Core1_8bank_Bank0     n2_pm_mcu_all_th_rd.s             -midas_args=-DBANK0
n2_pm_mcu_all_th_wrrd_Core1_8bank_Bank0   n2_pm_mcu_all_th_wrrd.s           -midas_args=-DBANK0
n2_pm_mcu_diff_th_wr_rd_Core1_8bank_Bank0 n2_pm_mcu_diff_th_wr_rd.s         -midas_args=-DBANK0


n2_pm_mcu_all_th_wr_Core1_8bank_Bank1     n2_pm_mcu_all_th_wr.s             -midas_args=-DBANK1
n2_pm_mcu_all_th_rd_Core1_8bank_Bank1     n2_pm_mcu_all_th_rd.s             -midas_args=-DBANK1
n2_pm_mcu_all_th_wrrd_Core1_8bank_Bank1   n2_pm_mcu_all_th_wrrd.s           -midas_args=-DBANK1
n2_pm_mcu_diff_th_wr_rd_Core1_8bank_Bank1 n2_pm_mcu_diff_th_wr_rd.s         -midas_args=-DBANK1

n2_pm_all_dimm_Core1_8bank_B0       n2_pm_all_dimm.s -midas_args=-DPM_8BANK   -midas_args=-DBANK0
n2_pm_all_dimm_Core1_8bank_B1       n2_pm_all_dimm.s -midas_args=-DPM_8BANK   -midas_args=-DBANK1               

n2_pm_all_dimm_rdwr_Core1_8bank_B0  n2_pm_all_dimm_rdwr.s -midas_args=-DPM_8BANK   -midas_args=-DBANK0
n2_pm_all_dimm_rdwr_Core1_8bank_B1  n2_pm_all_dimm_rdwr.s -midas_args=-DPM_8BANK   -midas_args=-DBANK1

n2_pm_all_dimm_rdwr_2_Core1_8bank_B0  n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_8BANK   -midas_args=-DBANK0
n2_pm_all_dimm_rdwr_2_Core1_8bank_B1  n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_8BANK   -midas_args=-DBANK1

n2_pm_all_dimm_rdwr_3_Core1_8bank  n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_8BANK
n2_pm_all_dimm_rdwr_4_Core1_8bank  n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_8BANK

n2_pm_all_dimm_rdwr_5_Core1_8bank  n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_8BANK
n2_pm_all_dimm_rdwr_6_Core1_8bank  n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_8BANK


n2_mcu_0_all_bcopy_all_banks_Core1_8bank n2_mcu_0_all_bcopy_all_banks.s
</runargs>

n2_pm_all_dimm_rdwr_3_Core1_8bank_way  n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_8BANK
n2_pm_all_dimm_rdwr_4_Core1_8bank_way  n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_8BANK

n2_pm_all_dimm_rdwr_5_Core1_8bank_way  n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_8BANK
n2_pm_all_dimm_rdwr_6_Core1_8bank_way  n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_8BANK
</runargs>

//Core1257_4bank
<runargs -vcs_run_args=+core_set_mask=a6 -midas_args=-DCMP_THREAD_START=0x0100010000010100 -finish_mask=0100010000010100 -vcs_run_args=+STACK_DIMM>
n2_pm_mcu_cmda_Core1257_4Bank	n2_pm_mcu_cmda_4bank.s
</runargs>

<runargs -vcs_run_args=+core_set_mask=a6 -vcs_run_args=+bank_set_mask=3 -midas_args=-DCMP_THREAD_START=0xff00ff0000ffff00 -finish_mask=ff00ff0000ffff00 >
<runargs -midas_args=-DL2_DIRECT_MAP>
n2_pm_mcu_all_th_wr_Core1257_4bank_Bank0     n2_pm_mcu_all_th_wr.s         -midas_args=-DBANK0
n2_pm_mcu_all_th_rd_Core1257_4bank_Bank0     n2_pm_mcu_all_th_rd.s         -midas_args=-DBANK0
n2_pm_mcu_all_th_wrrd_Core1257_4bank_Bank0   n2_pm_mcu_all_th_wrrd.s       -midas_args=-DBANK0
n2_pm_mcu_diff_th_wr_rd_Core1257_4bank_Bank0 n2_pm_mcu_diff_th_wr_rd.s     -midas_args=-DBANK0

n2_pm_mcu_all_th_wr_Core1257_4bank_Bank1     n2_pm_mcu_all_th_wr.s         -midas_args=-DBANK1
n2_pm_mcu_all_th_rd_Core1257_4bank_Bank1     n2_pm_mcu_all_th_rd.s         -midas_args=-DBANK1
n2_pm_mcu_all_th_wrrd_Core1257_4bank_Bank1   n2_pm_mcu_all_th_wrrd.s       -midas_args=-DBANK1
n2_pm_mcu_diff_th_wr_rd_Core1257_4bank_Bank1 n2_pm_mcu_diff_th_wr_rd.s     -midas_args=-DBANK1

n2_pm_all_dimm_Core1257_4bank_B0       n2_pm_all_dimm.s -midas_args=-DPM_4BANK   -midas_args=-DBANK0
n2_pm_all_dimm_Core1257_4bank_B1       n2_pm_all_dimm.s -midas_args=-DPM_4BANK   -midas_args=-DBANK1               

n2_pm_all_dimm_rdwr_Core1257_4bank_B0  n2_pm_all_dimm_rdwr.s -midas_args=-DPM_4BANK   -midas_args=-DBANK0
n2_pm_all_dimm_rdwr_Core1257_4bank_B1  n2_pm_all_dimm_rdwr.s -midas_args=-DPM_4BANK   -midas_args=-DBANK1

n2_pm_all_dimm_rdwr_2_Core1257_4bank_B0  n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_4BANK   -midas_args=-DBANK0
n2_pm_all_dimm_rdwr_2_Core1257_4bank_B1  n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_4BANK   -midas_args=-DBANK1

n2_pm_all_dimm_rdwr_3_Core1257_4bank	 n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_4BANK
n2_pm_all_dimm_rdwr_4_Core1257_4bank     n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_4BANK

n2_pm_all_dimm_rdwr_5_Core1257_4bank     n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_4BANK
n2_pm_all_dimm_rdwr_6_Core1257_4bank     n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_4BANK

// long running n2_mcu_0_all_bcopy_all_banks_Core1257_4bank n2_mcu_0_all_bcopy_all_banks.s
</runargs>

n2_pm_all_dimm_rdwr_3_Core1257_4bank_way     n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_4BANK
n2_pm_all_dimm_rdwr_4_Core1257_4bank_way     n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_4BANK

n2_pm_all_dimm_rdwr_5_Core1257_4bank_way     n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_4BANK
n2_pm_all_dimm_rdwr_6_Core1257_4bank_way     n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_4BANK
</runargs>



</runargs>

</sys(pm_mcu)>


</sys(pm_all)>
</sys(mcu_pm)>