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// 
// OpenSPARC T2 Processor File: defines.vri
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// ========== Copyright Header End ============================================
#include <vera_defines.vrh>

///////////////////////////////////////////////////////////////
// Vera defines used in this testbench
///////////////////////////////////////////////////////////////

#define STD_DISP gDbg

// Defines for bit positions for sim_status
#define ASM_PASS 0
#define ASM_ERR  1

// #define OUTPUT_SKEW  #10 if PHOLD
// #define INPUT_SKEW   #-10
#define OUTPUT_SKEW  #0
#define INPUT_SKEW   #-0
#define OUTPUT_EDGE  NHOLD
#define INPUT_EDGE   NSAMPLE
#define BOTH_DIR     NSAMPLE NHOLD

//#define IDLE_DATA {urandom(),urandom(),urandom(),urandom()}
// #define IDLE_DATA 128'hDEAD_BEEF_DEAD_BEEF_DEAD_BEEF_DEAD_BEEF

#define PP_CPX 0
#define PP_PCX 1
#define PP_MEM 2
#define PP_SPC 3
#define PP_TRG 4
// 
// #define READ 0
// #define WRITE 1
// 
// #define PASSIVE 1
// #define ACTIVE  0
// 
// // ccx devices
// #define DEV_SPC0 0
// #define DEV_SPC1 1
// #define DEV_SPC2 2
// #define DEV_SPC3 3
// #define DEV_SPC4 4
// #define DEV_SPC5 5
// #define DEV_SPC6 6
// #define DEV_SPC7 7
// #define DEV_MEM0 8
// #define DEV_MEM1 9
// #define DEV_MEM2 10
// #define DEV_MEM3 11
// #define DEV_MEM4 12
// #define DEV_MEM5 13
// #define DEV_MEM6 14
// #define DEV_MEM7 15
// 
// #define DEV_MEM8 16
// #define DEV_NCU  16

// "same cache line address". is it PA[38:6] or PA[17:6] ?
// [8:6] is bank number.
// [38:6] marks choice
// #define CACHE_LINE_MASK 64'h0000007fffffffc0
// [17:6] my choice
// #define CACHE_LINE_MASK 64'h000000000003ffc0
// [17:9]
// #define CACHE_LINE_MASK 64'h000000000003fe00
// [17:4]
// #define CACHE_LINE_MASK 64'h000000000003fff0
// [38:9]
// #define CACHE_LINE_MASK 64'h0000007ffffffe00


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