// ========== Copyright Header Begin ========================================== // // OpenSPARC T2 Processor File: dmu_cmu_sample.vrhpal // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved // 4150 Network Circle, Santa Clara, California 95054, U.S.A. // // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; version 2 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // // For the avoidance of doubt, and except that if any non-GPL license // choice is available it will apply instead, Sun elects to use only // the General Public License version 2 (GPLv2) at this time for any // software where a choice of GPL license versions is made // available with the language indicating that GPLv2 or any later version // may be used, or where a choice of which version of the GPL is applied is // otherwise unspecified. // // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, // CA 95054 USA or visit www.sun.com if you need additional information or // have any questions. // // ========== Copyright Header End ============================================ #inc "dmu_cov_inc.pal"; sample cov_dmu_cmu_Type (dmu_cmu_Type) { state CMU_Ingress_DMA_MRd32 ( 7'b0000000); state CMU_Ingress_DMA_MRd64 ( 7'b0100000); state CMU_Ingress_DMA_MRdLk32 ( 7'b0000001); state CMU_Ingress_DMA_MRdLk64 ( 7'b0100001); state CMU_Ingress_Unsupported ( 7'b0001001); state CMU_Ingress_DMA_MWr32 ( 7'b1000000); state CMU_Ingress_DMA_MWr64 ( 7'b1100000); state CMU_Ingress_MSI_MWr32 ( 7'b1011000); state CMU_Ingress_MSI_MWr64 ( 7'b1111000); state CMU_Ingress_MSG_MWr32 ( 7'b1010000); state CMU_Ingress_MSG_MWr64 ( 7'b1110000); state CMU_Ingress_NULL ( 7'b1111100); state CMU_Ingress_MONDO ( 7'b1111010); state CMU_Ingress_PIO_Cpl ( 7'b0001010); state CMU_Ingress_PIO_CplD ( 7'b1001010); } sample cov_dmu_cmu_len (dmu_cmu_Len) { . &toggle(10 ); cov_weight = 1; } sample cov_dmu_cmu_byte (dmu_cmu_Byte) { . &toggle(12 ); cov_weight = 1; } sample cov_dmu_cmu_cntxt (dmu_cmu_Cntxt) { . &toggle(5 ); cov_weight = 1; } sample cov_dmu_cmu_pkseq (dmu_cmu_Pkseq) { . &toggle(5 ); cov_weight = 1; } // N2 does not toggle upper 4 bits of PA sample cov_dmu_cmu_addr (dmu_cmu_Addr[36:0]) { . &toggle(37 ); cov_weight = 1; } sample cov_dmu_cmu_addr_err (dmu_cmu_Addr_err) { . &toggle(1 ); cov_weight = 1; }