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// 
// OpenSPARC T2 Processor File: ilu_peu_fcsm_state_sample.vrh
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#define   IDLE                  4'h0
#define   FC1_P                 4'h1
#define   FC1_NP                4'h2
#define   FC1_CPL               4'h3
#define   FC2_P                 4'h4
#define   FC2_NP                4'h5
#define   FC2_CPL               4'h6


sample ilu_peu_coverage_fcsm_state_coverage_group.fc_state 

{
        state s_IDLE                (IDLE);
        state s_FC1_P               (FC1_P);
        state s_FC1_NP              (FC1_NP);
        state s_FC1_CPL             (FC1_CPL);
        state s_FC2_P               (FC2_P);
        state s_FC2_NP              (FC2_NP);
        state s_FC2_CPL             (FC2_CPL);

        trans    t_IDLE_FC1_P_01         (IDLE      ->  FC1_P);
        trans    t_FC1_P_FC1_NP_02       (FC1_P     ->  FC1_NP);
//        trans    t_FC1_P_FC1_P_03        (FC1_P     ->  FC1_P);
        trans    t_FC1_NP_FC1_CPL_04     (FC1_NP    ->  FC1_CPL);
//        trans    t_FC1_NP_FC1_NP_05      (FC1_NP    ->  FC1_NP);
        trans    t_FC1_CPL_FC2_P_06      (FC1_CPL   ->  FC2_P);
        trans    t_FC1_CPL_FC1_P_07      (FC1_CPL   ->  FC1_P);
//        trans    t_FC1_CPL_FC2_CPL_08    (FC1_CPL   ->  FC2_CPL);
        trans    t_FC2_P_FC2_NP_09       (FC2_P     ->  FC2_NP);
//        trans    t_FC2_P_FC2_P_10        (FC2_P     ->  FC2_P);
        trans    t_FC2_NP_FC2_CPL_11     (FC2_NP    ->  FC2_CPL);
//        trans    t_FC2_NP_FC2_NP_12      (FC2_NP    ->  FC2_NP);
        trans    t_FC2_CPL_IDLE_13       (FC2_CPL   ->  IDLE);
        trans    t_FC2_CPL_FC2_P_14      (FC2_CPL   ->  FC2_P);
//        trans    t_FC2_CPL_FC2_CPL_15    (FC2_CPL   ->  FC2_CPL);

}