// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: l2_cpx_fields_sample.vrhpal
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
wildcard state LOAD_miss_1  ( {1'b1, LOAD_RET, 1'b1, 2'bxx, 1'bx, 3'bx, 1'bx, 3'bxxx, 2'b00, 5'bx} );
wildcard state LOAD_ce      ( {1'b1, LOAD_RET, 1'bx, 2'bx1, 1'bx, 3'bx, 1'bx, 3'bxxx, 2'b00, 5'bx} );
wildcard state LOAD_ue      ( {1'b1, LOAD_RET, 1'bx, 2'b1x, 1'bx, 3'bx, 1'bx, 3'bxxx, 2'b00, 5'bx} );
wildcard state LOAD_invway_0( {1'b1, LOAD_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 1'bx, 3'b000, 2'b00, 5'bx} );
wildcard state LOAD_invway_1( {1'b1, LOAD_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 1'bx, 3'b001, 2'b00, 5'bx} );
wildcard state LOAD_invway_2( {1'b1, LOAD_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 1'bx, 3'b010, 2'b00, 5'bx} );
wildcard state LOAD_invway_3( {1'b1, LOAD_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 1'bx, 3'b011, 2'b00, 5'bx} );
wildcard state LOAD_invway_4( {1'b1, LOAD_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 1'bx, 3'b100, 2'b00, 5'bx} ); 
wildcard state LOAD_invway_5( {1'b1, LOAD_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 1'bx, 3'b101, 2'b00, 5'bx} );
wildcard state LOAD_invway_6( {1'b1, LOAD_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 1'bx, 3'b110, 2'b00, 5'bx} );
wildcard state LOAD_invway_7( {1'b1, LOAD_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 1'bx, 3'b111, 2'b00, 5'bx} );
wildcard state LOAD_wv_0    ( {1'b1, LOAD_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 1'b0, 3'bxxx, 2'b00, 5'bx} );
wildcard state LOAD_wv_1    ( {1'b1, LOAD_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 1'b1, 3'bxxx, 2'b00, 5'bx} );

// PREFETCH_RET                    vld   reqtype   miss  err    nc    thr   invway  f4b   at pf  data[127:123]
wildcard state PREFETCH_miss_0  ( {1'b1, LOAD_RET, 1'b0, 2'bxx, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'b01, 5'bx} );
wildcard state PREFETCH_miss_1  ( {1'b1, LOAD_RET, 1'b1, 2'bxx, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'b01, 5'bx} );
wildcard state PREFETCH_ce      ( {1'b1, LOAD_RET, 1'bx, 2'bx1, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'b01, 5'bx} );
wildcard state PREFETCH_ue      ( {1'b1, LOAD_RET, 1'bx, 2'b1x, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'b01, 5'bx} );
wildcard state PREFETCH_invway_0( {1'b1, LOAD_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 3'b000, 1'bx, 2'b01, 5'bx} );
wildcard state PREFETCH_invway_1( {1'b1, LOAD_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 3'b000, 1'bx, 2'b01, 5'bx} );
wildcard state PREFETCH_invway_2( {1'b1, LOAD_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 3'b000, 1'bx, 2'b01, 5'bx} );
wildcard state PREFETCH_invway_3( {1'b1, LOAD_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 3'b000, 1'bx, 2'b01, 5'bx} );

// IFILL_RET                    vld   reqtype    miss  err    nc    thr   invway  f4b   at pf  data[127:123]
wildcard state IFILL_miss_0  ( {1'b1, IFILL_RET, 1'b0, 2'bxx, 1'bx, 3'bx, 3'bxxx, 1'b0, 2'bx0, 5'bx} );
wildcard state IFILL_miss_1  ( {1'b1, IFILL_RET, 1'b1, 2'bxx, 1'bx, 3'bx, 3'bxxx, 1'b0, 2'bx0, 5'bx} );
wildcard state IFILL_ce      ( {1'b1, IFILL_RET, 1'bx, 2'bx1, 1'bx, 3'bx, 3'bxxx, 1'b0, 2'bx0, 5'bx} );
wildcard state IFILL_ue      ( {1'b1, IFILL_RET, 1'bx, 2'b1x, 1'bx, 3'bx, 3'bxxx, 1'b0, 2'bx0, 5'bx} );
wildcard state IFILL_invway_0( {1'b1, IFILL_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 3'bx00, 1'b0, 2'bx0, 5'bx} );
wildcard state IFILL_invway_1( {1'b1, IFILL_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 3'bx01, 1'b0, 2'bx0, 5'bx} );
wildcard state IFILL_invway_2( {1'b1, IFILL_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 3'bx10, 1'b0, 2'bx0, 5'bx} );
wildcard state IFILL_invway_3( {1'b1, IFILL_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 3'bx11, 1'b0, 2'bx0, 5'bx} );
wildcard state IFILL_wv_0    ( {1'b1, IFILL_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 3'b0xx, 1'b0, 2'bx0, 5'bx} );
wildcard state IFILL_wv_1    ( {1'b1, IFILL_RET, 1'bx, 2'bxx, 1'bx, 3'bx, 3'b1xx, 1'b0, 2'bx0, 5'bx} );

// ST_ACK                     vld   reqtype miss  err    nc    thr   invway  f4b   at pf  data[127:123]
wildcard state STORE_miss_0( {1'b1, ST_ACK, 1'b0, 2'bxx, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'b00, 5'b0} );
wildcard state STORE_miss_1( {1'b1, ST_ACK, 1'b1, 2'bxx, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'b00, 5'b0} );

// BLKSTORE_ACK/BLKINITST_ACK     vld   reqtype miss  err    nc    thr   invway  f4b   at pf  data[127:123]
wildcard state BLKINITST_miss_0( {1'b1, ST_ACK, 1'b0, 2'bxx, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'b00, 5'b00100} );
wildcard state BLKINITST_miss_1( {1'b1, ST_ACK, 1'b1, 2'bxx, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'b00, 5'b00100} );

// CAS_RET/SWAP_RET          vld   reqtype   miss  err    nc    thr   invway  f4b   at pf  data[127:123]
wildcard state CAS_SWAP_ce( {1'b1, LOAD_RET, 1'bx, 2'bx1, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'b10, 5'bx} );
wildcard state CAS_SWAP_ue( {1'b1, LOAD_RET, 1'bx, 2'b1x, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'b10, 5'bx} );

// STRLOAD_RET                  vld   reqtype      miss  err    nc    thr   invway  f4b   at pf  data[127:123]
wildcard state STRLOAD_miss_0( {1'b1, STRLOAD_RET, 1'b0, 2'bxx, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'bx0, 5'bx} );
wildcard state STRLOAD_miss_1( {1'b1, STRLOAD_RET, 1'b1, 2'bxx, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'bx0, 5'bx} );
wildcard state STRLOAD_ce    ( {1'b1, STRLOAD_RET, 1'bx, 2'bx1, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'bx0, 5'bx} );
wildcard state STRLOAD_ue    ( {1'b1, STRLOAD_RET, 1'bx, 2'b1x, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'bx0, 5'bx} );

// FWDRQ_LOAD_RET                  vld   reqtype      miss  err    nc    thr   invway  f4b   at pf  data[127:123]
/*wildcard state FWDRQ_LOAD_miss_0( {1'b1, FWD_RPY_RET, 1'b0, 2'bxx, 1'b1, 3'bx, 3'bxxx, 1'bx, 2'bx0, 5'bx} );
wildcard state FWDRQ_LOAD_miss_1( {1'b1, FWD_RPY_RET, 1'b1, 2'bxx, 1'b1, 3'bx, 3'bxxx, 1'bx, 2'bx0, 5'bx} );
wildcard state FWDRQ_LOAD_ce    ( {1'b1, FWD_RPY_RET, 1'bx, 2'bx1, 1'b1, 3'bx, 3'bxxx, 1'bx, 2'bx0, 5'bx} );
wildcard state FWDRQ_LOAD_ue    ( {1'b1, FWD_RPY_RET, 1'bx, 2'b1x, 1'b1, 3'bx, 3'bxxx, 1'bx, 2'bx0, 5'bx} );
*/
// FWDRQ_STORE_ACK                  vld   reqtype      miss  err    nc    thr   invway  f4b   at pf  data[127:123]
/*wildcard state FWDRQ_STORE_miss_0( {1'b1, FWD_RPY_RET, 1'b0, 2'bxx, 1'b0, 3'bx, 3'bxxx, 1'bx, 2'bx0, 5'b0} );
wildcard state FWDRQ_STORE_miss_1( {1'b1, FWD_RPY_RET, 1'b1, 2'bxx, 1'b0, 3'bx, 3'bxxx, 1'bx, 2'bx0, 5'b0} );
*/
// ERR_RET                     vld   reqtype  miss  err    nc    thr   invway  f4b   at pf data[127:123]
wildcard state ERR_RET_ce   ( {1'b1, ERR_RET, 1'bx, 2'bx1, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'bx, 5'bx} );
wildcard state ERR_RET_ue   ( {1'b1, ERR_RET, 1'bx, 2'b1x, 1'bx, 3'bx, 3'bxxx, 1'bx, 2'bx, 5'bx} );
wildcard state ERR_RET_tid_0( {1'b1, ERR_RET, 1'bx, 2'bxx, 1'bx, 3'h0, 3'bxxx, 1'bx, 2'bx, 5'bx} );
wildcard state ERR_RET_tid_1( {1'b1, ERR_RET, 1'bx, 2'bxx, 1'bx, 3'h1, 3'bxxx, 1'bx, 2'bx, 5'bx} );
wildcard state ERR_RET_tid_2( {1'b1, ERR_RET, 1'bx, 2'bxx, 1'bx, 3'h2, 3'bxxx, 1'bx, 2'bx, 5'bx} );
wildcard state ERR_RET_tid_3( {1'b1, ERR_RET, 1'bx, 2'bxx, 1'bx, 3'h3, 3'bxxx, 1'bx, 2'bx, 5'bx} );

//review add new cpx packet types