// ========== Copyright Header Begin ========================================== // // OpenSPARC T2 Processor File: l2_fb_bypass_insts_sample.vrhpal // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved // 4150 Network Circle, Santa Clara, California 95054, U.S.A. // // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; version 2 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // // For the avoidance of doubt, and except that if any non-GPL license // choice is available it will apply instead, Sun elects to use only // the General Public License version 2 (GPLv2) at this time for any // software where a choice of GPL license versions is made // available with the language indicating that GPLv2 or any later version // may be used, or where a choice of which version of the GPL is applied is // otherwise unspecified. // // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, // CA 95054 USA or visit www.sun.com if you need additional information or // have any questions. // // ========== Copyright Header End ============================================ wildcard state LOAD_addr54_0( {1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 1'b0, 1'b0, 2'h0} ); wildcard state LOAD_addr54_1( {1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 1'b0, 1'b0, 2'h1} ); wildcard state LOAD_addr54_2( {1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 1'b0, 1'b0, 2'h2} ); wildcard state LOAD_addr54_3( {1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 1'b0, 1'b0, 2'h3} ); // PREFETCH fbhit diag reqtype nc jbi inv pf addr54 state PREFETCH_addr54_0( {1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 1'b0, 1'b1, 2'h0} ); state PREFETCH_addr54_1( {1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 1'b0, 1'b1, 2'h1} ); state PREFETCH_addr54_2( {1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 1'b0, 1'b1, 2'h2} ); state PREFETCH_addr54_3( {1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 1'b0, 1'b1, 2'h3} ); // IMISS fbhit diag reqtype nc jbi inv pf addr54 wildcard state IMISS_addr5_0( {1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 1'b0, 1'b0, 2'h0} ); wildcard state IMISS_addr5_1( {1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 1'b0, 1'b0, 2'h2} ); // STORE/BLKSTORE/BLKINITST fbhit diag reqtype nc jbi inv pf addr54 wildcard state STORE_addr54_0( {1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 1'b0, 1'bx, 2'h0} ); wildcard state STORE_addr54_1( {1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 1'b0, 1'bx, 2'h1} ); wildcard state STORE_addr54_2( {1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 1'b0, 1'bx, 2'h2} ); wildcard state STORE_addr54_3( {1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 1'b0, 1'bx, 2'h3} ); // CAS1 fbhit diag reqtype nc jbi inv pf addr54 state CAS1_addr54_0( {1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 1'b0, 1'b0, 2'h0} ); state CAS1_addr54_1( {1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 1'b0, 1'b0, 2'h1} ); state CAS1_addr54_2( {1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 1'b0, 1'b0, 2'h2} ); state CAS1_addr54_3( {1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 1'b0, 1'b0, 2'h3} ); // SWAP fbhit diag reqtype nc jbi inv pf addr54 state SWAP_addr54_0( {1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 1'b0, 1'b0, 2'h0} ); state SWAP_addr54_1( {1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 1'b0, 1'b0, 2'h1} ); state SWAP_addr54_2( {1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 1'b0, 1'b0, 2'h2} ); state SWAP_addr54_3( {1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 1'b0, 1'b0, 2'h3} ); // STRLOAD fbhit diag reqtype nc jbi inv pf addr54 state STRLOAD_addr54_0( {1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 1'b0, 1'b0, 2'h0} ); state STRLOAD_addr54_1( {1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 1'b0, 1'b0, 2'h1} ); state STRLOAD_addr54_2( {1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 1'b0, 1'b0, 2'h2} ); state STRLOAD_addr54_3( {1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 1'b0, 1'b0, 2'h3} ); // STRST fbhit diag reqtype nc jbi inv pf addr54 wildcard state STRST_addr54_0( {1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 1'b0, 1'b0, 2'h0} ); wildcard state STRST_addr54_1( {1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 1'b0, 1'b0, 2'h1} ); wildcard state STRST_addr54_2( {1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 1'b0, 1'b0, 2'h2} ); wildcard state STRST_addr54_3( {1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 1'b0, 1'b0, 2'h3} ); /* // FWDRQ_LOAD fbhit diag reqtype nc jbi inv pf addr54 state FWDRQ_LOAD_addr54_0( {1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 1'b0, 1'b0, 2'h0} ); state FWDRQ_LOAD_addr54_1( {1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 1'b0, 1'b0, 2'h1} ); state FWDRQ_LOAD_addr54_2( {1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 1'b0, 1'b0, 2'h2} ); state FWDRQ_LOAD_addr54_3( {1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 1'b0, 1'b0, 2'h3} ); // FWDRQ_STORE fbhit diag reqtype nc jbi inv pf addr54 state FWDRQ_STORE_addr54_0( {1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 1'b0, 1'b0, 2'h0} ); state FWDRQ_STORE_addr54_1( {1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 1'b0, 1'b0, 2'h1} ); state FWDRQ_STORE_addr54_2( {1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 1'b0, 1'b0, 2'h2} ); state FWDRQ_STORE_addr54_3( {1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 1'b0, 1'b0, 2'h3} ); */ // RDD fbhit diag reqtype nc jbi inv pf addr54 wildcard state RDD_addr54_0( {1'b1, 1'b0, 5'bxx001, 1'bx, 1'b1, 1'bx, 1'bx, 2'h0} ); wildcard state RDD_addr54_1( {1'b1, 1'b0, 5'bxx001, 1'bx, 1'b1, 1'bx, 1'bx, 2'h1} ); wildcard state RDD_addr54_2( {1'b1, 1'b0, 5'bxx001, 1'bx, 1'b1, 1'bx, 1'bx, 2'h2} ); wildcard state RDD_addr54_3( {1'b1, 1'b0, 5'bxx001, 1'bx, 1'b1, 1'bx, 1'bx, 2'h3} ); // WR8 fbhit diag reqtype nc jbi inv pf addr54 wildcard state WR8_addr54_0( {1'b1, 1'b0, 5'bxx010, 1'bx, 1'b1, 1'bx, 1'bx, 2'h0} ); wildcard state WR8_addr54_1( {1'b1, 1'b0, 5'bxx010, 1'bx, 1'b1, 1'bx, 1'bx, 2'h1} ); wildcard state WR8_addr54_2( {1'b1, 1'b0, 5'bxx010, 1'bx, 1'b1, 1'bx, 1'bx, 2'h2} ); wildcard state WR8_addr54_3( {1'b1, 1'b0, 5'bxx010, 1'bx, 1'b1, 1'bx, 1'bx, 2'h3} );