// ========== Copyright Header Begin ========================================== // // OpenSPARC T2 Processor File: l2_inst_flow_sample.vrhpal // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved // 4150 Network Circle, Santa Clara, California 95054, U.S.A. // // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; version 2 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // // For the avoidance of doubt, and except that if any non-GPL license // choice is available it will apply instead, Sun elects to use only // the General Public License version 2 (GPLv2) at this time for any // software where a choice of GPL license versions is made // available with the language indicating that GPLv2 or any later version // may be used, or where a choice of which version of the GPL is applied is // otherwise unspecified. // // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, // CA 95054 USA or visit www.sun.com if you need additional information or // have any questions. // // ========== Copyright Header End ============================================ wildcard state LOAD_hit ( {HIT, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state LOAD_miss ( {MISS, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state LOAD_dep ( {DEP, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state LOAD_dephit ( {DEPHIT, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state LOAD_depmiss( {DEPMISS, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); // PREFETCH vld diag reqtype nc jbi cputh inv pf bis wildcard state PREFETCH_hit ( {HIT, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} ); wildcard state PREFETCH_miss ( {MISS, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} ); wildcard state PREFETCH_dep ( {DEP, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} ); wildcard state PREFETCH_dephit ( {DEPHIT, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} ); wildcard state PREFETCH_depmiss( {DEPMISS, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} ); // IMISS vld diag reqtype nc jbi cputh inv pf bis wildcard state IMISS_hit ( {HIT, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state IMISS_miss ( {MISS, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state IMISS_dep ( {DEP, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state IMISS_dephit ( {DEPHIT, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state IMISS_depmiss( {DEPMISS, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); // STORE vld diag reqtype nc jbi cputh inv pf bis wildcard state STORE_hit ( {HIT, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state STORE_miss ( {MISS, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state STORE_dep ( {DEP, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state STORE_dephit ( {DEPHIT, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state STORE_depmiss( {DEPMISS, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); // BLKSTORE vld diag reqtype nc jbi cputh inv pf bis wildcard state BLKSTORE_hit ( {HIT, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} ); wildcard state BLKSTORE_miss ( {MISS, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} ); wildcard state BLKSTORE_dep ( {DEP, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} ); wildcard state BLKSTORE_dephit ( {DEPHIT, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} ); wildcard state BLKSTORE_depmiss( {DEPMISS, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} ); // BLKINITST vld diag reqtype nc jbi cputh inv pf bis wildcard state BLKINITST_hit ( {HIT, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} ); wildcard state BLKINITST_miss ( {MISS, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} ); wildcard state BLKINITST_dep ( {DEP, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} ); wildcard state BLKINITST_dephit ( {DEPHIT, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} ); wildcard state BLKINITST_depmiss( {DEPMISS, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} ); // CAS1 vld diag reqtype nc jbi cputh inv pf bis wildcard state CAS1_hit ( {HIT, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state CAS1_miss ( {MISS, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state CAS1_dep ( {DEP, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state CAS1_dephit ( {DEPHIT, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state CAS1_depmiss( {DEPMISS, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); // CAS2 vld diag reqtype nc jbi cputh inv pf bis // CAS2 never has HIT (true hit: see top) combination //wildcard state CAS2_hit ( {HIT, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state CAS2_miss ( {MISS, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state CAS2_dep ( {DEP, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state CAS2_dephit ( {DEPHIT, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state CAS2_depmiss( {DEPMISS, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); // SWAP vld diag reqtype nc jbi cputh inv pf bis wildcard state SWAP_hit ( {HIT, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state SWAP_miss ( {MISS, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state SWAP_dep ( {DEP, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state SWAP_dephit ( {DEPHIT, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state SWAP_depmiss( {DEPMISS, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); // STRLOAD vld diag reqtype nc jbi cputh inv pf bis wildcard state STRLOAD_hit ( {HIT, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state STRLOAD_miss ( {MISS, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state STRLOAD_dep ( {DEP, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state STRLOAD_dephit ( {DEPHIT, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state STRLOAD_depmiss( {DEPMISS, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); // STRST vld diag reqtype nc jbi cputh inv pf bis wildcard state STRST_hit ( {HIT, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state STRST_miss ( {MISS, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state STRST_dep ( {DEP, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state STRST_dephit ( {DEPHIT, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state STRST_depmiss( {DEPMISS, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); /* // FWDRQ_LOAD vld diag reqtype nc jbi cputh inv pf bis wildcard state FWDRQ_LOAD_hit ( {HIT, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state FWDRQ_LOAD_miss ( {MISS, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state FWDRQ_LOAD_dep ( {DEP, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state FWDRQ_LOAD_dephit ( {DEPHIT, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state FWDRQ_LOAD_depmiss( {DEPMISS, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); // FWDRQ_STORE vld diag reqtype nc jbi cputh inv pf bis wildcard state FWDRQ_STORE_hit ( {HIT, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state FWDRQ_STORE_miss ( {MISS, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state FWDRQ_STORE_dep ( {DEP, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state FWDRQ_STORE_dephit ( {DEPHIT, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state FWDRQ_STORE_depmiss( {DEPMISS, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); */ // RDD vld diag reqtype nc jbi wildcard state RDD_hit ( {HIT, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} ); wildcard state RDD_miss ( {MISS, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} ); wildcard state RDD_dep ( {DEP, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} ); wildcard state RDD_dephit ( {DEPHIT, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} ); wildcard state RDD_depmiss( {DEPMISS, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} ); // WR8 vld diag reqtype nc jbi wildcard state WR8_hit ( {HIT, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} ); wildcard state WR8_miss ( {MISS, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} ); wildcard state WR8_dep ( {DEP, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} ); wildcard state WR8_dephit ( {DEPHIT, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} ); wildcard state WR8_depmiss( {DEPMISS, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} ); // WRI vld diag reqtype nc jbi wildcard state WRI_hit ( {HIT, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} ); wildcard state WRI_miss ( {MISS, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} ); wildcard state WRI_dep ( {DEP, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} ); wildcard state WRI_dephit ( {DEPHIT, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} ); wildcard state WRI_depmiss( {DEPMISS, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} );