// ========== Copyright Header Begin ========================================== // // OpenSPARC T2 Processor File: l2_offmode_directmap_insts_sample.vrhpal // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved // 4150 Network Circle, Santa Clara, California 95054, U.S.A. // // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; version 2 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // // For the avoidance of doubt, and except that if any non-GPL license // choice is available it will apply instead, Sun elects to use only // the General Public License version 2 (GPLv2) at this time for any // software where a choice of GPL license versions is made // available with the language indicating that GPLv2 or any later version // may be used, or where a choice of which version of the GPL is applied is // otherwise unspecified. // // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, // CA 95054 USA or visit www.sun.com if you need additional information or // have any questions. // // ========== Copyright Header End ============================================ wildcard state LOAD_off ( {1'b1, 1'b0, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state LOAD_dmap( {1'b0, 1'b1, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); //wildcard state LOAD_both( {1'b1, 1'b1, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); // PREFETCH off dmap vld diag reqtype nc jbi cputh inv pf bis wildcard state PREFETCH_off ( {1'b1, 1'b0, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} ); wildcard state PREFETCH_dmap( {1'b0, 1'b1, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} ); //wildcard state PREFETCH_both( {1'b1, 1'b1, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} ); // DIAG_LOAD off dmap vld diag reqtype nc jbi cputh inv pf bis wildcard state DIAG_LOAD_off ( {1'b1, 1'b0, 1'b1, 1'b1, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state DIAG_LOAD_dmap( {1'b0, 1'b1, 1'b1, 1'b1, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); //wildcard state DIAG_LOAD_both( {1'b1, 1'b1, 1'b1, 1'b1, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); // DCACHE_INV off dmap vld diag reqtype nc jbi cputh inv pf bis wildcard state DCACHE_INV_off ( {1'b1, 1'b0, 1'b1, 1'b0, LOAD_RQ, 1'b0, 1'b0, 6'bx, 1'b1, 1'b0, 1'b0} ); wildcard state DCACHE_INV_dmap( {1'b0, 1'b1, 1'b1, 1'b0, LOAD_RQ, 1'b0, 1'b0, 6'bx, 1'b1, 1'b0, 1'b0} ); //wildcard state DCACHE_INV_both( {1'b1, 1'b1, 1'b1, 1'b0, LOAD_RQ, 1'b0, 1'b0, 6'bx, 1'b1, 1'b0, 1'b0} ); // IMISS off dmap vld diag reqtype nc jbi cputh inv pf bis wildcard state IMISS_off ( {1'b1, 1'b0, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state IMISS_dmap( {1'b0, 1'b1, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); //wildcard state IMISS_both( {1'b1, 1'b1, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); // ICACHE_INV off dmap vld diag reqtype nc jbi cputh inv pf bis wildcard state ICACHE_INV_off ( {1'b1, 1'b0, 1'b1, 1'b0, IMISS_RQ, 1'b0, 1'b0, 6'bx, 1'b1, 1'b0, 1'b0} ); wildcard state ICACHE_INV_dmap( {1'b0, 1'b1, 1'b1, 1'b0, IMISS_RQ, 1'b0, 1'b0, 6'bx, 1'b1, 1'b0, 1'b0} ); //wildcard state ICACHE_INV_both( {1'b1, 1'b1, 1'b1, 1'b0, IMISS_RQ, 1'b0, 1'b0, 6'bx, 1'b1, 1'b0, 1'b0} ); // STORE off dmap vld diag reqtype nc jbi cputh inv pf bis wildcard state STORE_off ( {1'b1, 1'b0, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state STORE_dmap( {1'b0, 1'b1, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); //wildcard state STORE_both( {1'b1, 1'b1, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); // BLKSTORE off dmap vld diag reqtype nc jbi cputh inv pf bis wildcard state BLKSTORE_off ( {1'b1, 1'b0, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} ); wildcard state BLKSTORE_dmap( {1'b0, 1'b1, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} ); //wildcard state BLKSTORE_both( {1'b1, 1'b1, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} ); // BLKINITST off dmap vld diag reqtype nc jbi cputh inv pf bis wildcard state BLKINITST_off ( {1'b1, 1'b0, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} ); wildcard state BLKINITST_dmap( {1'b0, 1'b1, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} ); //wildcard state BLKINITST_both( {1'b1, 1'b1, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} ); // DIAG_STORE off dmap vld diag reqtype nc jbi cputh inv pf bis wildcard state DIAG_STORE_off ( {1'b1, 1'b0, 1'b1, 1'b1, STORE_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state DIAG_STORE_dmap( {1'b0, 1'b1, 1'b1, 1'b1, STORE_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); //wildcard state DIAG_STORE_both( {1'b1, 1'b1, 1'b1, 1'b1, STORE_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); // CAS1 off dmap vld diag reqtype nc jbi cputh inv pf bis wildcard state CAS1_off ( {1'b1, 1'b0, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state CAS1_dmap( {1'b0, 1'b1, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); //wildcard state CAS1_both( {1'b1, 1'b1, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); // CAS2 off dmap vld diag reqtype nc jbi cputh inv pf bis wildcard state CAS2_off ( {1'b1, 1'b0, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state CAS2_dmap( {1'b0, 1'b1, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); //wildcard state CAS2_both( {1'b1, 1'b1, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); // SWAP off dmap vld diag reqtype nc jbi cputh inv pf bis wildcard state SWAP_off ( {1'b1, 1'b0, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state SWAP_dmap( {1'b0, 1'b1, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); //wildcard state SWAP_both( {1'b1, 1'b1, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); // STRLOAD off dmap vld diag reqtype nc jbi cputh inv pf bis wildcard state STRLOAD_off ( {1'b1, 1'b0, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state STRLOAD_dmap( {1'b0, 1'b1, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); //wildcard state STRLOAD_both( {1'b1, 1'b1, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); // STRST off dmap vld diag reqtype nc jbi cputh inv pf bis wildcard state STRST_off ( {1'b1, 1'b0, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state STRST_dmap( {1'b0, 1'b1, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); //wildcard state STRST_both( {1'b1, 1'b1, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); /* // FWDRQ_LOAD off dmap vld diag reqtype nc jbi cputh inv pf bis wildcard state FWDRQ_LOAD_off ( {1'b1, 1'b0, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state FWDRQ_LOAD_dmap( {1'b0, 1'b1, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); //wildcard state FWDRQ_LOAD_both( {1'b1, 1'b1, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); // FWDRQ_STORE off dmap vld diag reqtype nc jbi cputh inv pf bis wildcard state FWDRQ_STORE_off ( {1'b1, 1'b0, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state FWDRQ_STORE_dmap( {1'b0, 1'b1, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); //wildcard state FWDRQ_STORE_both( {1'b1, 1'b1, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); // FWDRQ_DIAG_LOAD off dmap vld diag reqtype nc jbi cputh inv pf bis wildcard state FWDRQ_DIAG_LOAD_off ( {1'b1, 1'b0, 1'b1, 1'b1, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state FWDRQ_DIAG_LOAD_dmap( {1'b0, 1'b1, 1'b1, 1'b1, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); //wildcard state FWDRQ_DIAG_LOAD_both( {1'b1, 1'b1, 1'b1, 1'b1, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); // FWDRQ_DIAG_STORE off dmap vld diag reqtype nc jbi cputh inv pf bis wildcard state FWDRQ_DIAG_STORE_off ( {1'b1, 1'b0, 1'b1, 1'b1, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); wildcard state FWDRQ_DIAG_STORE_dmap( {1'b0, 1'b1, 1'b1, 1'b1, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); //wildcard state FWDRQ_DIAG_STORE_both( {1'b1, 1'b1, 1'b1, 1'b1, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); */ // PREFETCH_ICE off dmap vld diag reqtype nc jbi cputh inv pf bis wildcard state PFICE_off ( {1'b1, 1'b0, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b1, 1'b1, 1'b0} ); wildcard state PFICE_dmap( {1'b0, 1'b1, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b1, 1'b1, 1'b0} ); //wildcard state PFICE_both( {1'b1, 1'b1, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b1, 1'b1, 1'b0} ); // RDD off dmap vld diag reqtype nc jbi wildcard state RDD_off ( {1'b1, 1'b0, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} ); wildcard state RDD_dmap( {1'b0, 1'b1, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} ); //wildcard state RDD_both( {1'b1, 1'b1, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} ); // WR8 off dmap vld diag reqtype nc jbi wildcard state WR8_off ( {1'b1, 1'b0, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} ); wildcard state WR8_dmap( {1'b0, 1'b1, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} ); //wildcard state WR8_both( {1'b1, 1'b1, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} ); // WRI off dmap vld diag reqtype nc jbi wildcard state WRI_off ( {1'b1, 1'b0, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} ); wildcard state WRI_dmap( {1'b0, 1'b1, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} ); //wildcard state WRI_both( {1'b1, 1'b1, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} );