// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: l2sat_defines.vrhpal
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
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// ========== Copyright Header End ============================================
#define CTRUE       37
#define REQTYPE     25:21
#define NC	    20
#define JBI_INST    19
#define	PF	    11
#define BIS	    10


// ccx_cpx_sequence
#define CPX_NO_REQ        17'b00000000_0_xxxxxxxx
#define CPX_NO_REQ_G0     17'b00000000_0_xxxxxxx0
#define CPX_NO_REQ_G1     17'b00000000_0_xxxxxxx1
#define CPX_SINGLE_REQ    17'b00000001_0_xxxxxxxx
#define CPX_SINGLE_REQ_G0 17'b00000001_0_xxxxxxx0
#define CPX_SINGLE_REQ_G1 17'b00000001_0_xxxxxxx1
#define CPX_DOUBLE_REQ    17'b00000001_1_xxxxxxxx
#define CPX_DOUBLE_REQ_G0 17'b00000001_1_xxxxxxx0
#define CPX_DOUBLE_REQ_G1 17'b00000001_1_xxxxxxx1

// ccx_pcx_sequence
//    requests only to L2 bank0, all combos of gnts and atm/non reqs
#define PCX_NO_REQ        24'b00000000_00000000_xxxxxxxx
#define PCX_NO_REQ_G0     24'b00000000_00000000_xxxxxxx0
#define PCX_NO_REQ_G1     24'b00000000_00000000_xxxxxxx1
#define PCX_SINGLE_REQ    24'b00000001_00000000_xxxxxxxx
#define PCX_SINGLE_REQ_G0 24'b00000001_00000000_xxxxxxx0
#define PCX_SINGLE_REQ_G1 24'b00000001_00000000_xxxxxxx1
#define PCX_DOUBLE_REQ    24'b00000001_00000001_xxxxxxxx
#define PCX_DOUBLE_REQ_G0 24'b00000001_00000001_xxxxxxx0
#define PCX_DOUBLE_REQ_G1 24'b00000001_00000001_xxxxxxx1

// PCX reqtypes
#define LOAD_RQ    5'b00000
#define IMISS_RQ   5'b10000
#define STORE_RQ   5'b00001
#define CAS1_RQ    5'b00010
#define CAS2_RQ    5'b00011
#define SWAP_RQ    5'b00111
#define STRLOAD_RQ 5'b00100
#define STRST_RQ   5'b00101
#define INT_RQ     5'b01001
#define FWD_RQ     5'b01101
#define FILL       5'b11111

// CPX rtntypes
#define LOAD_RET    4'b0000
#define IFILL_RET   4'b0001
#define ST_ACK      4'b0100
#define STRLOAD_RET 4'b0010
#define STRST_ACK   4'b0110
#define INT_RET     4'b0111
#define FWD_RPY_RET 4'b1011
#define EVICT_REQ   4'b0011
#define ERR_RET     4'b1100

// l2_inst_flow
#define HIT     4'b1000
#define MISS    4'b0000
#define DEP     4'bx100
#define DEPHIT  4'b1010
#define DEPMISS 4'b0010

// l2_error_status_reg_cov
#define LDAC_0 10'bx, 1'b0, 21'bx
#define LDAU_0 11'bx, 1'b0, 20'bx
#define LDWC_0 12'bx, 1'b0, 19'bx
#define LDWU_0 13'bx, 1'b0, 18'bx
#define LDRC_0 14'bx, 1'b0, 17'bx
#define LDRU_0 15'bx, 1'b0, 16'bx
#define LDSC_0 16'bx, 1'b0, 15'bx
#define LDSU_0 17'bx, 1'b0, 14'bx
#define LTC_0  18'bx, 1'b0, 13'bx
#define LRU_0  19'bx, 1'b0, 12'bx
#define LVU_0  20'bx, 1'b0, 11'bx
#define DAC_0  21'bx, 1'b0, 10'bx
#define DAU_0  22'bx, 1'b0,  9'bx
#define DRC_0  23'bx, 1'b0,  8'bx
#define DRU_0  24'bx, 1'b0,  7'bx
#define DSC_0  25'bx, 1'b0,  6'bx
#define DSU_0  26'bx, 1'b0,  5'bx
#define LVC_0  29'bx, 1'b0,  2'bx
#define LDAC_1 10'bx, 1'b1, 21'bx
#define LDAU_1 11'bx, 1'b1, 20'bx
#define LDWC_1 12'bx, 1'b1, 19'bx
#define LDWU_1 13'bx, 1'b1, 18'bx
#define LDRC_1 14'bx, 1'b1, 17'bx
#define LDRU_1 15'bx, 1'b1, 16'bx
#define LDSC_1 16'bx, 1'b1, 15'bx
#define LDSU_1 17'bx, 1'b1, 14'bx
#define LTC_1  18'bx, 1'b1, 13'bx
#define LRU_1  19'bx, 1'b1, 12'bx
#define LVU_1  20'bx, 1'b1, 11'bx
#define DAC_1  21'bx, 1'b1, 10'bx
#define DAU_1  22'bx, 1'b1,  9'bx
#define DRC_1  23'bx, 1'b1,  8'bx
#define DRU_1  24'bx, 1'b1,  7'bx
#define DSC_1  25'bx, 1'b1,  6'bx
#define DSU_1  26'bx, 1'b1,  5'bx
#define LVC_1  29'bx, 1'b1,  2'bx

// l2_notdata_error_reg_cov
#define NDSP_0 1'b0, 1'bx
#define NDDM_0 1'bx, 1'b0
#define NDSP_1 1'b1, 1'bx
#define NDDM_1 1'bx, 1'b1


// l2_atomic_store_cov
#define CAS_STORE      14'b0000000_0000001
#define CAS_BLKSTORE   14'b0000000_0000010
#define CAS_BLKINITST  14'b0000000_0000100
#define CAS_STRST      14'b0000000_0001000
#define CAS_FWDRQST    14'b0000000_0010000
#define CAS_WR8        14'b0000000_0100000
#define CAS_WRI        14'b0000000_1000000
#define SWAP_STORE     14'b0000001_0000000
#define SWAP_BLKSTORE  14'b0000010_0000000
#define SWAP_BLKINITST 14'b0000100_0000000
#define SWAP_STRST     14'b0001000_0000000
#define SWAP_FWDRQST   14'b0010000_0000000
#define SWAP_WR8       14'b0100000_0000000
#define SWAP_WRI       14'b1000000_0000000

// l2_pst1_dataerr_pst2_tagerr_cov
#define PST12_STORE 3'b001
#define PST12_STRST 3'b010
#define PST12_WR8   3'b100