// ========== Copyright Header Begin ========================================== // // OpenSPARC T2 Processor File: misc_cov_if.vrhpal // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved // 4150 Network Circle, Santa Clara, California 95054, U.S.A. // // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; version 2 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // // For the avoidance of doubt, and except that if any non-GPL license // choice is available it will apply instead, Sun elects to use only // the General Public License version 2 (GPLv2) at this time for any // software where a choice of GPL license versions is made // available with the language indicating that GPLv2 or any later version // may be used, or where a choice of which version of the GPL is applied is // otherwise unspecified. // // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, // CA 95054 USA or visit www.sun.com if you need additional information or // have any questions. // // ========== Copyright Header End ============================================ #ifndef __MISC_COV_IF_VRH__ #define __MISC_COV_IF_VRH__ #include #inc "l2sat_cov_inc.pal" interface misc_cov_if { // Common & Clock Signals // This clock declaration allows referencing "l2sat_coverage_ifc.clock" #ifdef FC_COVERAGE input clock CLOCK verilog_node "`TOP.cpu.l2t0.gclk"; #else input clock CLOCK verilog_node "l2sat_top.clock"; #endif //for l2_iq_cas12_samp input iqsel_px2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.iqsel_px2"; input ique_iq_arb_atm_px2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.ique_iq_arb_atm_px2"; input iqu_sel_iq_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].iqu.iqu_sel_iq"; //for l2_error_vuad_ce_samp input arb_vuad_ce_err_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].misbuf.arb_vuad_ce_err_c2_qual"; input [15:0] l2t_l2d_way_sel_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].l2t_l2d_way_sel_c2"; input tag_hit_unqual_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].tag_hit_unqual_c2"; //for l2_atomic_store_samp input arbctl_inst_vld_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_inst_vld_c2"; input tagctl_hit_l2orfb_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].tagctl.tag_hit_l2orfb_c2"; input [40:0] arbdp_inst_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arbdec.arbdp_inst_c2"; input [39:0] arbdp_addr_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arbadr.arbdp_addr_c2"; //for l2_pst1_dataerr_pst2_tagerr_samp input decdp_pst_inst_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb_decdp_pst_inst_c2"; input data_corr_err_c8_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].deccck.data_corr_err_c8"; input par_err_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].tagdp.par_err_c2"; // for l2_pcx_siu_same_addr_samp and l2_pcx_siu_diff_addr_samp input pcx_l2t_data_rdy_px1 PSAMPLE #-3 verilog_node "$L2T_PATH[0].pcx_l2t_data_rdy_px1"; input pcx_l2t_atm_px1 PSAMPLE #-3 verilog_node "$L2T_PATH[0].pcx_l2t_atm_px1"; input [129:0] pcx_l2t_data_px2 PSAMPLE #-3 verilog_node "$L2T_PATH[0].pcx_l2t_data_px2"; input sii_l2t_req_vld PSAMPLE #-3 verilog_node "$L2T_PATH[0].sii_l2t_req_vld"; input [31:0] sii_l2t_req PSAMPLE #-3 verilog_node "$L2T_PATH[0].sii_l2t_req"; //CURRENT } #endif