// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: mcusat_cov_ports_binds.vrhpal
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
#inc "mcusat_cov_inc.pal";
#ifndef __DRAM_PORTS_VRH__
#define __DRAM_PORTS_VRH__

#include <vera_defines.vrh>

//---------------------------------------------------------------
// The clock port
//---------------------------------------------------------------

//port dram_clk_port {
//  dram_gclk;
//}

//port core_clk_port {
//  cmp_clk;
//  cmp_diag_done;
//  cmp_grst_l;
//}

//---------------------------------------------------------------
// dram_que.v , controller state machine
//---------------------------------------------------------------
port dram_que_fsm {
  que_pos;
}

//---------------------------------------------------------------
// rd que status signals
//---------------------------------------------------------------
port dram_rd_que_status_port {
    rd_que_status;
    // 
    //dram_Ch{c}_rd_req                
    //[7:0] dram_Ch{c}_rd_que_wr_ptr  
    //[7:0] dram_Ch{c}_rd_que_rd_ptr 
    //[3:0] dram_Ch{c}_rd_q_cnt     
    //dram_Ch{c}_rd_q_full         
    //[3:0] dram_Ch{c}_rd_colps_q_cnt 
    //dram_Ch{c}_rd_colps_q_full     
    //dram_Ch{c}_rd_q_empty         
    //dram_Ch{c}_rd_colps_q_empty  

}

port dram_rd_q_full_n_req_port {
    fsm_state;
}

//---------------------------------------------------------------
// wr que status signals
//---------------------------------------------------------------
port dram_wr_que_status_port {
    wr_que_status;
}

port dram_wr_q_full_n_req_port {
    fsm_state;
}

port dram_que_wr_picked_port {
    wr_pick;
}

port dram_rd_wr_hit_port {
    rd_wr_hit;
}

// write memory read from the dram side
port dram_wr_data_rd_mem_sample {
    en_n_addr;
}

//---------------------------------------------------------------
// Scrub and request to the same bank, scrb should be picked first.
// No request to same bank in between a scrub
//---------------------------------------------------------------
port dram_scb_req_same_bank_port {
    scb_req;
}
//---------------------------------------------------------------
// Power throttle blk bank open cross with hw refresh issued
//---------------------------------------------------------------
port dram_pt_refresh_blk_bank {
    pt_refresh_blk_bank;
}

//---------------------------------------------------------------
//  refresh monitor signal
//---------------------------------------------------------------
port dram_refresh_all_clr_mon_state_port {
    fsm_state;
}

//---------------------------------------------------------------
//  CAS Queue
//---------------------------------------------------------------
port dram_cas_que_port {
    cas_valid;
}

//---------------------------------------------------------------
//  CAS Queue
//---------------------------------------------------------------
port dram_rd_wr_scrb_schmoo_port {
    rd_wr_scrb_vld;
}

//---------------------------------------------------------------
// RAS/CAS pending cnt, ras_picked, cas_picked
//---------------------------------------------------------------
port dram_ras_cas_pend_cnt_port {
    ras_cas_pend_cnt;
}
port dram_ras_picked_port {
    ras_picked;
}
port dram_cas_picked_port {
    cas_picked;
}

//---------------------------------------------------------------
//  DRAM registers
//---------------------------------------------------------------
port dram_reg_port {
    registers;
}
port dram_reg_ack_nack_port {
    ack_nack;
}

//---------------------------------------------------------------
//  DRAM perf cntr ( control and sticky bit )
//---------------------------------------------------------------
port dram_perf_cntr_port {
    perf;
}

//---------------------------------------------------------------
//  DRAM parameters : (pa_err,s,r,bank,2ch,8bk) * 4 ( = rd/wr*lo/hi)
//---------------------------------------------------------------
port dram_rank_stack_addr_param_rd_hi_port {
    addr_etc_info_rd_hi;
}
port dram_rank_stack_addr_param_wr_hi_port {
    addr_etc_info_wr_hi;
}
port dram_rank_stack_addr_param_rd_lo_port {
    addr_etc_info_rd_lo;
}
port dram_rank_stack_addr_param_wr_lo_port {
    addr_etc_info_wr_lo;
}

//---------------------------------------------------------------
//  DRAM DP
//---------------------------------------------------------------
port dram_dp_pioson_l2_data_port {
    dp_pioson_l2_data;
}

//---------------------------------------------------------------
//  DRAM for line cov
//---------------------------------------------------------------
//port dram_line_cov_port {
//    line_cov;
//}

//---------------------------------------------------------------
//  Q counters to indicate how much time a request spend in RD/WR Q
//---------------------------------------------------------------
port dram_rd_q_cntr_port {
    cntr;
}
port dram_wr_q_cntr_port {
    cntr;
}

//---------------------------------------------------------------
//  Q counters to indicate how much time between
//  1) rd req and rd data return
//  2) wr req and wr ack
//---------------------------------------------------------------
port dram_rd_req_ack_cntr_port {
    cntr;
}
port dram_wr_req_ack_cntr_port {
    cntr;
}


port dram_cs_bank_req_cntr_port {
    cntr;
}


//---------------------------------------------------------------
// DRAM-l2if rd wr handshake signals
//---------------------------------------------------------------
port dram_rd_wr_l2if_port    {
  rd_wr_l2if;
  //dram_Ch{c}_sctag_dram_rd_req,
  //dram_Ch{c}_sctag_dram_rd_dummy_req,
  //dram_Ch{c}_dram_sctag_rd_ack,
  //dram_Ch{c}_sctag_dram_wr_req,
  //dram_Ch{c}_dram_sctag_wr_ack,
  //dram_Ch{c}_sctag_dram_data_vld,
  //[3:0] dram_Ch{c}_l2if_b0_rd_val,
  //[3:0] dram_Ch{c}_l2if_b1_rd_val,
  //[3:0] dram_Ch{c}_l2if_b0_wr_val,
  //[3:0] dram_Ch{c}_l2if_b1_wr_val,
  //[5:0] dram_Ch{c}_l2if_wr_b0_data_addr,
}

// write memory wr from the l2 side
port dram_wr_data_mem_sample {
    en_n_addr;
}

port dram_err_l2if_port    {
  secc_pa_mecc_scb_secc_mecc;
}

port dram_l2if_data_ret_fifo_port    {
  fifo_en;
}

// Error status and enables
port dram_err_sts_port    {
  err_en_n_sts;
}



//---------------------------------------------------------------
// DRAM-l2if freq schmoo between rd/wr req and sync pulse
//---------------------------------------------------------------
port dram_rd_sync_port    {
  rd_sync;
}

port dram_wr_sync_port    {
  wr_sync;
}

port dram_mcu_ncu_intf_port    {
  intr;
}
port dram_err_intr_ucb_trig_port1    {
  err_intr_ucb_trig1;
}

port dram_ucb_etc_port    {
  ucb_etc;
}
port dram_raw_hazard_port {
    hazard;
}
port dram_refresh_port {
    refresh;
}
port dram_single_channel_port {
    single_ch;
}
port dram_fbd_fast_reset_port {
    fast_reset;
}
port dram_fbd_cmd_a_port {
    cmd;
}
port dram_fbd_cmd_b_port {
    cmd;
}
port dram_fbd_cmd_c_port {
    cmd;
}
port dram_fbd_dimm_cmd_a_port {
    frame;
}
port dram_fbd_dimm_cmd_b_port {
    frame;
}
port dram_fbd_dimm_cmd_c_port {
    frame;
}
port dram_fbd_l0s_state_port {
    l0sstate;
}
port dram_fbd_nb_ts0_port {
    frame;
}
port dram_fbd_nb_stspar_port {
    frame;
}
port dram_fbd_nb_idle_port {
    frame;
}
port dram_fbd_nb_alrt_port {
    frame;
}
port dram_fbd_nb_alrt_assrt_port {
    frame;
}
port dram_fbd_nb_nbde_port {
    frame;
}
port dram_dbg_rd_req_port {
    dbgrd;
}
port dram_dbg_wr_req_port {
    dbgwr;
}
port dram_dbg_err_port {
    dbgerr;
}
port dram_fbd_sb_port {
    frame;
}
port dram_failover_port {
    failover;
}
port dram_fbd0_sb_failover_port {
    failover;
}
port dram_fbd1_sb_failover_port {
    failover;
}
port dram_fbd0_nb_failover_port {
    failover;
}
port dram_fbd1_nb_failover_port {
    failover;
}
port dram_mem_poison_port {
    ecc;
}
port dram_wr_mem_poison_port {
    poison;
}




//---------------------------------------------------------------



. sub coreBindings {
.	my($core_num) = @_;
.	my $c	      = $core_num;

//bind dram_clk_port dram_Ch${c}_dram_clk_bind {
//  dram_gclk        dram_coverage_ifc_dram_clk.dram_gclk;
//}

//bind core_clk_port dram_Ch${c}_core_clk_bind {
//  cmp_clk          dram_coverage_ifc_core_clk.cmp_clk;
//  cmp_diag_done    dram_coverage_ifc_core_clk.cmp_diag_done;
//  cmp_grst_l       dram_coverage_ifc_core_clk.cmp_grst_l;
//}

bind dram_que_fsm ${prefix}mcu_que_fsm_sample_bind_Ch${c} {
  que_pos 	dram_coverage_ifc_dram_clk.dram_Ch${c}_que_pos;
  }

bind dram_rd_que_status_port ${prefix}mcu_rd_que_status_sample_bind_Ch${c}_l2b0 {
  rd_que_status    {
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_req,
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_que_wr_ptr,
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_que_rd_ptr,
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_q_cnt,
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_q_full,
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_colps_q_cnt,
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_colps_q_full,
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_q_empty,
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_colps_q_empty
                   };
  }

bind dram_rd_que_status_port ${prefix}mcu_rd_que_status_sample_bind_Ch${c}_l2b1 {
  rd_que_status    {
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_req,
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_que_wr_ptr,
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_que_rd_ptr,
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_q_cnt,
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_q_full,
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_colps_q_cnt,
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_colps_q_full,
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_q_empty,
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_colps_q_empty
                   };
  }

bind dram_rd_q_full_n_req_port ${prefix}mcu_rd_q_full_n_req_sample_bind_Ch${c} {
    fsm_state  dram_coverage_ifc_core_clk.dram_rd_req_q_full_Ch${c}_rd_taken_state;
  }

bind dram_scb_req_same_bank_port ${prefix}mcu_scb_req_same_bank_sample_bind_Ch${c} {
    scb_req  {
              dram_coverage_ifc_dram_clk.dram_Ch${c}_scrb_indx_val,
              dram_coverage_ifc_dram_clk.dram_Ch${c}_que_l2req_valid,
              dram_coverage_ifc_dram_clk.dram_Ch${c}_que_pos 
             };
}

bind dram_wr_que_status_port ${prefix}mcu_wr_que_status_sample_bind_Ch${c}_l2b0 {
  wr_que_status    {
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_req,
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_que_wr_ptr,
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_que_rd_ptr,
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_q_cnt,
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_q_full,
                     //dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_colps_q_cnt,       // not in N2
                     //dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_colps_q_full,       // not in N2
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_q_empty,
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_colps_q_empty
                   };
}

bind dram_wr_que_status_port ${prefix}mcu_wr_que_status_sample_bind_Ch${c}_l2b1 {
  wr_que_status    {
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_req,
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_que_wr_ptr,
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_que_rd_ptr,
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_q_cnt,
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_q_full,
                     //dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_colps_q_cnt,       // not in N2
                     //dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_colps_q_full,       // not in N2
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_q_empty,
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_colps_q_empty
                   };
}

bind dram_wr_q_full_n_req_port ${prefix}l2_mcu_intf_wr_q_full_n_req_sample_bind_Ch${c}_l2b0 {
    fsm_state  dram_coverage_ifc_core_clk.dram_l2b0_wr_req_q_full_Ch${c}_wr_taken_state;
  }
bind dram_wr_q_full_n_req_port ${prefix}l2_mcu_intf_wr_q_full_n_req_sample_bind_Ch${c}_l2b1 {
    fsm_state  dram_coverage_ifc_core_clk.dram_l2b0_wr_req_q_full_Ch${c}_wr_taken_state;
  }

bind dram_que_wr_picked_port  ${prefix}mcu_que_pick_wr_first_sample_bind_Ch${c} {
    wr_pick dram_coverage_ifc_dram_clk.dram_Ch${c}_que_pick_wr_first;
  }


bind dram_rd_wr_hit_port ${prefix}mcu_rd_wr_hit_sample_bind_Ch${c} {
    rd_wr_hit dram_coverage_ifc_dram_clk.dram_Ch${c}_que_rd_wr_hit;
}

bind dram_refresh_all_clr_mon_state_port ${prefix}mcu_refresh_all_clr_mon_state_sample_bind_Ch${c} {
    fsm_state dram_coverage_ifc_dram_clk.dram_Ch${c}_refresh_all_clr_mon_state;
}

bind dram_cas_que_port ${prefix}mcu_cas_que_sample_bind_Ch${c} {
    cas_valid dram_coverage_ifc_dram_clk.dram_Ch${c}_que_cas_valid;
}


bind dram_ras_cas_pend_cnt_port ${prefix}mcu_ras_cas_pend_cnt_sample_bind_Ch${c} {  // not necessary for N2
    ras_cas_pend_cnt {
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_ras_pend_cnt,
                     dram_coverage_ifc_dram_clk.dram_Ch${c}_cas_pend_cnt
                     };
}
bind dram_ras_picked_port  ${prefix}mcu_ras_picked_sample_bind_Ch${c} {
    ras_picked  dram_coverage_ifc_dram_clk.dram_Ch${c}_ras_picked;
}
bind dram_cas_picked_port ${prefix}mcu_cas_picked_sample_bind_Ch${c} {   // not necessary for N2
    cas_picked  dram_coverage_ifc_dram_clk.dram_Ch${c}_que_cas_picked;
}

bind dram_rd_wr_scrb_schmoo_port ${prefix}mcu_rd_wr_scrb_schmoo_sample_bind_Ch${c}_l2b0 {
    rd_wr_scrb_vld { 
                  dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_req_2a_addr_vld,
                  dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_req_2a_addr_vld,
                  dram_coverage_ifc_dram_clk.dram_Ch${c}_scrb_req_2a_addr_vld 
              };
}
bind dram_rd_wr_scrb_schmoo_port ${prefix}mcu_rd_wr_scrb_schmoo_sample_bind_Ch${c}_l2b1 {
    rd_wr_scrb_vld { 
                  dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_req_2a_addr_vld,
                  dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_req_2a_addr_vld,
                  dram_coverage_ifc_dram_clk.dram_Ch${c}_scrb_req_2a_addr_vld 
              };
}


//    registers { 
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_chip_config_reg,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_mode_reg,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_rrd_reg,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_rc_reg,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_rcd_reg,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_wtr_dly_reg,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_rtw_dly_reg,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_rtp_reg,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_ras_reg,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_rp_reg,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_wr_reg,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_mrd_reg,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_iwtr_reg,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_ext_mode_reg2,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_ext_mode_reg1,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_ext_mode_reg3,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_que_eight_bank_mode,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_que_rank1_present,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_que_channel_disabled,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_que_addr_bank_low_sel,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_que_init,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_que_data_del_cnt,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_dram_io_pad_clk_inv,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_dram_io_ptr_clk_inv,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_que_wr_mode_reg_done,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_que_init_status_reg,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_que_dimms_present,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_dram_fail_over_mode,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_dram_fail_over_mask,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_que_dbg_trig_en,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_que_err_sts_reg,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_err_inj_reg,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_sshot_err_reg,
//                  dram_coverage_ifc_dram_clk.dram_Ch${c}_que_err_cnt
//              };
//}
//

bind dram_perf_cntr_port  ${prefix}mcu_perf_cntr_sample_bind_Ch${c} {
    perf {
                  dram_coverage_ifc_dram_clk.dram_Ch${c}_perf_cntl,
                  dram_coverage_ifc_dram_clk.dram_Ch${c}_cnt0_sticky_bit, 
                  dram_coverage_ifc_dram_clk.dram_Ch${c}_cnt1_sticky_bit 
             };
}

bind dram_reg_ack_nack_port ${prefix}mcu_reg_ack_nack_sample_bind_Ch${c} {
    ack_nack {
                  dram_coverage_ifc_dram_clk.dram_Ch${c}_que_l2if_ack_vld,
                  dram_coverage_ifc_dram_clk.dram_Ch${c}_que_l2if_nack_vld 
             };
}

bind dram_rank_stack_addr_param_rd_hi_port ${prefix}mcu_rank_stack_addr_param_rd_hi_sample_bind_Ch${c}_l2b0 {
    addr_etc_info_rd_hi dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_adr_info_hi;
}
bind dram_rank_stack_addr_param_rd_hi_port ${prefix}mcu_rank_stack_addr_param_rd_hi_sample_bind_Ch${c}_l2b1 {
    addr_etc_info_rd_hi dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_adr_info_hi;
}
bind dram_rank_stack_addr_param_wr_hi_port ${prefix}mcu_rank_stack_addr_param_wr_hi_sample_bind_Ch${c}_l2b0 {
    addr_etc_info_wr_hi dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_adr_info_hi;
}
bind dram_rank_stack_addr_param_wr_hi_port ${prefix}mcu_rank_stack_addr_param_wr_hi_sample_bind_Ch${c}_l2b1 {
    addr_etc_info_wr_hi dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_adr_info_hi;
}
bind dram_rank_stack_addr_param_rd_lo_port ${prefix}mcu_rank_stack_addr_param_rd_lo_sample_bind_Ch${c}_l2b0 {
    addr_etc_info_rd_lo dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_adr_info_lo;
}
bind dram_rank_stack_addr_param_rd_lo_port ${prefix}mcu_rank_stack_addr_param_rd_lo_sample_bind_Ch${c}_l2b1 {
    addr_etc_info_rd_lo dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_adr_info_lo;
}
bind dram_rank_stack_addr_param_wr_lo_port ${prefix}mcu_rank_stack_addr_param_wr_lo_sample_bind_Ch${c}_l2b0 {
    addr_etc_info_wr_lo dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_adr_info_lo;
}
bind dram_rank_stack_addr_param_wr_lo_port ${prefix}mcu_rank_stack_addr_param_wr_lo_sample_bind_Ch${c}_l2b1 {
    addr_etc_info_wr_lo dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_adr_info_lo;
}
// to be binded laterx

//    en_n_addr dram_coverage_ifc_dram_clk.dram_Ch${c}_que_mem_addr;
//}
. for ( $i = 0; $i < 8; $i++ ) {

bind dram_rd_q_cntr_port ${prefix}mcu_rd_q_cntr${i}_sample_bind_Ch${c}_l2b0 {
    cntr dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_q_cntr_${i};
}
bind dram_rd_q_cntr_port ${prefix}mcu_rd_q_cntr${i}_sample_bind_Ch${c}_l2b1 {
    cntr dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_q_cntr_${i};
}
bind dram_wr_q_cntr_port ${prefix}mcu_wr_q_cntr${i}_sample_bind_Ch${c}_l2b0 {
    cntr dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_q_cntr_${i};
}
bind dram_wr_q_cntr_port ${prefix}mcu_wr_q_cntr${i}_sample_bind_Ch${c}_l2b1 {
    cntr dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_q_cntr_${i};
}
bind dram_rd_req_ack_cntr_port ${prefix}mcu_rd_req_ack_${i}_sample_bind_Ch${c}_l2b0 {
    cntr dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_req_ack_cntr_${i};
}
bind dram_rd_req_ack_cntr_port ${prefix}mcu_rd_req_ack_${i}_sample_bind_Ch${c}_l2b1 {
    cntr dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_req_ack_cntr_${i};
}
.}

bind dram_wr_req_ack_cntr_port ${prefix}mcu_wr_req_ack_sample_bind_Ch${c}_l2b0 {
    cntr dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_req_ack_cntr;
}
bind dram_wr_req_ack_cntr_port ${prefix}mcu_wr_req_ack_sample_bind_Ch${c}_l2b1 {
    cntr dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_req_ack_cntr;
}

. for ( $ch = 0; $ch < 4; $ch++ ) {
. for ( $i = 0; $i < 8; $i++ ) {
bind dram_cs_bank_req_cntr_port ${prefix}mcu_cs${ch}_bank_req_cntr_${i}_sample_bind_Ch${c} {
    cntr dram_coverage_ifc_dram_clk.dram_Ch${c}_cs${ch}_bank_req_cntr_${i};
}
.}
.}

bind dram_dp_pioson_l2_data_port  ${prefix}mcu_dp_pioson_l2_data_sample_bind_Ch${c} {
    dp_pioson_l2_data {  dram_coverage_ifc_dram_clk.dram_Ch${c}_dp_pioson_l2_chunk,
                         dram_coverage_ifc_dram_clk.dram_Ch${c}_dp_pioson_l2_data
                      };
}

bind dram_raw_hazard_port ${prefix}mcu_raw_hazard_sample_bind_Ch${c} {
    hazard {
             dram_coverage_ifc_dram_clk.dram_Ch${c}_drif0_raw_hazard,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_drif1_raw_hazard
           };
}

bind dram_refresh_port ${prefix}mcu_refresh_sample_bind_Ch${c} {
    refresh {
             dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_ref_go,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_refresh_rank
            };
}

bind dram_single_channel_port ${prefix}mcu_single_channel_sample_bind_Ch${c} {
    single_ch {
             dram_coverage_ifc_dram_clk.dram_Ch${c}_fbd1_data,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_single_channel_mode
            };
}

bind dram_fbd_fast_reset_port ${prefix}mcu_fbd_fast_reset_sample_bind_Ch${c} {
    fast_reset {
             dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic_fast_reset,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic_fbd_state
            };
}

bind dram_fbd_fast_reset_port ${prefix}mcu_fbd_full_reset_sample_bind_Ch${c} {
    fast_reset {
             dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic_fast_reset,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic_fbd_state
            };
}

bind dram_fbd_cmd_a_port ${prefix}mcu_fbd_cmd_a_sample_bind_Ch${c} {
    cmd {
             dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic_sync_frame_req,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic_scr_frame_req,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_dram_cmd_a
            };
}

bind dram_fbd_cmd_b_port ${prefix}mcu_fbd_cmd_b_sample_bind_Ch${c} {
    cmd {
             dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic_config_reg_write,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic_config_reg_read,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic_issue_cke_cmd,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_dram_cmd_b,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_dram_addr_b
            };
}

bind dram_fbd_cmd_c_port ${prefix}mcu_fbd_cmd_c_sample_bind_Ch${c} {
    cmd {
             dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic_config_reg_write,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic_issue_cke_cmd,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_dram_cmd_c,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_dram_addr_c
            };
}

bind dram_fbd_dimm_cmd_a_port ${prefix}mcu_fbd_dimm_cmd_a_sample_bind_Ch${c} {
    frame {
             dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_dram_dimm_a,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_dram_bank_a,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_dram_rank_a
            };
}

bind dram_fbd_dimm_cmd_b_port ${prefix}mcu_fbd_dimm_cmd_b_sample_bind_Ch${c} {
    frame {
             dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_dram_dimm_b,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_dram_bank_b,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_dram_rank_b
            };
}

bind dram_fbd_dimm_cmd_c_port ${prefix}mcu_fbd_dimm_cmd_c_sample_bind_Ch${c} {
    frame {
             dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_dram_dimm_c,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_dram_bank_c,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_dram_rank_c
            };
}

bind dram_fbd_l0s_state_port ${prefix}mcu_fbd_l0s_state_sample_bind_Ch${c} {
    l0sstate {
             dram_coverage_ifc_dram_clk.dram_Ch${c}_l0s_enable,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_l0s_stall
            };
}

bind dram_fbd_nb_ts0_port ${prefix}mcu_fbd_nb_ts0_sample_bind_Ch${c} {
    frame {
             dram_coverage_ifc_dram_clk.dram_Ch${c}_ts0_hdr_0,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_ts0_hdr_1
            };
}

bind dram_fbd_nb_stspar_port ${prefix}mcu_fbd_nb_stspar_sample_bind_Ch${c} {
    frame {
             dram_coverage_ifc_dram_clk.dram_Ch${c}_sts_par_0,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_sts_par_1
            };
}

bind dram_fbd_nb_idle_port ${prefix}mcu_fbd_nb_idle_sample_bind_Ch${c} {
    frame {
             dram_coverage_ifc_dram_clk.dram_Ch${c}_idle_0,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_idle_1
            };
}

bind dram_fbd_nb_alrt_port ${prefix}mcu_fbd_nb_alrt_sample_bind_Ch${c} {
    frame {
             dram_coverage_ifc_dram_clk.dram_Ch${c}_alrt_0,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_alrt_1
            };
}

bind dram_fbd_nb_alrt_assrt_port ${prefix}mcu_fbd_nb_alrt_assrt_sample_bind_Ch${c} {
    frame {
             dram_coverage_ifc_dram_clk.dram_Ch${c}_alrt_assrt_0,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_alrt_assrt_1
            };
}

bind dram_fbd_nb_nbde_port ${prefix}mcu_fbd_nb_nbde_sample_bind_Ch${c} {
    frame {
             dram_coverage_ifc_dram_clk.dram_Ch${c}_nbde_0,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_nbde_1
            };
}

bind dram_fbd_sb_port ${prefix}mcu_fbd_sb_frame_sample_bind_Ch${c} {
    frame {
             dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic_f
            };
}

bind dram_failover_port ${prefix}mcu_failover_sample_bind_Ch${c} {
    failover {
             dram_coverage_ifc_dram_clk.dram_Ch${c}_fail_over_mode
            };
}

bind dram_fbd0_sb_failover_port ${prefix}mcu_fbd0_sb_failover_sample_bind_Ch${c} {
    failover {
             dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic0_sb_failover,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic0_sb_failover_mask
            };
}

bind dram_fbd1_sb_failover_port ${prefix}mcu_fbd1_sb_failover_sample_bind_Ch${c} {
    failover {
             dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic1_sb_failover,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic1_sb_failover_mask
            };
}

bind dram_fbd0_nb_failover_port ${prefix}mcu_fbd0_nb_failover_sample_bind_Ch${c} {
    failover {
             dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic0_nb_failover,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic0_nb_failover_mask
            };
}

bind dram_fbd1_nb_failover_port ${prefix}mcu_fbd1_nb_failover_sample_bind_Ch${c} {
    failover {
             dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic1_nb_failover,
             dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic1_nb_failover_mask
            };
}

bind dram_mem_poison_port ${prefix}l2_mcu_intf_mem_poison_sample_bind_Ch${c} {
    ecc     {
             dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_mcu_data_mecc,
             dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_mcu_data_mecc
            };
}

bind dram_wr_mem_poison_port ${prefix}mcu_wr_mem_poison_sample_bind_Ch${c} {
    poison  {
            dram_coverage_ifc_dram_clk.dram_Ch${c}_l2poison_qw
            };
}

//

//    line_cov   	      { dram_coverage_ifc_dram_clk.dram_Ch${c}_que_wl_addr_cnt0,
//			dram_coverage_ifc_dram_clk.dram_Ch${c}_que_wl_addr_cnt1,
//			dram_coverage_ifc_dram_clk.dram_Ch${c}_que_wl_data_addr0_load_cas2, 
//			dram_coverage_ifc_dram_clk.dram_Ch${c}_que_wl_data_addr0_load,
//			dram_coverage_ifc_dram_clk.dram_Ch${c}_que_wl_data_addr1_load
//                      };
//}




//  rd_wr_l2if    {
//                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_sctag_dram_rd_req,
//                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_sctag_dram_rd_dummy_req,
//                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_dram_sctag_rd_ack,
//                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_sctag_dram_wr_req,
//                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_dram_sctag_wr_ack,
//                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_sctag_dram_data_vld,
//                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_b0_rd_val, 	//not in N2
//                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_b1_rd_val,	// not in N2
//                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_l2if_b0_wr_val,
//                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_l2if_b1_wr_val
//
//
//                     //dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_wr_b0_data_addr
//
//                };
//  }

//  rd_wr_l2if    {
//                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_sctag_dram_rd_req,
//                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_sctag_dram_rd_dummy_req,
//                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_dram_sctag_rd_ack,
//                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_sctag_dram_wr_req,
//                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_dram_sctag_wr_ack,
//                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_sctag_dram_data_vld,
//                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_b0_rd_val, 	// not in N2
//                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_b1_rd_val,	// not in N2
//                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_l2if_b0_wr_val,
//                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_l2if_b1_wr_val
//                     //dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_wr_b0_data_addr
//
//                };
//  }
//

bind dram_err_l2if_port ${prefix}l2_mcu_intf_err_sample_bind_Ch${c}_l2b0    {
  secc_pa_mecc_scb_secc_mecc {
                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_dram_sctag_secc_err,
                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_dram_sctag_pa_err,
                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_dram_sctag_mecc_err,
                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_dram_sctag_scb_secc_err,
                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_dram_sctag_scb_mecc_err
                              };
}
bind dram_err_l2if_port ${prefix}l2_mcu_intf_err_sample_bind_Ch${c}_l2b1    {
  secc_pa_mecc_scb_secc_mecc {
                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_dram_sctag_secc_err,
                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_dram_sctag_pa_err,
                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_dram_sctag_mecc_err,
                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_dram_sctag_scb_secc_err,
                     dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_dram_sctag_scb_mecc_err
                              };
}
bind dram_l2if_data_ret_fifo_port ${prefix}mcu_l2if_data_ret_fifo_en_sample_bind_Ch${c}    {
  fifo_en dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_data_ret_fifo_en;
}

bind dram_err_sts_port ${prefix}mcu_err_sts_sample_bind_Ch${c}_l2b0    {
  err_en_n_sts  {
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_scrb_val_d2,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_l2if_secc_err,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_l2if_mecc_err_partial,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_l2if_pa_err,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_err_sts_reg,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en6,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en5,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en4,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en3,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en2,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en1,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en0,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en ,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_addr_reg_en,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_secc_loc_en
                };
}
bind dram_err_sts_port ${prefix}mcu_err_sts_sample_bind_Ch${c}_l2b1    {
  err_en_n_sts  {
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_scrb_val_d2,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_l2if_secc_err,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_l2if_mecc_err_partial,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_l2if_pa_err,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_err_sts_reg,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en6,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en5,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en4,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en3,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en2,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en1,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en0,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en ,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_addr_reg_en,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_secc_loc_en
                };
}

bind dram_wr_data_mem_sample ${prefix}l2_mcu_intf_wr_data_mem_sample_bind_Ch${c}_l2b0 {
    en_n_addr { dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_cpu_wr_en,  
                dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_cpu_wr_addr
              };
}
bind dram_wr_data_mem_sample ${prefix}l2_mcu_intf_wr_data_mem_sample_bind_Ch${c}_l2b1 {
    en_n_addr { dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_cpu_wr_en,  
                dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_cpu_wr_addr
              };
}

bind dram_wr_data_rd_mem_sample ${prefix}mcu_wr_data_rd_mem_sample_bind_Ch${c}_l2b0 {
    en_n_addr { dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_wdq_rd_en,  
                dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_wdq_radr
              };
}
bind dram_wr_data_rd_mem_sample ${prefix}mcu_wr_data_rd_mem_sample_bind_Ch${c}_l2b1 {
    en_n_addr { dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_wdq_rd_en,  
                dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_wdq_radr
              };
}


bind dram_rd_sync_port  ${prefix}l2_mcu_intf_rd_sync_schmoo_sample_bind_Ch${c}_l2b0   {
  rd_sync       { 
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_sctag_dram_rd_req,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_clspine_dram_txrd_sync
                };
}
bind dram_rd_sync_port  ${prefix}l2_mcu_intf_rd_sync_schmoo_sample_bind_Ch${c}_l2b1   {
  rd_sync       { 
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_sctag_dram_rd_req,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_clspine_dram_txrd_sync
                };
}

bind dram_wr_sync_port  ${prefix}l2_mcu_intf_wr_sync_schmoo_sample_bind_Ch${c}_l2b0   {
  wr_sync       { 
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_sctag_dram_wr_req,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_clspine_dram_txwr_sync
                };
}
bind dram_wr_sync_port  ${prefix}l2_mcu_intf_wr_sync_schmoo_sample_bind_Ch${c}_l2b1   {
  wr_sync       { 
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_sctag_dram_wr_req,
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_clspine_dram_txwr_sync
                };
}

bind  dram_err_intr_ucb_trig_port1 ${prefix}mcu_err_intr_ucb_trig1_sample_bind_Ch${c}    {
  err_intr_ucb_trig1 {
                    dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_ucb_trig
                    };
}



bind dram_dbg_wr_req_port ${prefix}mcu_dbg_wr_req_sample_bind_Ch${c} {
    dbgwr {
             dram_coverage_ifc_jbus_clk.dram_Ch${c}_dbg1_wrreq_in_0,
             dram_coverage_ifc_jbus_clk.dram_Ch${c}_dbg1_wrreq_in_1,
             dram_coverage_ifc_jbus_clk.dram_Ch${c}_dbg1_wrreq_out
            };
}


bind dram_dbg_rd_req_port ${prefix}mcu_dbg_rd_req_sample_bind_Ch${c} {
    dbgrd {
             dram_coverage_ifc_jbus_clk.dram_Ch${c}_dbg1_rdreq_in_0,
             dram_coverage_ifc_jbus_clk.dram_Ch${c}_dbg1_rdreq_in_1,
             dram_coverage_ifc_jbus_clk.dram_Ch${c}_dbg1_rdreq_out
            };
}


bind dram_dbg_err_port ${prefix}mcu_dbg_err_sample_bind_Ch${c} {
    dbgerr {
             dram_coverage_ifc_jbus_clk.dram_Ch${c}_ucb_serdes_dtm,
             dram_coverage_ifc_jbus_clk.dram_Ch${c}_dbg1_mecc_err,
             dram_coverage_ifc_jbus_clk.dram_Ch${c}_dbg1_secc_err,
             dram_coverage_ifc_jbus_clk.dram_Ch${c}_dbg1_fbd_err,
             dram_coverage_ifc_jbus_clk.dram_Ch${c}_dbg1_err_mode,
             dram_coverage_ifc_core_clk.dram_Ch0_dbg1_crc21,
             dram_coverage_ifc_core_clk.dram_Ch0_dbg1_err_event
            };
}

.
. } # coreBindings
.

bind dram_ucb_etc_port ${prefix}mcu_ucb_req_pend_ack_int_busy_sample_bind_Ch0    {
  ucb_etc {
                    dram_coverage_ifc_jbus_clk.dram_Ch0_rd_req_vld,
                    dram_coverage_ifc_jbus_clk.dram_Ch0_ucb_req_pend,
                    dram_coverage_ifc_jbus_clk.dram_Ch0_ucb_dram_ack_busy,
                    dram_coverage_ifc_jbus_clk.dram_Ch0_ucb_dram_int_busy
          };
}

bind dram_ucb_etc_port ${prefix}mcu_ucb_req_pend_ack_int_busy_sample_bind_Ch1    {
  ucb_etc {
                    dram_coverage_ifc_jbus_clk.dram_Ch1_rd_req_vld,
                    dram_coverage_ifc_jbus_clk.dram_Ch1_ucb_req_pend,
                    dram_coverage_ifc_jbus_clk.dram_Ch1_ucb_dram_ack_busy,
                    dram_coverage_ifc_jbus_clk.dram_Ch1_ucb_dram_int_busy
          };
}

bind dram_ucb_etc_port ${prefix}mcu_ucb_req_pend_ack_int_busy_sample_bind_Ch2    {
  ucb_etc {
                    dram_coverage_ifc_jbus_clk.dram_Ch2_rd_req_vld,
                    dram_coverage_ifc_jbus_clk.dram_Ch2_ucb_req_pend,
                    dram_coverage_ifc_jbus_clk.dram_Ch2_ucb_dram_ack_busy,
                    dram_coverage_ifc_jbus_clk.dram_Ch2_ucb_dram_int_busy
          };
}

bind dram_ucb_etc_port ${prefix}mcu_ucb_req_pend_ack_int_busy_sample_bind_Ch3    {
  ucb_etc {
                    dram_coverage_ifc_jbus_clk.dram_Ch3_rd_req_vld,
                    dram_coverage_ifc_jbus_clk.dram_Ch3_ucb_req_pend,
                    dram_coverage_ifc_jbus_clk.dram_Ch3_ucb_dram_ack_busy,
                    dram_coverage_ifc_jbus_clk.dram_Ch3_ucb_dram_int_busy
          };
}

bind  dram_mcu_ncu_intf_port ${prefix}mcu_ncu_intf_sample_bind_Ch0    {
  intr          {
                    dram_coverage_ifc_jbus_clk.dram_Ch0_mcu_ncu_ecc,
                    dram_coverage_ifc_jbus_clk.dram_Ch0_mcu_ncu_fbr
                };
}

bind  dram_mcu_ncu_intf_port ${prefix}mcu_ncu_intf_sample_bind_Ch1    {
  intr          {
                    dram_coverage_ifc_jbus_clk.dram_Ch1_mcu_ncu_ecc,
                    dram_coverage_ifc_jbus_clk.dram_Ch1_mcu_ncu_fbr
                };
}

bind  dram_mcu_ncu_intf_port ${prefix}mcu_ncu_intf_sample_bind_Ch2    {
  intr          {
                    dram_coverage_ifc_jbus_clk.dram_Ch2_mcu_ncu_ecc,
                    dram_coverage_ifc_jbus_clk.dram_Ch2_mcu_ncu_fbr
                };
}

bind  dram_mcu_ncu_intf_port ${prefix}mcu_ncu_intf_sample_bind_Ch3    {
  intr          {
                    dram_coverage_ifc_jbus_clk.dram_Ch3_mcu_ncu_ecc,
                    dram_coverage_ifc_jbus_clk.dram_Ch3_mcu_ncu_fbr
                };
}

bind dram_pt_refresh_blk_bank ${prefix}mcu_pt_refresh_blk_bank_sample_bind_Ch0 {
    pt_refresh_blk_bank {
			dram_coverage_ifc_dram_clk.dram_Ch0_pt_selfrsh,
			dram_coverage_ifc_dram_clk.dram_Ch0_pt_blk_new_openbank_d1
     			};
}
bind dram_pt_refresh_blk_bank ${prefix}mcu_pt_refresh_blk_bank_sample_bind_Ch1 {
    pt_refresh_blk_bank {
			dram_coverage_ifc_dram_clk.dram_Ch1_pt_selfrsh,
			dram_coverage_ifc_dram_clk.dram_Ch1_pt_blk_new_openbank_d1
     			};
}
bind dram_pt_refresh_blk_bank ${prefix}mcu_pt_refresh_blk_bank_sample_bind_Ch2 {
    pt_refresh_blk_bank {
			dram_coverage_ifc_dram_clk.dram_Ch2_pt_selfrsh,
			dram_coverage_ifc_dram_clk.dram_Ch2_pt_blk_new_openbank_d1
     			};
}
bind dram_pt_refresh_blk_bank ${prefix}mcu_pt_refresh_blk_bank_sample_bind_Ch3 {
    pt_refresh_blk_bank {
			dram_coverage_ifc_dram_clk.dram_Ch3_pt_selfrsh,
			dram_coverage_ifc_dram_clk.dram_Ch3_pt_blk_new_openbank_d1
     			};
}

// ***********************************************************
// Declare bindings for each core
// ***********************************************************

. foreach $dr (@DRC_STR) {
.	&coreBindings( $dr );
. }

#endif