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// OpenSPARC T2 Processor File: mcusat_err_intr_ucb_trig_sample.vrhpal
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       state s_err_intr0_ucb_trig  (1'b0);
       state s_err_intr1_ucb_trig  (1'b1);

       trans t_err_intr_0_0_ucb_trig  (1'b0 -> 1'b0);
       trans t_err_intr_0_1_ucb_trig  (1'b0 -> 1'b1);
       trans t_err_intr_1_0_ucb_trig  (1'b1 -> 1'b0);
       trans t_err_intr_1_1_ucb_trig  (1'b1 -> 1'b1);


  // bad states
  //bad_state s_not_rd_q_full_n_req_state (not state);

  // bad transitions
  //bad_trans t_not_rd_q_full_n_req_trans (not trans);

//}