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// OpenSPARC T2 Processor File: mcusat_fbd_full_reset_sample.vrhpal
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state s_dsbl (4'b0000);
state s_calb (4'b0001);
state s_trng (4'b0010);
state s_tstg (4'b0011);
state s_plng (4'b0100);
state s_cnfg (4'b0101);
state s_l0   (4'b0110);

// transitions (to same)
trans t_s_dsbl_s_dsbl             (4'b0000 -> 4'b0000);
trans t_s_calb_s_calb             (4'b0001 -> 4'b0001);
trans t_s_trng_s_trng             (4'b0010 -> 4'b0010);
trans t_s_tstg_s_tstg             (4'b0011 -> 4'b0011);
trans t_s_plng_s_plng             (4'b0100 -> 4'b0100);
trans t_s_cnfg_s_cnfg             (4'b0101 -> 4'b0101);
trans t_s_l0_s_l0                 (4'b0110 -> 4'b0110);

// transitions (to diff)
trans t_s_dsbl_s_calb             (4'b0000 -> 4'b0001);
trans t_s_calb_s_dsbl             (4'b0001 -> 4'b0000);
trans t_s_trng_s_tstg             (4'b0010 -> 4'b0011);
trans t_s_tstg_s_plng             (4'b0011 -> 4'b0100);
trans t_s_plng_s_cnfg             (4'b0100 -> 4'b0101);
trans t_s_cnfg_s_l0               (4'b0101 -> 4'b0110);

//bad_state s_invalid (not state) if (fbdic_fast_reset${c} == 0);
//bad_trans t_invalid (not trans) if (fbdic_fast_reset${c} == 0);