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// OpenSPARC T2 Processor File: mcusat_refrsh_issued_all_cas_clr_sample.vrhpal
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       state s_refrsh_issued_all_cas_clr0  (2'b00);
       state s_refrsh_issued_all_cas_clr1  (2'b01);
       state s_refrsh_issued_all_cas_clr2  (2'b10);

       trans t_refrsh_issued_all_cas_clr0_0  (2'b00 -> 2'b00);
       trans t_refrsh_issued_all_cas_clr1_1  (2'b01 -> 2'b01);

       trans t_refrsh_issued_all_cas_clr0_1  (2'b00 -> 2'b01);
       trans t_refrsh_issued_all_cas_clr1_2  (2'b01 -> 2'b10);
       trans t_refrsh_issued_all_cas_clr2_0  (2'b10 -> 2'b00);

  // bad states
  bad_state s_not_refrsh_issued_all_cas_clr_state (not state);

  // bad transitions
  bad_trans t_not_refrsh_issued_all_cas_clr_trans (not trans);

//}