// ========== Copyright Header Begin ========================================== // // OpenSPARC T2 Processor File: ncu_pcx_sample.vrhpal // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved // 4150 Network Circle, Santa Clara, California 95054, U.S.A. // // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; version 2 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // // For the avoidance of doubt, and except that if any non-GPL license // choice is available it will apply instead, Sun elects to use only // the General Public License version 2 (GPLv2) at this time for any // software where a choice of GPL license versions is made // available with the language indicating that GPLv2 or any later version // may be used, or where a choice of which version of the GPL is applied is // otherwise unspecified. // // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, // CA 95054 USA or visit www.sun.com if you need additional information or // have any questions. // // ========== Copyright Header End ============================================ sample ncu_pcx_intf_add_global (ncu_pcx_add[39:32]) { state NCU_ADD ( 8'h80 ); state NIU_ADD ( 8'h81 ); state CCU_ADD ( 8'h83 ); state MCU_ADD ( 8'h84 ); state TCU_ADD ( 8'h85 ); state DBG1_ADD ( 8'h86 ); state DMU_ADD ( 8'h88 ); state RST_ADD ( 8'h89 ); state ASI_ADD ( 8'h90 ); wildcard state PIO_ADD ( 8'Hcx ); state SSI_ADD ( 8'hff ); } sample ncu_pcx_intf_add_mcu (ncu_pcx_add[13:12]) { m_state MCU_ADD (0:3) if (ncu_pcx_add[39:32] === 8'h84); } sample ncu_pcx_intf_add_ncu (ncu_pcx_add[15:0]) { wildcard state INTMAN_REG (16'b0000_00xx_xxxx_x000) if (ncu_pcx_add[39:16] === 24'h800000); state MONDOINVEC_reg (16'h0a00) if (ncu_pcx_add[39:16] === 24'h800000); state SERNUM_REG (16'h1000) if (ncu_pcx_add[39:16] === 24'h800000); state FUSESTAT_REG (16'h1008) if (ncu_pcx_add[39:16] === 24'h800000); state COREAVAIL_REG (16'h1010) if (ncu_pcx_add[39:16] === 24'h800000); state BANKAVAIL_REG (16'h1018) if (ncu_pcx_add[39:16] === 24'h800000); state BANK_ENABLE_REG (16'h1020) if (ncu_pcx_add[39:16] === 24'h800000); state BANK_ENABLE_STATUS_REG (16'h1028) if (ncu_pcx_add[39:16] === 24'h800000); state L2_IDX_HASH_EN_REG (16'h1030) if (ncu_pcx_add[39:16] === 24'h800000); state L2_IDX_HASH_EN_ST_REG (16'h1038) if (ncu_pcx_add[39:16] === 24'h800000); state MEM32_BASE_REG (16'h2000) if (ncu_pcx_add[39:16] === 24'h800000); state MEM32_MASK_REG (16'h2008) if (ncu_pcx_add[39:16] === 24'h800000); state MEM64_BASE_REG (16'h2010) if (ncu_pcx_add[39:16] === 24'h800000); state MEM64_MASK_REG (16'h2018) if (ncu_pcx_add[39:16] === 24'h800000); state IOCON_BASE_REG (16'h2020) if (ncu_pcx_add[39:16] === 24'h800000); state IOCON_MASK_REG (16'h2028) if (ncu_pcx_add[39:16] === 24'h800000); state MMUFSH_REG (16'h2030) if (ncu_pcx_add[39:16] === 24'h800000); wildcard state MDATA0_REG (16'b0000_000x_xxxx_x000) if (ncu_pcx_add[39:16] === 24'h800004); wildcard state MDATA1_REG (16'b0000_001x_xxxx_x000) if (ncu_pcx_add[39:16] === 24'h800004); state MDATA0_ALIAS_REG (16'h0400) if (ncu_pcx_add[39:16] === 24'h800004); state MDATA1_ALIAS_REG (16'h0600) if (ncu_pcx_add[39:16] === 24'h800004); wildcard state MBUSY_REG (16'b0000_100x_xxxx_x000) if (ncu_pcx_add[39:16] === 24'h800004); state MBUSY_ALIAS_REG (16'h0600) if (ncu_pcx_add[39:16] === 24'h800004); state ASI_CORAVAIL_REG (16'h0000) if (ncu_pcx_add[39:16] === 24'h900104); state ASI_COREN_STAT_REG (16'h0010) if (ncu_pcx_add[39:16] === 24'h900104); state ASI_COREN_REG (16'h0020) if (ncu_pcx_add[39:16] === 24'h900104); state ASI_CORRUN_REG (16'h0050) if (ncu_pcx_add[39:16] === 24'h900104); state ASI_CORRUN_STATU_REG (16'h0058) if (ncu_pcx_add[39:16] === 24'h900104); state ASI_CORRUN_W1S_REG (16'h0060) if (ncu_pcx_add[39:16] === 24'h900104); state ASI_CORRUN_W1C_REG (16'h0068) if (ncu_pcx_add[39:16] === 24'h900104); state ASI_INT_VEC_DISP_REG (16'h0000) if (ncu_pcx_add[39:16] === 24'h9001cc); } sample ncu_intr_pcx_int_des (pcx_int_des_reg) { wildcard state INT32_IN32CLK (2'bx1); wildcard state INT32_IN64CLK (2'b1x); } sample ncu_pcx_intf_add_ncu_mem (ncu_pcx_add[9:3]) { m_state INTMAN_REG (0:127) if (ncu_pcx_add[39:16] === 24'h800000); m_state MDATA0_REG (0:63) if (ncu_pcx_add[39:16] === 24'h800004); m_state MDATA1_REG (0:63) if (ncu_pcx_add[39:16] === 24'h800004); m_state MBUSY_REG (0:63) if (ncu_pcx_add[39:16] === 24'h800004); } sample ncu_pcx_intf_type_sample (ncu_pcx_type) { state PCX_LOAD (5'b00000); state PCX_STORE (5'b00001); } sample ncu_pcx_intf_type_trans (ncu_pcx_type) { state PCX_LOAD (5'b00000); state PCX_STORE (5'b00001); state PCX_IFILL (5'b10000); trans PCX_TYPE_TRAN00 ("PCX_LOAD"->"PCX_LOAD"); trans PCX_TYPE_TRAN01 ("PCX_LOAD"->"PCX_STORE"); trans PCX_TYPE_TRAN02 ("PCX_LOAD"->"PCX_IFILL"); trans PCX_TYPE_TRAN10 ("PCX_STORE"->"PCX_LOAD"); trans PCX_TYPE_TRAN11 ("PCX_STORE"->"PCX_STORE"); trans PCX_TYPE_TRAN12 ("PCX_STORE"->"PCX_IFILL"); trans PCX_TYPE_TRAN20 ("PCX_IFILL"->"PCX_LOAD"); trans PCX_TYPE_TRAN21 ("PCX_IFILL"->"PCX_STORE"); trans PCX_TYPE_TRAN22 ("PCX_IFILL"->"PCX_IFILL"); } sample ncu_pcx_intf_size_sample (ncu_pcx_size) { m_state PCX_BYTE1248 (0:3) if (ncu_pcx_type == 5'bx0000); state PCX_PKT_1BYTE0 (8'b00000001) if (ncu_pcx_type === 5'b0001); state PCX_PKT_1BYTE1 (8'b00000010) if (ncu_pcx_type === 5'b0001); state PCX_PKT_1BYTE2 (8'b00000100) if (ncu_pcx_type === 5'b0001); state PCX_PKT_1BYTE3 (8'b00001000) if (ncu_pcx_type === 5'b0001); state PCX_PKT_1BYTE4 (8'b00010000) if (ncu_pcx_type === 5'b0001); state PCX_PKT_1BYTE5 (8'b00100000) if (ncu_pcx_type === 5'b0001); state PCX_PKT_1BYTE6 (8'b01000000) if (ncu_pcx_type === 5'b0001); state PCX_PKT_1BYTE7 (8'b10000000) if (ncu_pcx_type === 5'b0001); state PCX_PKT_2BYTE0 (8'b00000011) if (ncu_pcx_type === 5'b0001); state PCX_PKT_2BYTE1 (8'b00001100) if (ncu_pcx_type === 5'b0001); state PCX_PKT_2BYTE2 (8'b00110000) if (ncu_pcx_type === 5'b0001); state PCX_PKT_2BYTE3 (8'b11000000) if (ncu_pcx_type === 5'b0001); state PCX_PKT_4BYTE0 (8'b00001111) if (ncu_pcx_type === 5'b0001); state PCX_PKT_4BYTE1 (8'b11110000) if (ncu_pcx_type === 5'b0001); state PCX_PKT_8BYTE0 (8'b11111111) if (ncu_pcx_type === 5'b0001); } sample ncu_pcx_intf_cpu_sample (ncu_pcx_cpu) { m_state CPU_THREAD_ID (0:63); } sample ncu_pcx_intf_b2b_sample (ncu_pcx_b2b) { m_state PCX_B2B (2:34); } sample ncu_pcx_intf_stall_cnt_cov (ncu_pcx_stall_cnt) { m_state STALL (1:50); } cross ncu_pcx_intf_type_add_cross ( ncu_pcx_intf_type_sample , ncu_pcx_intf_add_global); cross ncu_pcx_intf_type_cpu_cross ( ncu_pcx_intf_type_sample , ncu_pcx_intf_cpu_sample); sample ncu_pcx_intf_load_b2b (ncu_pcx_load_b2b) { m_state (2:32); } sample ncu_pcx_intf_store_b2b (ncu_pcx_load_b2b) { m_state (2:32); } sample ncu_pcx_intf_pio_b2b (ncu_pcx_load_b2b) { m_state (2:32); } sample ncu_pcx_intf_niu_b2b (ncu_pcx_load_b2b) { m_state (2:32); } sample ncu_pcx_intf_ccu_b2b (ncu_pcx_load_b2b) { m_state (2:32); } sample ncu_pcx_intf_tcu_b2b (ncu_pcx_load_b2b) { m_state (2:32); } sample ncu_pcx_intf_ssi_b2b (ncu_pcx_load_b2b) { m_state (2:32); } sample ncu_pcx_intf_dmu_b2b (ncu_pcx_load_b2b) { m_state (2:32); } sample ncu_pcx_intf_rst_b2b (ncu_pcx_load_b2b) { m_state (2:32); } sample ncu_pcx_intf_mcu0_b2b (ncu_pcx_load_b2b) { m_state (2:32); } sample ncu_pcx_intf_mcu1_b2b (ncu_pcx_load_b2b) { m_state (2:32); } sample ncu_pcx_intf_mcu2_b2b (ncu_pcx_load_b2b) { m_state (2:32); } sample ncu_pcx_intf_mcu3_b2b (ncu_pcx_load_b2b) { m_state (2:32); } sample ncu_pcx_intf_dbg1_b2b (ncu_pcx_load_b2b) { m_state (2:32); } sample ncu_pcx_intf_pkt_gap (ncu_pcx_pkt_gap_cnt) { m_state (1:10); }