// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: siu_cov.if.vrhpal
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
#ifndef __SIU_COV_IF_VRH__
#define __SIU_COV_IF_VRH__

#include <vera_defines.vrh>

#define OUTPUT_EDGE  PHOLD
#define OUTPUT_SKEW  #3
#define INPUT_EDGE   PSAMPLE
#define INPUT_SKEW   #-3

#ifdef FC_COVERAGE
#define SII	`TOP.cpu.sii
#define SIO	`TOP.cpu.sio
#else
#define SII	siu_top.cpu.sii
#define SIO	siu_top.cpu.sio
#endif



interface siu_coverage_ifc
{
// Common & Clock Signals
input           clk     CLOCK                           verilog_node "`SII.iol2clk";

input           cmp_diag_done           PSAMPLE;

// dmu interface
input           dmureq          INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.dmu_sii_hdr_vld";
input           dmubypass       INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.dmu_sii_reqbypass";
input           dmudatareq      INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.dmu_sii_datareq";
input           dmudatareq16    INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.dmu_sii_datareq16";
input [127:0]   dmudata         INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.dmu_sii_data";
input [1:0]     dmuparity       INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.dmu_sii_parity";
input [15:0]    dmube           INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.dmu_sii_be";
input           dmuwrack_vld    INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.sii_dmu_wrack_vld";
input [3:0]     dmuwrack_tag    INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.sii_dmu_wrack_tag";

//sio-dmu
input           sio_dmu_req     INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.sio_dmu_hdr_vld";
input [127:0]   sio_dmu_data   	INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.sio_dmu_data";

// niu interface
input           niureq          INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.niu_sii_hdr_vld";
input           niubypass       INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.niu_sii_reqbypass";
input           niudatareq      INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.niu_sii_datareq";
input           niudatareq16    INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.niu_sii_datareq16";
input [127:0]   niudata         INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.niu_sii_data";
input [1:0]     niuparity       INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.niu_sii_parity";
input           niuoqdq    	INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.sii_niu_oqdq";
input           niubqdq    	INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.sii_niu_bqdq";

//sio-niu
input           sio_niu_req    	INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.sio_niu_hdr_vld";
input [127:0]   sio_niu_data   	INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.sio_niu_data";
input           niu_sio_dq    	INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.niu_sio_dq";

//ncu-sii
input           ncu_gnt         INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.ncu_sii_gnt";
input           ncu_req         INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.sii_ncu_req";
input           ncu_pm          INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.ncu_sii_pm";
input           ncu_ba01        INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.ncu_sii_ba01";
input           ncu_ba23        INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.ncu_sii_ba23";
input           ncu_ba45        INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.ncu_sii_ba45";
input           ncu_ba67        INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.ncu_sii_ba67";

}

interface siu_coverage_ifc_l2
{
input           clk     	CLOCK		verilog_node "`SII.l2clk";
input           cmp_diag_done	PSAMPLE;

// L2 interface
. for ($bank=0; $bank<8; $bank++)
.{
  input           l2t${bank}_iq_dq		INPUT_EDGE	INPUT_SKEW      verilog_node "`SII.l2t${bank}_sii_iq_dequeue";
  input           l2t${bank}_wib_dq       	INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.l2t${bank}_sii_wib_dequeue";
  input           sii_l2t${bank}        	INPUT_EDGE     	INPUT_SKEW     	verilog_node "`SII.sii_l2t${bank}_req_vld";
  input  [31:0]   sii_l2t${bank}_data   	INPUT_EDGE     	INPUT_SKEW     	verilog_node "`SII.sii_l2t${bank}_req";

input l2b${bank}_sio_ctag_vld INPUT_EDGE INPUT_SKEW verilog_node "`SIO.l2b${bank}_sio_ctag_vld";
input [31:0] l2b${bank}_sio_data INPUT_EDGE INPUT_SKEW verilog_node "`SIO.l2b${bank}_sio_data"; 

.}

}

// ipdohq ipodq
.for ($q=0; $q<2; $q++)
.{
interface siu_coverage_ipdoq${q}_rd 
{
input		clk		CLOCK		verilog_node "`SII.ipdohq${q}.rdclk";
input           cmp_diag_done	PSAMPLE;

input		h_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdohq${q}.rd_en";
input [3:0]	h_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdohq${q}.rd_adr";
input		d_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdodq${q}_l.rd_en";
input [5:0]	d_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdodq${q}_l.rd_adr";
}

interface siu_coverage_ipdoq${q}_wr 
{
input		clk		CLOCK		verilog_node "`SII.ipdohq${q}.wrclk";
input           cmp_diag_done	PSAMPLE;

input		h_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdohq${q}.wr_en";
input [3:0]	h_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdohq${q}.wr_adr";
input		d_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdodq${q}_l.wr_en";
input [5:0]	d_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdodq${q}_l.wr_adr";

}
.}

.for ($q=0; $q<2; $q++)
.{
interface siu_coverage_ipdbq${q}_rd
{
input		clk		CLOCK		verilog_node "`SII.ipdbhq${q}.rdclk";
input           cmp_diag_done	PSAMPLE;

input		h_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdbhq${q}.rd_en";
input [3:0]	h_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdbhq${q}.rd_adr";
input		d_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdbdq${q}_l.rd_en";
input [5:0]	d_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdbdq${q}_l.rd_adr";
}

interface siu_coverage_ipdbq${q}_wr
{
input		clk		CLOCK		verilog_node "`SII.ipdbhq${q}.wrclk";
input           cmp_diag_done	PSAMPLE;

input		h_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdbhq${q}.wr_en";
input [3:0]	h_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdbhq${q}.wr_adr";
input		d_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdbdq${q}_l.wr_en";
input [5:0]	d_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipdbdq${q}_l.wr_adr";
}
.}

.for ($q=0; $q<8; $q++)
.{
interface siu_coverage_ildq${q}
{
input		clk		CLOCK		verilog_node "`SII.ildq${q}.rdclk";
input           cmp_diag_done	PSAMPLE;

input		wr_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ildq${q}.wr_en";
input [4:0]	wr_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ildq${q}.wr_adr";
input		rd_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ildq${q}.rd_en";
input [4:0]	rd_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ildq${q}.rd_adr";
}
.}

interface siu_coverage_indq
{
input		clk		CLOCK		verilog_node "`SII.indq.rdclk";
input           cmp_diag_done	PSAMPLE;

input		wr_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.indq.wr_en";
input [5:0]	wr_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.indq.wr_adr";
input		rd_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.indq.rd_en";
input [5:0]	rd_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.indq.rd_adr";
}

interface siu_coverage_ipcc_ipcs
{
input		clk		CLOCK		verilog_node "`SII.ipcs0.iol2clk";
input           cmp_diag_done	PSAMPLE;

input		by0_go		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcs0.ipcc_ipcs_by_go";
input [3:0]	by0_raddr	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcs0.ipcc_ipcs_by_raddr";
input		or0_go		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcs0.ipcc_ipcs_or_go";
input [3:0]	or0_raddr	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcs0.ipcc_ipcs_or_raddr";
input		by1_go		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcs1.ipcc_ipcs_by_go";
input [3:0]	by1_raddr	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcs1.ipcc_ipcs_by_raddr";
input		or1_go		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcs1.ipcc_ipcs_or_go";
input [3:0]	or1_raddr	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcs1.ipcc_ipcs_or_raddr";
}

interface siu_sii_check_cnt_dmu_or
{
input		clk		CLOCK		verilog_node "`SII.ipcc.l2clk";
input [4:0]	dmu_or_cnt_r	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.dmu_or_cnt_r";
}

interface siu_sii_check_cnt_dmu_by
{
input		clk		CLOCK		verilog_node "`SII.ipcc.l2clk";
input [4:0]	dmu_by_cnt_r	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.dmu_by_cnt_r";
}

interface siu_sii_check_cnt_niu_or
{
input		clk		CLOCK		verilog_node "`SII.ipcc.l2clk";
input [4:0]	niu_or_cnt_r	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.niu_or_cnt_r";
}

interface siu_sii_check_cnt_niu_by
{
input		clk		CLOCK		verilog_node "`SII.ipcc.l2clk";
input [4:0]	niu_by_cnt_r	INPUT_EDGE	INPUT_SKEW      verilog_node "`SII.ipcc.niu_by_cnt_r";
}

interface siu_sio_commun_dmu_by
{
input		clk				CLOCK		verilog_node "`SIO.opcc.l2clk";
input [2:0]	sio_sii_opcc_ipcc_dmu_by_cnt	INPUT_EDGE	INPUT_SKEW      verilog_node "`SIO.opcc.sio_sii_opcc_ipcc_dmu_by_cnt";
}

interface siu_sio_commun_niu_by
{
input		clk				CLOCK		verilog_node "`SIO.opcc.l2clk";
input [2:0]	sio_sii_opcc_ipcc_niu_by_cnt	INPUT_EDGE	INPUT_SKEW      verilog_node "`SIO.opcc.sio_sii_opcc_ipcc_niu_by_cnt";
}

.for ($q=0; $q<8; $q++)
.{
interface siu_sio_buffer_cnt_ilc${q}
{
input		clk		CLOCK		verilog_node "`SII.ipcc.l2clk";
input [2:0]	sio_cnt_r	INPUT_EDGE	INPUT_SKEW      verilog_node "`SII.ilc${q}.sio_cnt_r";
}
.}

interface siu_ipcc_wrm_cnt
{
input		clk		CLOCK		verilog_node "`SII.ipcc.l2clk";
input [3:0]	dmu_wrm_cnt_r	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.dmu_wrm_cnt_r";
}

.for ($q=0; $q<8; $q++)
.{
interface siu_ilc${q}_wrm_cnt
{
input		clk		CLOCK		verilog_node "`SII.ipcc.l2clk";
input [2:0]	wrm_cnt_r	INPUT_EDGE	INPUT_SKEW      verilog_node "`SII.ilc${q}.wrm_cnt_r";
}
.}

.for ($q=0; $q<8; $q++)
.{
interface siu_ilc${q}_state_machine
{
input		clk		CLOCK		verilog_node "`SII.ilc${q}.l2clk";
input [5:0]	cstate  	INPUT_EDGE	INPUT_SKEW      verilog_node "`SII.ilc${q}.cstate";
}
.}

interface siu_ipcc_state_machine
{
input		clk		CLOCK		verilog_node "`SII.ipcc.l2clk";
input [13:0]	cstate		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.cstate";
}

interface siu_inc_state_machine
{
input		clk		CLOCK		verilog_node "`SII.inc.l2clk";
input [4:0]	cstate		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.inc.cstate";
}

.for ($q=0; $q<2; $q++)
.{
interface siu_ipcs${q}_state_machine
{
input		clk		CLOCK		verilog_node "`SII.ipcs${q}.iol2clk";
input [6:0]	cstate  	INPUT_EDGE	INPUT_SKEW      verilog_node "`SII.ipcs${q}.cstate";
}
.}

.for ($q=0; $q<2; $q++)
.{
interface siu_opcs${q}_state_machine
{
input		clk		CLOCK		verilog_node "`SIO.opcs${q}.iol2clk";
input [7:0]	cstate		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.opcs${q}.cstate";
}
.}

interface siu_coverage_ipcs_order
{
input		clk		CLOCK		verilog_node "`SII.ipcs0.iol2clk";
input [3:0]	young0_match	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcs0.youngest_match";
input [3:0]	young0_dep	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcs0.youngest_dep";
input [3:0]	young1_match	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcs1.youngest_match";
input [3:0]	young1_dep	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcs1.youngest_dep";
}


interface siu_coverage_ipcc_arb
{
input		clk		CLOCK		verilog_node "`SII.ipcc.l2clk";
input		niu_by_go	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.niu_by_go";
input		niu_or_go	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.niu_or_go";
input		dmu_by_go	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.dmu_by_go";
input		dmu_or_go	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.dmu_or_go";
input		tcu_go		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.tcu_go";
}

///
/// SIO
///
.for ($q=0; $q<2; $q++)
.{
interface siu_coverage_opdhq${q}_rd
{
input		clk		CLOCK		verilog_node "`SIO.opdhq${q}.rdclk";

input		rd_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.opdhq${q}.rd_en";
input [3:0]	rd_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.opdhq${q}.rd_adr";
}

interface siu_coverage_opdhq${q}_wr
{
input		clk		CLOCK		verilog_node "`SIO.opdhq${q}.wrclk";

input		wr_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.opdhq${q}.wr_en";
input [3:0]	wr_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.opdhq${q}.wr_adr";
}
.}

.for ($q=0; $q<2; $q++)
.{
.for ($p=0; $p<2; $p++)
.{
interface siu_coverage_opddq${q}${p}_rd
{
input		clk		CLOCK		verilog_node "`SIO.opddq${q}${p}.rdclk";

input		rd_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.opddq${q}${p}.rd_en";
input [5:0]	rd_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.opddq${q}${p}.rd_adr";
}

interface siu_coverage_opddq${q}${p}_wr
{
input		clk		CLOCK		verilog_node "`SIO.opddq${q}${p}.wrclk";

input		wr_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.opddq${q}${p}.wr_en";
input [5:0]	wr_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.opddq${q}${p}.wr_adr";
}
.}
.}

.for ($bank=0; $bank<8; $bank++)
.{
.for ($q=0; $q<2; $q++)
.{
interface siu_coverage_olddq${bank}${q}
{
input		clk		CLOCK		verilog_node "`SIO.olddq${bank}${q}.rdclk";
input           cmp_diag_done	PSAMPLE;

input		wr_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.olddq${bank}${q}.wr_en";
input [4:0]	wr_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.olddq${bank}${q}.wr_adr";
input		rd_en		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.olddq${bank}${q}.rd_en";
input [4:0]	rd_adr		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.olddq${bank}${q}.rd_adr";
}
.}
.}


interface siu_coverage_opcc_arb
{
input		clk		CLOCK		verilog_node "`SIO.l2clk";
input		olc0_req	INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.olc0_opcc_req";
input		olc1_req	INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.olc1_opcc_req";
input		olc2_req	INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.olc2_opcc_req";
input		olc3_req	INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.olc3_opcc_req";
input		olc4_req	INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.olc4_opcc_req";
input		olc5_req	INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.olc5_opcc_req";
input		olc6_req	INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.olc6_opcc_req";
input		olc7_req	INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.olc7_opcc_req";
}

interface siu_coverage_tcu_pkt
{
input           clk            CLOCK            verilog_node "`SII.l2clk";
input		jtag_cov       INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.newhdr_l2[63]";
input[2:0]	tcurdwr	       INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.newhdr_l2[58:56]";
input		tcureq	       INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.tcu_sii_vld";
}

interface siu_coverage_err_det
{
input           clk            CLOCK            verilog_node "`SII.l2clk";
input		cp_err	       INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.cmd_parity_err";
input		ap_err	       INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.addr_parity_err";
input		dp_err	       INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.data_parity_err";
input		cecc_ue	       INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.ctag_ecc_ue";
input		cecc_ce	       INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.ctag_ecc_ce";
input[15:0]	id	       INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.id";
input[5:0]	c	       INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.c";
input[5:0]	e	       INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.e";
input[3:0]	ebits_piortn   INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.sii_ncu_data[31:28]";
input[5:0]	err_sig_l      INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.err_sig_l";
input		sending_r      INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.ipcc.sending_r";
}
// *****************************************************************************************************
// Interface for SIU internal coverage obj for FC
// *****************************************************************************************************

.for ($q=0; $q<2; $q++)
.{
interface siu_coverage_opcs${q}_err
{
input           clk            CLOCK            verilog_node "`SIO.l2clk";
input           ctag_ue        INPUT_EDGE       INPUT_SKEW      verilog_node "`SIO.opcs${q}.myctag_ue"; 
input           ctag_ce        INPUT_EDGE       INPUT_SKEW      verilog_node "`SIO.opcs${q}.myctag_ce"; 
input[5:0]      e              INPUT_EDGE       INPUT_SKEW      verilog_node "`SIO.opcs${q}.e"; 
input[15:0]	id	       INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.opcs${q}.id";
}
.}

.for ($bank=0; $bank<8; $bank++)
.{
.for ($q=0; $q<2; $q++)
.{
interface sio_fifo_depth_olddq${bank}${q}
{ 
input           clk             CLOCK                           verilog_node "`SIO.olddq${bank}${q}.rdclk";
input           wr_en           INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.olddq${bank}${q}.wr_en";
input [4:0]     wr_adr          INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.olddq${bank}${q}.wr_adr";
input           rd_en           INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.olddq${bank}${q}.rd_en";
input [4:0]     rd_adr          INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.olddq${bank}${q}.rd_adr";
} 
.}
        
interface sii_fifo_depth_ildq${bank}
{
input           clk             CLOCK                           verilog_node "`SII.ildq${q}.rdclk";
input           wr_en           INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.ildq${q}.wr_en";
input [4:0]     wr_adr          INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.ildq${q}.wr_adr";
input           rd_en           INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.ildq${q}.rd_en";
input [4:0]     rd_adr          INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.ildq${q}.rd_adr";
}       
.}      

interface l2b_to_sio_UEs
{
input           clk             CLOCK                           verilog_node "`SII.l2clk";
.for ($bank=0; $bank<8; $bank++)
.{
input           l2b${bank}_to_sio_ue_err	INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.l2b${bank}_sio_ue_err";
input [31:0]    l2b${bank}_to_sio_data 		INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.l2b${bank}_sio_data";
input           l2b${bank}_to_sio_ctag_vld	INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.l2b${bank}_sio_ctag_vld";
.}
}

interface siu_ncu_ctag_ce
{
input           clk             CLOCK                           		verilog_node "`SII.iol2clk";
input           sii_ncu_niuctag_ce		INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.sii_ncu_niuctag_ce";
input           sii_ncu_dmuctag_ce		INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.sii_ncu_dmuctag_ce";
input           sio_ncu_ctag_ce			INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.sio_ncu_ctag_ce";
}

#endif