// ========== Copyright Header Begin ========================================== // // OpenSPARC T2 Processor File: siu_ildq5_wr_sample.vrhpal // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved // 4150 Network Circle, Santa Clara, California 95054, U.S.A. // // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; version 2 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // // For the avoidance of doubt, and except that if any non-GPL license // choice is available it will apply instead, Sun elects to use only // the General Public License version 2 (GPLv2) at this time for any // software where a choice of GPL license versions is made // available with the language indicating that GPLv2 or any later version // may be used, or where a choice of which version of the GPL is applied is // otherwise unspecified. // // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, // CA 95054 USA or visit www.sun.com if you need additional information or // have any questions. // // ========== Copyright Header End ============================================ sample siu_coverage_ildq5.wr_adr { state s_ILDQ5_FULL (0:31) if (ildq5_size == 32); state s_ILDQ5_BACK_TO_BACK_WR (0:31) if (ildq5_wr_b2b == 1); trans t_ILDQ5_WR_ADR_00 ( 0 -> 1); trans t_ILDQ5_WR_ADR_01 ( 1 -> 2); trans t_ILDQ5_WR_ADR_02 ( 2 -> 3); trans t_ILDQ5_WR_ADR_03 ( 3 -> 4); trans t_ILDQ5_WR_ADR_04 ( 4 -> 5); trans t_ILDQ5_WR_ADR_05 ( 5 -> 6); trans t_ILDQ5_WR_ADR_06 ( 6 -> 7); trans t_ILDQ5_WR_ADR_07 ( 7 -> 8); trans t_ILDQ5_WR_ADR_08 ( 8 -> 9); trans t_ILDQ5_WR_ADR_09 ( 9 -> 10); trans t_ILDQ5_WR_ADR_10 (10 -> 11); trans t_ILDQ5_WR_ADR_11 (11 -> 12); trans t_ILDQ5_WR_ADR_12 (12 -> 13); trans t_ILDQ5_WR_ADR_13 (13 -> 14); trans t_ILDQ5_WR_ADR_14 (14 -> 15); trans t_ILDQ5_WR_ADR_15 (15 -> 16); trans t_ILDQ5_WR_ADR_16 (16 -> 17); trans t_ILDQ5_WR_ADR_17 (17 -> 18); trans t_ILDQ5_WR_ADR_18 (18 -> 19); trans t_ILDQ5_WR_ADR_19 (19 -> 20); trans t_ILDQ5_WR_ADR_20 (20 -> 21); trans t_ILDQ5_WR_ADR_21 (21 -> 22); trans t_ILDQ5_WR_ADR_22 (22 -> 23); trans t_ILDQ5_WR_ADR_23 (23 -> 24); trans t_ILDQ5_WR_ADR_24 (24 -> 25); trans t_ILDQ5_WR_ADR_25 (25 -> 26); trans t_ILDQ5_WR_ADR_26 (26 -> 27); trans t_ILDQ5_WR_ADR_27 (27 -> 28); trans t_ILDQ5_WR_ADR_28 (28 -> 29); trans t_ILDQ5_WR_ADR_29 (29 -> 30); trans t_ILDQ5_WR_ADR_30 (30 -> 31); trans t_ILDQ5_WR_ADR_31 (31 -> 0); }