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// 
// OpenSPARC T2 Processor File: siu_ipcc_wrm_cnt_sample.vrhpal
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sample siu_ipcc_wrm_cnt.dmu_wrm_cnt_r
{


trans t_SII_IPCC_ADR_00 	( 0 ->  1);
trans t_SII_IPCC_ADR_01 	( 1 ->  2);
trans t_SII_IPCC_ADR_02 	( 2 ->  3);
trans t_SII_IPCC_ADR_03 	( 3 ->  4);
trans t_SII_IPCC_ADR_04 	( 4 ->  5);
trans t_SII_IPCC_ADR_05 	( 5 ->  6);
trans t_SII_IPCC_ADR_06 	( 6 ->  7);
trans t_SII_IPCC_ADR_07 	( 7 ->  8);

}