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// 
// OpenSPARC T2 Processor File: siu_l2intf_cmd_sample.vrhpal
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#inc "siu_cov_inc.pal";

#ifndef SIU_INTF_COV
. for ($bank=0; $bank<8; $bank++)
. {
    sample siu_l2intf_bank${bank}_cmd_sample_this (this_l2${bank}_cmd)
                                     // <5:3>=O-P-S; 
	   		             // <2:0>= 001->RDD; 010->WR8; 100->WRI
    {
      state DMU_RDD_ord_npt	    ( 6'b101001 );
      state DMU_WR8_ord_pst         ( 6'b111010 );
      state DMU_WRI_pst_ord         ( 6'b111100 );

      state NIU_RDD_ord_npt         ( 6'b100001 );
      state NIU_RDD_byp_npt         ( 6'b000001 );

      state NIU_WRI_ord_npt         ( 6'b100100 );
      state NIU_WRI_byp_npt         ( 6'b000100 );

      state NIU_WRI_ord_pst         ( 6'b110100 );
      state NIU_WRI_byp_pst         ( 6'b010100 );
      cov_weight = 0;
    }

    sample siu_l2intf_bank${bank}_cmd_sample_last (last_l2${bank}_cmd)
    {
      state DMU_RDD_ord_npt_last    ( 6'b101001 ) if (l2${bank}_back_to_back==1'b1);
      state DMU_WR8_ord_pst_last    ( 6'b111010 ) if (l2${bank}_back_to_back==1'b1);
      state DMU_WRI_pst_ord_last    ( 6'b111100 ) if (l2${bank}_back_to_back==1'b1);

      state NIU_RDD_ord_npt_last    ( 6'b100001 ) if (l2${bank}_back_to_back==1'b1);
      state NIU_RDD_byp_npt_last    ( 6'b000001 ) if (l2${bank}_back_to_back==1'b1);

      state NIU_WRI_ord_npt_last    ( 6'b100100 ) if (l2${bank}_back_to_back==1'b1);
      state NIU_WRI_byp_npt_last    ( 6'b000100 ) if (l2${bank}_back_to_back==1'b1);

      state NIU_WRI_ord_pst_last    ( 6'b110100 ) if (l2${bank}_back_to_back==1'b1);
      state NIU_WRI_byp_pst_last    ( 6'b010100 ) if (l2${bank}_back_to_back==1'b1);

      cov_weight = 0;

    }

  cross l2siu_intf_bank${bank}_cross ( siu_l2intf_bank${bank}_cmd_sample_last, siu_l2intf_bank${bank}_cmd_sample_this);

. }

#else

// FC
. for ($bank=0; $bank<8; $bank++)
. {
    sample siu_l2intf_bank${bank}_cmd_sample_this (this_l2${bank}_cmd)
                                     // <5:3>=O-P-S;
                                     // <2:0>= 001->RDD; 010->WR8; 100->WRI
    {
      state DMU_RDD_ord_npt         ( 6'b101001 );
      state DMU_WR8_ord_pst         ( 6'b111010 );
      state DMU_WRI_pst_ord         ( 6'b111100 );

      state NIU_RDD_byp_npt         ( 6'b000001 );
      state NIU_WRI_ord_npt         ( 6'b100100 );
      state NIU_WRI_byp_pst         ( 6'b010100 );
    }

    sample siu_l2intf_bank${bank}_cmd_sample_last (last_l2${bank}_cmd)
    {
      state DMU_RDD_ord_npt_last    ( 6'b101001 ) if (l2${bank}_back_to_back==1'b1);
      state DMU_WR8_ord_pst_last    ( 6'b111010 ) if (l2${bank}_back_to_back==1'b1);
      state DMU_WRI_pst_ord_last    ( 6'b111100 ) if (l2${bank}_back_to_back==1'b1);

      state NIU_RDD_byp_npt_last    ( 6'b000001 ) if (l2${bank}_back_to_back==1'b1);
      state NIU_WRI_ord_npt_last    ( 6'b100100 ) if (l2${bank}_back_to_back==1'b1);
      state NIU_WRI_byp_pst_last    ( 6'b010100 ) if (l2${bank}_back_to_back==1'b1);

      cov_weight = 0;

    }
. }

  cross l2siu_intf_bank0_cross ( siu_l2intf_bank0_cmd_sample_last, siu_l2intf_bank0_cmd_sample_this);
#endif