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// 
// OpenSPARC T2 Processor File: siu_opdhq0_wr_sample.vrhpal
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sample siu_coverage_opdhq0_wr.wr_adr
{
	state s_OPDHQ0_RD_WR		(0:15)	if ( siu_coverage_opdhq0_rd.rd_en === 1'b1 );

	trans t_OPDHQ0_WR_ADR_00 	(4'b0000 -> 4'b0001);
	trans t_OPDHQ0_WR_ADR_01 	(4'b0001 -> 4'b0010);
	trans t_OPDHQ0_WR_ADR_02 	(4'b0010 -> 4'b0011);
	trans t_OPDHQ0_WR_ADR_03 	(4'b0011 -> 4'b0100);
	trans t_OPDHQ0_WR_ADR_04 	(4'b0100 -> 4'b0101);
	trans t_OPDHQ0_WR_ADR_05 	(4'b0101 -> 4'b0110);
	trans t_OPDHQ0_WR_ADR_06 	(4'b0110 -> 4'b0111);
	trans t_OPDHQ0_WR_ADR_07 	(4'b0111 -> 4'b1000);
	trans t_OPDHQ0_WR_ADR_08 	(4'b1000 -> 4'b1001);
	trans t_OPDHQ0_WR_ADR_09 	(4'b1001 -> 4'b1010);
	trans t_OPDHQ0_WR_ADR_10 	(4'b1010 -> 4'b1011);
	trans t_OPDHQ0_WR_ADR_11 	(4'b1011 -> 4'b1100);
	trans t_OPDHQ0_WR_ADR_12 	(4'b1100 -> 4'b1101);
	trans t_OPDHQ0_WR_ADR_13 	(4'b1101 -> 4'b1110);
	trans t_OPDHQ0_WR_ADR_14 	(4'b1110 -> 4'b1111);
	trans t_OPDHQ0_WR_ADR_15 	(4'b1111 -> 4'b0000);

// bad state
	bad_state s_OPDHQ0_BACK_TO_BACK_WR	(0:15)	if ( opdhq0_wr_b2b == 1 );
	bad_state s_OPDHQ0_FULL		(0:15)	if ( opdhq0_size == 16 );

}