// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: baseAsmToVeraIntf.vrh
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
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// ========== Copyright Header End ============================================
#ifndef INC__TMP_BASEASMTOVERAINTF_VRH
#define INC__TMP_BASEASMTOVERAINTF_VRH


extern virtual class BaseAsmToVeraIntf { 
  task generic_ev(
    string     arg1_str,
    reg [63:0] arg2_64bits,
    reg [63:0] arg3_64bits
  );
  task intp (
    reg [5:0] tid = 0,
    reg [63:0] type = 0,
    reg [63:0] vec = 0,
    integer src = 16,
    integer wait = 0
  );
  task dump_mem (
    reg [63:0] addr = 0,
    integer amount = 8
  );
  task extint (
    integer wait = 0,
    integer width = 0
  );
  task warmrst (
    integer wait = 0
  );
  task cpx_stall (
    reg [7:0] ccxPortMask = 0,
    integer length = 0,
    integer wait = 0
  );
  task store (
    reg [7:0] ccxPortMask = 0,
    reg [63:0] addr = 0,
    reg [63:0] data = 0
  );

//for counting traps taken in random
  task L2ErrTrapCount(reg [8:0] count=0);


  //random Error Injection in CCM: L2 Data Array
  task L2DAErrInjection(integer injectErr=0);
  
  //random Error Injection in CCM: L2 TAG Array
  task L2TAErrInjection(integer errorinject=0);
 
  task siuDmaRd(reg [63:0] addr=0,
                integer amount=0);

  task siuDmaWri(reg [63:0] addr=0,
                 integer amount=0);

  task siuDmaWr8(reg [63:0] addr=0,
                 reg [63:0] data=0,
                 reg [63:0] size=0);

  task jtagRdWrL2(reg [63:0] paAddr=0,
                  reg [63:0] data=0,
                  reg [63:0] jtagDoneAddrMem=0,
                  reg rdwr=0);

  task IosErrInj (string errtype, bit [15:0] ctag, bit [39:0] pa);
  task IosRandErrInj (string errtype, integer num_errs, integer weight);
 
  task pktGenConfig(integer mac_port, integer frame_type, integer frame_class, integer data_length,
                    (integer tx_multi_port = 0, integer data_length_p1 = -1));

  task NIU_SetTxRingKick (integer mac_port, integer dma_no,
                          (integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0));

  task NIU_AddTxChannels (integer mac_port, integer dma_no,
                          (integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0));

  task NIU_SetTxMaxBurst (integer mac_port, integer dma_no, integer SetTxMaxBurst_Data,
                          (integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0));

  task NIU_TxDMAActivate (integer mac_port, integer dma_activelist,
                          (integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0));

  task NIU_InitTxDma (integer mac_port, integer dma_no, bit Xlate,
                      (integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0));
   
  task NIU_EXIT_chk (integer mac_port);

  task TxPktGen (integer mac_port, integer dmaport, integer numofpacket,
                 (integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0));

  task NIU_InitRxDma (integer RxDmaChnlNo, 
                      integer RxDescRingLen, 
                      bit [39:0] RxRingStartAddr, 
                      bit [63:0] RbrConfData, 
                      integer RxInitKick, 
                      bit Xlate, 
                      (bit [15:0] rx_multi_dma = 16'h0));

  task NIU_RxPktConf (integer RxPktCnt, (integer iport = 0));

  task NIU_RxGenPkt (integer mac_port, 
                     integer RxDmaChnlNo, 
                     integer RxPktCnt, 
                     integer RxPktLen, 
                     (integer rx_multi_PORT=0, bit [15:0] rx_multi_DMA= 16'h0));

  task errCpxPkt(reg [2:0] tid,
                 reg [3:0] type,
                 reg [1:0] errBits,
                 reg [1:0] ifill2 = 0,
                 reg [63:0] addr = 64'hffffffffffffffff,
                 reg ncValue=0);
  
  
  task IC_hard_err_inj(reg [3:0] err_type,
                       reg [48:0] va,
                       reg [2:0] way=0,
                       reg [7:0] tid=~0);

  task DC_hard_err_inj(reg [3:0] err_type,
                       reg [6:0] index,
                       reg [1:0] way=0,
                       reg [7:0] tid=~0);

  task DTLB_err_enable(bit [2:0] err_type=~0,
                       integer err_freq=-1,
                       bit [1:0] merr=~0,
                       integer burst_len=-1,
                       integer burst_freq=-1,
                       bit [7:0] tid=~0);

  task ITLB_err_enable(bit [2:0] err_type=~0,
                       integer err_freq=-1,
                       bit [1:0] merr=~0,
                       integer burst_len=-1,
                       integer burst_freq=-1,
                       bit [7:0] tid=~0);

  task DC_err_enable(bit [3:0] err_type=~0,
                       integer err_freq=-1,
                       bit [1:0] merr=~0,
                       integer burst_len=-1,
                       integer burst_freq=-1,
                       bit [7:0] tid=~0);

  task STB_err_enable(bit [4:0] err_type=~0,
                       integer err_freq=-1,
                       bit [1:0] merr=~0,
                       integer burst_len=-1,
                       integer burst_freq=-1,
                       bit [1:0] ue_en=~0,
                       integer ce_wt=-1,
                       bit [7:0] tid=~0);

  task L2C_err_enable(bit [5:0] err_type=~0,
                       integer err_freq=-1,
                       integer ce_wt=-1,
                       integer nd_wt=-1,
                       integer burst_len=-1,
                       integer burst_freq=-1,
                       bit [7:0] tid=~0);

  task IRF_err_enable(bit [2:0] err_type=~0,
                       integer err_freq=-1,
                       integer ce_wt=-1,
                       reg [1:0] merr=~0,
                       integer burst_len=-1,
                       integer burst_freq=-1,
                       bit [7:0] tid=~0);

  task FRF_err_enable(bit [2:0] err_type=~0,
                       integer err_freq=-1,
                       integer ce_wt=-1,
                       reg [1:0] merr=~0,
                       integer burst_len=-1,
                       integer burst_freq=-1,
                       bit [7:0] tid=~0);


  task MRA_err_enable(bit [1:0] err_type=~0,
                       integer err_freq=-1,
                       reg [7:0] mra_entry=~0,
                       reg [1:0] wr_en=~0,
                       integer burst_len=-1,
                       integer burst_freq=-1,
                       bit [7:0] tid=~0);

  task SCA_err_enable(integer err_freq=-1,
                       integer ce_wt=-1,
                       integer burst_len=-1,
                       integer burst_freq=-1,
                       bit [7:0] tid=~0);

  task TSA_err_enable(bit [1:0] err_type=~0,
                       integer err_freq=-1,
                       reg [6:0] tsa_entry=~0,
                       reg [1:0] wr_en=~0,
                       integer ce_wt=-1,
                       integer burst_len=-1,
                       integer burst_freq=-1,
                       bit [7:0] tid=~0);

  task TCC_err_enable(bit [1:0] err_type=~0,
                       integer err_freq=-1,
                       integer ce_wt=-1,
                       integer burst_len=-1,
                       integer burst_freq=-1,
                       bit [7:0] tid=~0);

  task IC_err_enable(bit [3:0] err_type=~0,
                       integer err_freq=-1,
                       bit [1:0] merr=~0,
                       integer burst_len=-1,
                       integer burst_freq=-1,
                       bit [7:0] tid=~0);

  task registerSlam(string registerName,
                    reg[127:0] value,
                    reg[63:0] tidMask);
  
  task marker(string what, reg [5:0] fromTid, reg [63:0] pc);

  task reset_now(string what);


  task set_StartPEUTest ();

  task EnablePCIeEgCmd (string cmdType,
                        bit [63:0] addr,
                        bit [31:0] txLen,
                        bit [31:0] startData,
                        string err);

  task EnablePCIeIgCmd (string cmdType,
                        bit [63:0] StartAddr,
                        bit [63:0] EndAddr,
                        //                        bit [31:0] txLen,
                        string txLen,
                        bit [31:0] NumCmdss,
                        string err);


  task watchDebugReg(integer which, integer wait=0,
                       reg verbose=0, reg [1:0] checkValue);

  task spc_warm_reset();


}

#endif