// ========== Copyright Header Begin ========================================== // // OpenSPARC T2 Processor File: siu_ncu_mondo.if.vrh // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved // 4150 Network Circle, Santa Clara, California 95054, U.S.A. // // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; version 2 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // // For the avoidance of doubt, and except that if any non-GPL license // choice is available it will apply instead, Sun elects to use only // the General Public License version 2 (GPLv2) at this time for any // software where a choice of GPL license versions is made // available with the language indicating that GPLv2 or any later version // may be used, or where a choice of which version of the GPL is applied is // otherwise unspecified. // // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, // CA 95054 USA or visit www.sun.com if you need additional information or // have any questions. // // ========== Copyright Header End ============================================ #ifndef INC__SIU_NCU_MONDO_IF_VRH #define INC__SIU_NCU_MONDO_IF_VRH /////////////////////////////////////////////////////////////////////////// #include "top_defines.vrh" ///////////// mondo ncu and ssi/dmu interface ////////////////////// interface mondo_ncu_if { input iol2clk CLOCK verilog_node "`CPU.ncu.iol2clk"; input sii_ncu_req PSAMPLE INPUT_SKEW verilog_node "`CPU.ncu.sii_ncu_req"; input [31:0] sii_ncu_data PSAMPLE INPUT_SKEW verilog_node "`CPU.ncu.sii_ncu_data"; input ncu_sii_gnt PSAMPLE INPUT_SKEW verilog_node "`CPU.ncu.ncu_sii_gnt"; input ncu_dmu_mondo_ack PSAMPLE INPUT_SKEW verilog_node "`CPU.ncu.ncu_dmu_mondo_ack"; input ncu_dmu_mondo_nack PSAMPLE INPUT_SKEW verilog_node "`CPU.ncu.ncu_dmu_mondo_nack"; input [5:0] ncu_dmu_mondo_id PSAMPLE INPUT_SKEW verilog_node "`CPU.ncu.ncu_dmu_mondo_id"; } #endif