// ========== Copyright Header Begin ========================================== // // OpenSPARC T2 Processor File: niu_intr_mon.if.vri // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved // 4150 Network Circle, Santa Clara, California 95054, U.S.A. // // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; version 2 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // // For the avoidance of doubt, and except that if any non-GPL license // choice is available it will apply instead, Sun elects to use only // the General Public License version 2 (GPLv2) at this time for any // software where a choice of GPL license versions is made // available with the language indicating that GPLv2 or any later version // may be used, or where a choice of which version of the GPL is applied is // otherwise unspecified. // // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, // CA 95054 USA or visit www.sun.com if you need additional information or // have any questions. // // ========== Copyright Header End ============================================ #ifdef NIU_GATE // Do nothing #else #ifndef NIU_INT_IF #define NIU_INT_IF #define OUTPUT_EDGE PHOLD #define INPUT_EDGE PSAMPLE #-1 #define OUTPUT_SKEW #1 #define NIU_PIO_IC_PATH NIU_DUV_PATH.rdp.niu_pio.niu_pio_ic #define NIU_PIO NIU_DUV_PATH.rdp.niu_pio interface int_mon_ports_if { input activate_ig_sm INPUT_EDGE verilog_node NIU_PIO_IC_PATH.niu_pio_ig_sm.activate_ig_sm"; input activate_ig_sm_rel INPUT_EDGE verilog_node NIU_PIO_IC_PATH.niu_pio_ig_sm.activate_ig_sm_rel"; input ibusy INPUT_EDGE verilog_node NIU_PIO.ibusy"; input [63:0] intr_rel_group INPUT_EDGE verilog_node NIU_PIO_IC_PATH.intr_rel_group"; input req_rel_hit_skew0_noibusy INPUT_EDGE verilog_node "niu_intr_monitor.req_rel_hit_skew0_noibusy"; input req_rel_hit_skew1_noibusy INPUT_EDGE verilog_node "niu_intr_monitor.req_rel_hit_skew1_noibusy"; input req_rel_hit_skew2_noibusy INPUT_EDGE verilog_node "niu_intr_monitor.req_rel_hit_skew2_noibusy"; input req_rel_hit_skew3_noibusy INPUT_EDGE verilog_node "niu_intr_monitor.req_rel_hit_skew3_noibusy"; input req_rel_hit_skew4_noibusy INPUT_EDGE verilog_node "niu_intr_monitor.req_rel_hit_skew4_noibusy"; input req_rel_hit_skew5_noibusy INPUT_EDGE verilog_node "niu_intr_monitor.req_rel_hit_skew5_noibusy"; input req_rel_hit_skew0_ibusy INPUT_EDGE verilog_node "niu_intr_monitor.req_rel_hit_skew0_ibusy"; input req_rel_hit_skew1_ibusy INPUT_EDGE verilog_node "niu_intr_monitor.req_rel_hit_skew1_ibusy"; input req_rel_hit_skew2_ibusy INPUT_EDGE verilog_node "niu_intr_monitor.req_rel_hit_skew2_ibusy"; input req_rel_hit_skew3_ibusy INPUT_EDGE verilog_node "niu_intr_monitor.req_rel_hit_skew3_ibusy"; input req_rel_hit_skew4_ibusy INPUT_EDGE verilog_node "niu_intr_monitor.req_rel_hit_skew4_ibusy"; input req_rel_hit_skew5_ibusy INPUT_EDGE verilog_node "niu_intr_monitor.req_rel_hit_skew5_ibusy"; input rel_req_hit_skew1_noibusy INPUT_EDGE verilog_node "niu_intr_monitor.rel_req_hit_skew1_noibusy"; input rel_req_hit_skew2_noibusy INPUT_EDGE verilog_node "niu_intr_monitor.rel_req_hit_skew2_noibusy"; input rel_req_hit_skew3_noibusy INPUT_EDGE verilog_node "niu_intr_monitor.rel_req_hit_skew3_noibusy"; input rel_req_hit_skew4_noibusy INPUT_EDGE verilog_node "niu_intr_monitor.rel_req_hit_skew4_noibusy"; input rel_req_hit_skew5_noibusy INPUT_EDGE verilog_node "niu_intr_monitor.rel_req_hit_skew5_noibusy"; input rel_req_hit_skew1_ibusy INPUT_EDGE verilog_node "niu_intr_monitor.rel_req_hit_skew1_ibusy"; input rel_req_hit_skew2_ibusy INPUT_EDGE verilog_node "niu_intr_monitor.rel_req_hit_skew2_ibusy"; input rel_req_hit_skew3_ibusy INPUT_EDGE verilog_node "niu_intr_monitor.rel_req_hit_skew3_ibusy"; input rel_req_hit_skew4_ibusy INPUT_EDGE verilog_node "niu_intr_monitor.rel_req_hit_skew4_ibusy"; input rel_req_hit_skew5_ibusy INPUT_EDGE verilog_node "niu_intr_monitor.rel_req_hit_skew5_ibusy"; input req_rel_cov_en INPUT_EDGE verilog_node "niu_intr_monitor.req_rel_cov_en"; input rel_req_cov_en INPUT_EDGE verilog_node "niu_intr_monitor.rel_req_cov_en"; } port int_mon_port { activate_ig_sm; activate_ig_sm_rel; ibusy; intr_rel_group; req_rel_cov_en; rel_req_cov_en; req_rel_hit_skew0_noibusy; req_rel_hit_skew1_noibusy; req_rel_hit_skew2_noibusy; req_rel_hit_skew3_noibusy; req_rel_hit_skew4_noibusy; req_rel_hit_skew5_noibusy; req_rel_hit_skew0_ibusy; req_rel_hit_skew1_ibusy; req_rel_hit_skew2_ibusy; req_rel_hit_skew3_ibusy; req_rel_hit_skew4_ibusy; req_rel_hit_skew5_ibusy; rel_req_hit_skew1_noibusy; rel_req_hit_skew2_noibusy; rel_req_hit_skew3_noibusy; rel_req_hit_skew4_noibusy; rel_req_hit_skew5_noibusy; rel_req_hit_skew1_ibusy; rel_req_hit_skew2_ibusy; rel_req_hit_skew3_ibusy; rel_req_hit_skew4_ibusy; rel_req_hit_skew5_ibusy; } bind int_mon_port int_mon_port_bind { activate_ig_sm int_mon_ports_if.activate_ig_sm; activate_ig_sm_rel int_mon_ports_if.activate_ig_sm_rel; ibusy int_mon_ports_if.ibusy; intr_rel_group int_mon_ports_if.intr_rel_group; req_rel_cov_en int_mon_ports_if.req_rel_cov_en; rel_req_cov_en int_mon_ports_if.rel_req_cov_en; req_rel_hit_skew0_noibusy int_mon_ports_if.req_rel_hit_skew0_noibusy; req_rel_hit_skew1_noibusy int_mon_ports_if.req_rel_hit_skew1_noibusy; req_rel_hit_skew2_noibusy int_mon_ports_if.req_rel_hit_skew2_noibusy; req_rel_hit_skew3_noibusy int_mon_ports_if.req_rel_hit_skew3_noibusy; req_rel_hit_skew4_noibusy int_mon_ports_if.req_rel_hit_skew4_noibusy; req_rel_hit_skew5_noibusy int_mon_ports_if.req_rel_hit_skew5_noibusy; req_rel_hit_skew0_ibusy int_mon_ports_if.req_rel_hit_skew0_ibusy; req_rel_hit_skew1_ibusy int_mon_ports_if.req_rel_hit_skew1_ibusy; req_rel_hit_skew2_ibusy int_mon_ports_if.req_rel_hit_skew2_ibusy; req_rel_hit_skew3_ibusy int_mon_ports_if.req_rel_hit_skew3_ibusy; req_rel_hit_skew4_ibusy int_mon_ports_if.req_rel_hit_skew4_ibusy; req_rel_hit_skew5_ibusy int_mon_ports_if.req_rel_hit_skew5_ibusy; rel_req_hit_skew1_noibusy int_mon_ports_if.rel_req_hit_skew1_noibusy; rel_req_hit_skew2_noibusy int_mon_ports_if.rel_req_hit_skew2_noibusy; rel_req_hit_skew3_noibusy int_mon_ports_if.rel_req_hit_skew3_noibusy; rel_req_hit_skew4_noibusy int_mon_ports_if.rel_req_hit_skew4_noibusy; rel_req_hit_skew5_noibusy int_mon_ports_if.rel_req_hit_skew5_noibusy; rel_req_hit_skew1_ibusy int_mon_ports_if.rel_req_hit_skew1_ibusy; rel_req_hit_skew2_ibusy int_mon_ports_if.rel_req_hit_skew2_ibusy; rel_req_hit_skew3_ibusy int_mon_ports_if.rel_req_hit_skew3_ibusy; rel_req_hit_skew4_ibusy int_mon_ports_if.rel_req_hit_skew4_ibusy; rel_req_hit_skew5_ibusy int_mon_ports_if.rel_req_hit_skew5_ibusy; } #endif // NIU_RXC_IF #endif // if NIU_GATE... else...endif // End