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// 
// OpenSPARC T2 Processor File: niu_intr_util.vr
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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#include "niu_intr_memory_map.vri"
#include "niu_gen_pio.vrh"

#define  TIME {get_time(HI), get_time(LO)}

extern  niu_gen_pio     gen_pio_drv;
extern  Mesg            be_msg;

class niu_intr_util {

  task  new() { }
  task  set_sid_data_function(bit [ 5:0]  gn, bit [1:0] fn);
  task  rearm_arm_bit(bit [ 5:0]  gn);
  task  arm_all_intrs(bit [ 5:0]  timer);

}


// This function sets sid_data[6:5] (function number bits)
// for the passed group number
task niu_intr_util :: set_sid_data_function(bit [ 5:0]  gn, bit [1:0] fn) {
  bit [63:0] wr_data, rd_data;
  bit [31:0] addr;

  addr    = INTR_SID + 8*gn;
  gen_pio_drv.pio_rd(addr, rd_data);
  wr_data = {57'h0, fn, rd_data[4:0]};
  gen_pio_drv.pio_wr(addr, wr_data);
  printf("%d niu_intr_util :: set_sid_data_function addr = %x wr_data = %x \n",TIME, addr, wr_data);
}


// This function polls ARM bit and if it becomes 0
// it will set it back to 1 for the passed GROUP Number
// 

task niu_intr_util :: rearm_arm_bit(bit [ 5:0]  gn){
  bit        exit_loop;
  bit [63:0] wr_data, rd_data;
  bit [31:0] addr;  

  wr_data = 64'h0000_0000_8000_0000; // setting ARM bit (31)
  addr    = PCIE_LDGIMGN + 8192*gn;
  exit_loop = 0;
  while(~exit_loop) {
    gen_pio_drv.pio_rd(addr, rd_data);
    if( (rd_data & wr_data) == 0 ) {
       printf("%d niu_intr_util :: rearm_arm_bit :: ReArming the Arm bit \n", TIME);
       gen_pio_drv.pio_wr(addr, wr_data);
       exit_loop = 1;
      }
  }
}

// This function assigns each device to unique logic device group number
// Enables Mask0 and Mask1
// ARMs all interrupts
// Sets timer resolution to 0
// set the TIMER value to timer
// set SID to unique value starting at 0
task niu_intr_util :: arm_all_intrs(bit [ 5:0]  timer){
  integer     i;
  bit [63:0]  wr_data;
  bit [63:0]  rd_data;    
  bit [31:0]  addr;


  for(i = 0; i < 68; i = i+1) {
    wr_data = i;
    addr    = PCIE_LDG_NUM + 8*i;
    gen_pio_drv.pio_wr(addr, wr_data);
    printf("%d niu_intr_util :: arm_all_intrs  LDG_NUM:: addr = %x wr_data = %x \n",TIME, addr, wr_data);
  }


  wr_data = 64'b0;
  for(i = 0; i < 64; i = i+1) {
    addr    = PIO_IMASK0 + 8192*i;
    gen_pio_drv.pio_wr(addr, wr_data);
    printf("%d niu_intr_util :: arm_all_intrs IMASK0 :: addr = %x wr_data = %x \n",TIME, addr, wr_data);
  }

  wr_data = 64'b0;
  for(i = 0; i < 5; i = i+1) {
    addr    = PIO_IMASK1 + 8192*i;
    gen_pio_drv.pio_wr(addr, wr_data);
    printf("%d niu_intr_util :: arm_all_intrs IMASK1 :: addr = %x wr_data = %x \n",TIME, addr, wr_data);
  }
  // setting ARM bit (31) for all devices
  wr_data = 64'h0000_0000_8000_0000; // setting ARM bit (31)
  wr_data = wr_data + timer;
  for(i = 0; i < 64; i = i+1) {
    addr    = PCIE_LDGIMGN + 8192*i;  
    gen_pio_drv.pio_wr(addr, wr_data);
    printf("%d niu_intr_util :: arm_all_intrs ARM :: addr = %x wr_data = %x \n",TIME, addr, wr_data);
  }

  for(i = 0; i < 64; i = i+1) {
     wr_data = i;
     addr    = INTR_SID + 8*i;
     gen_pio_drv.pio_wr(addr, wr_data);
     printf("%d niu_intr_util :: arm_all_intrs SID :: addr = %x wr_data = %x \n",TIME, addr, wr_data);
  }

}