// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pcg_ports.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
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// ========== Copyright Header End ============================================
#define PCG_MII_IN_TIMING	PSAMPLE
#define PCG_MII_OUT_TIMING	PHOLD #0
#define PCG_MII_CLK_TIMING	CLOCK

#define PCG_GMII_IN_TIMING	PSAMPLE
#define PCG_GMII_OUT_TIMING	PHOLD #0
#define PCG_GMII_CLK_TIMING	CLOCK

#define PCG_XGMII_IN_TIMING	PSAMPLE
#define PCG_XGMII_OUT_TIMING	PHOLD #0
#define PCG_XGMII_CLK_TIMING	CLOCK

interface m0_rx {
	output	[7:0] data	PCG_MII_OUT_TIMING;
	output	crs		PCG_MII_OUT_TIMING;
	output	col		PCG_MII_OUT_TIMING;
	output	dv		PCG_MII_OUT_TIMING;
	output	[3:0] config	PCG_MII_OUT_TIMING;
	output	err		PCG_MII_OUT_TIMING;
	input	clk		PCG_MII_CLK_TIMING;
   }

interface m0_tx {
	input	[7:0] data	PCG_MII_IN_TIMING;
	input	en		PCG_MII_IN_TIMING;
	output	[3:0] config	PCG_MII_OUT_TIMING;
	input	err		PCG_MII_IN_TIMING;
	input	clk		PCG_MII_CLK_TIMING;
   }

interface m1_rx {
	output	[7:0] data	PCG_MII_OUT_TIMING;
	output	crs		PCG_MII_OUT_TIMING;
	output	col		PCG_MII_OUT_TIMING;
	output	dv		PCG_MII_OUT_TIMING;
	output	[3:0] config	PCG_MII_OUT_TIMING;
	output	err		PCG_MII_OUT_TIMING;
	input	clk		PCG_MII_CLK_TIMING;
   }

interface m1_tx {
	input	[7:0] data	PCG_MII_IN_TIMING;
	input	en		PCG_MII_IN_TIMING;
	output	[3:0] config	PCG_MII_OUT_TIMING;
	input	err		PCG_MII_IN_TIMING;
	input	clk		PCG_MII_CLK_TIMING;
   }

interface m2_rx {
	output	[7:0] data	PCG_MII_OUT_TIMING;
	output	crs		PCG_MII_OUT_TIMING;
	output	col		PCG_MII_OUT_TIMING;
	output	dv		PCG_MII_OUT_TIMING;
	output	[3:0] config	PCG_MII_OUT_TIMING;
	output	err		PCG_MII_OUT_TIMING;
	input	clk		PCG_MII_CLK_TIMING;
   }

interface m2_tx {
	input	[7:0] data	PCG_MII_IN_TIMING;
	input	en		PCG_MII_IN_TIMING;
	output	[3:0] config	PCG_MII_OUT_TIMING;
	input	err		PCG_MII_IN_TIMING;
	input	clk		PCG_MII_CLK_TIMING;
   }

interface m3_rx {
	output	[7:0] data	PCG_MII_OUT_TIMING;
	output	crs		PCG_MII_OUT_TIMING;
	output	col		PCG_MII_OUT_TIMING;
	output	dv		PCG_MII_OUT_TIMING;
	output	[3:0] config	PCG_MII_OUT_TIMING;
	output	err		PCG_MII_OUT_TIMING;
	input	clk		PCG_MII_CLK_TIMING;
   }

interface m3_tx {
	input	[7:0] data	PCG_MII_IN_TIMING;
	input	en		PCG_MII_IN_TIMING;
	output	[3:0] config	PCG_MII_OUT_TIMING;
	input	err		PCG_MII_IN_TIMING;
	input	clk		PCG_MII_CLK_TIMING;
   }


port xgmii_def {
	rxd;
        rxcrs;
        rxcol;
        rxdv;
	rxerr;
	rxclk_int;
	txd;
	txen;
	txerr;
	txclk_int;
	rx_config;
	tx_config;

   }

port gmii_def {
	rxd;
	rxcrs;
	rxcol;
	rxdv;
	rxerr;
	rxclk;
	txd;
	txen;
	txerr;
	txclk;
	rx_config;
	tx_config;
   }


port mii_def {
	rxd;
	rxcrs;
	rxcol;
	rxdv;
	rxerr;
	rxclk;
	txd;
	txen;
	txerr;
	txclk;
	rx_config;
	tx_config;
   }



bind mii_def m0 {
        rxd     m0_rx.data;
        rxcrs   m0_rx.crs;
        rxcol   m0_rx.col;
        rxdv    m0_rx.dv;
        rxerr   m0_rx.err;
        rxclk   m0_rx.clk;
        txd     m0_tx.data;
        txen    m0_tx.en;
        txerr   m0_tx.err;
        txclk   m0_tx.clk;
        rx_config       m0_rx.config;
        tx_config       m0_tx.config;
   }

bind mii_def m1 {
        rxd     m1_rx.data;
        rxcrs   m1_rx.crs;
        rxcol   m1_rx.col;
        rxdv    m1_rx.dv;
        rxerr   m1_rx.err;
        rxclk   m1_rx.clk;
        txd     m1_tx.data;
        txen    m1_tx.en;
        txerr   m1_tx.err;
        txclk   m1_tx.clk;
        rx_config       m1_rx.config;
        tx_config       m1_tx.config;
   }

bind mii_def m2 {
        rxd     m2_rx.data;
        rxcrs   m2_rx.crs;
        rxcol   m2_rx.col;
        rxdv    m2_rx.dv;
        rxerr   m2_rx.err;
        rxclk   m2_rx.clk;
        txd     m2_tx.data;
        txen    m2_tx.en;
        txerr   m2_tx.err;
        txclk   m2_tx.clk;
        rx_config       m2_rx.config;
        tx_config       m2_tx.config;
   }


bind mii_def m3 {
        rxd     m3_rx.data;
        rxcrs   m3_rx.crs;
        rxcol   m3_rx.col;
        rxdv    m3_rx.dv;
        rxerr   m3_rx.err;
        rxclk   m3_rx.clk;
        txd     m3_tx.data;
        txen    m3_tx.en;
        txerr   m3_tx.err;
        txclk   m3_tx.clk;
        rx_config       m3_rx.config;
        tx_config       m3_tx.config;
   }




bind gmii_def gm0 {
        rxd     m0_rx.data;
        rxcrs   m0_rx.crs;
        rxcol   m0_rx.col;
        rxdv    m0_rx.dv;
        rxerr   m0_rx.err;
        rxclk   m0_rx.clk;
        txd     m0_tx.data;
        txen    m0_tx.en;
        txerr   m0_tx.err;
        txclk   m0_tx.clk;
        rx_config       m0_rx.config;
        tx_config       m0_tx.config;
   }

bind gmii_def gm1 {
        rxd     m1_rx.data;
        rxcrs   m1_rx.crs;
        rxcol   m1_rx.col;
        rxdv    m1_rx.dv;
        rxerr   m1_rx.err;
        rxclk   m1_rx.clk;
        txd     m1_tx.data;
        txen    m1_tx.en;
        txerr   m1_tx.err;
        txclk   m1_tx.clk;
        rx_config       m1_rx.config;
        tx_config       m1_tx.config;
   }


bind gmii_def gm2 {
        rxd     m2_rx.data;
        rxcrs   m2_rx.crs;
        rxcol   m2_rx.col;
        rxdv    m2_rx.dv;
        rxerr   m2_rx.err;
        rxclk   m2_rx.clk;
        txd     m2_tx.data;
        txen    m2_tx.en;
        txerr   m2_tx.err;
        txclk   m2_tx.clk;
        rx_config       m2_rx.config;
        tx_config       m2_tx.config;
   }


bind gmii_def gm3 {
        rxd     m3_rx.data;
        rxcrs   m3_rx.crs;
        rxcol   m3_rx.col;
        rxdv    m3_rx.dv;
        rxerr   m3_rx.err;
        rxclk   m3_rx.clk;
        txd     m3_tx.data;
        txen    m3_tx.en;
        txerr   m3_tx.err;
        txclk   m3_tx.clk;
        rx_config       m3_rx.config;
        tx_config       m3_tx.config;
   }


bind xgmii_def xgm0 {
	rxd	m0_rx.data;
	rxcrs	m0_rx.crs;
        rxcol   m0_rx.col;
        rxdv    m0_rx.dv;
        rxerr   m0_rx.err;
	rxclk_int	m0_rx.clk;
	txd	m0_tx.data;
	txen	m0_tx.en;
	txerr	m0_tx.err;
	txclk_int	m0_tx.clk;
	rx_config	m0_rx.config;
	tx_config	m0_tx.config;
   }


bind xgmii_def xgm1 {
	rxd	m1_rx.data;
	rxcrs	m1_rx.crs;
        rxcol   m1_rx.col;
        rxdv    m1_rx.dv;
        rxerr   m1_rx.err;
	rxclk_int	m1_rx.clk;
	txd	m1_tx.data;
	txen	m1_tx.en;
	txerr	m1_tx.err;
	txclk_int	m1_tx.clk;
	rx_config	m1_rx.config;
	tx_config	m1_tx.config;
   }