// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: tlb_sync.vh
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`ifdef     INC_TLBSYNC_DEFINE

`else

`define     INC_TLBSYNC_DEFINE

`define ITLB_ENTRIES       64
`define DTLB_ENTRIES      128
`define ITLB_ENTRY_WIDTH    6
`define DTLB_ENTRY_WIDTH    7

// Number of entries in Instruction Buffer
`define IB_DEPTH           10  
`define IB_PTR_WIDTH        4

// Only include err_vect in SPC2 bench
`ifdef SPC
  `define TLB_FIFO_WIDE
`endif

`ifdef TLB_FIFO_WIDE
  // IB entry = {err_vect[7:0],timestamp}
  `define TLB_FIFO_WIDTH            9+`TS_WIDTH
`else
  `define TLB_FIFO_WIDTH            `TS_WIDTH
`endif

`endif

//----------------------------------------------------------