// ========== Copyright Header Begin ========================================== // // OpenSPARC T2 Processor File: fc_common.config // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved // 4150 Network Circle, Santa Clara, California 95054, U.S.A. // // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; version 2 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // // For the avoidance of doubt, and except that if any non-GPL license // choice is available it will apply instead, Sun elects to use only // the General Public License version 2 (GPLv2) at this time for any // software where a choice of GPL license versions is made // available with the language indicating that GPLv2 or any later version // may be used, or where a choice of which version of the GPL is applied is // otherwise unspecified. // // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, // CA 95054 USA or visit www.sun.com if you need additional information or // have any questions. // // ========== Copyright Header End ============================================ #if defined(AXIS_BUILD) || defined(AXIS_COSIM) -vcs_run_args=+dispmon_disable -vera_build_args="NO_0INMGR=1" -config_rtl=AXIS -sunv_args=-keepSectionSym=AXIS_SMEM -sunv_args=-keepSectionSym=EMUL_COSIM -sunv_args=-keepSectionSym=AXIS_EMUL_COSIM -vcs_build_args=+define+DISABLE_TID_CHKR -nouse_oolm -vcs_run_args=+fbdimm_nb_witdh_capability=1f -vcs_build_args=+define+ALL_DUMP_OFF -novcs_use_fsdb #ifndef AXIS_TL -vcs_build_args=-P $VERA_HOME/lib/vera_pli.tab -vcs_build_args=$VERA_HOME/lib/libSysSciTask.a #endif -vcs_build_args="-pl -lsocket -pl -lnsl -pl -lintl -pl -ldl " -vcs_build_args=+v2000 -vcs_build_args=+tran -vcs_build_args=+tran_force -vcs_build_args="-Z $DV_ROOT/verif/model/verilog/mem/dram/axis_sram.v" -axis_build_args=" -scope n2_fc -map_udp " -novcs_use_vcsd #ifndef AXIS_NO_IP -axis_build_args=" -vms_excl delay_n+delay_n_w_stalling+niu_smx_regfl+dmu_common_simple_fifo+fflp_flow_fifo+n2_iom_sp_2048b_cust+n2_iom_sp_1024b_cust" #endif #ifdef AXIS_USE_MC -vcs_build_args=" +mcexcl+dc_panel_array+cmp_sat +mcminsize+64 +rtlmemsize+20000 " #else -axis_build_args=" -no_mc -run_vms " #endif #ifndef AXIS_TL -axis_build_args=" -vms_excl wiz6c2b8n5d2t " #endif -vcs_build_args="-Z $DV_ROOT/verif/env/fc/axis_hacks.v" #endif #ifdef FASTER_AXIS -vcs_build_args=+define+FAST_AXIS #endif #ifdef AXIS_64BIT -vcs_build_args=+vlg64 #endif #ifdef CPU_TGL_COV -vcs_cm_args=tgl -vcs_cm_config=$DV_ROOT/verif/env/fc/fc_cpu_tgl.cm_config #endif #ifdef AXIS_TURNIN #ifdef AXIS_TL -axis_build_args=" -rm_axiswork " -vcs_build_args=+rtlUnsupportedError #endif #endif #ifdef AXIS_COSIM -vcs_build_args=" +rtlIgnPragma +rtlCommentPragma+niu_txc_drr_arbiter " -vcs_build_args="+define+AXIS_SMEM+EMUL_COSIM+AXIS_EMUL_COSIM " -axis_build_args="-hwtype xs -model_type axis_cs -comp_64" -axis_run_args=" -model_type axis_cs " #endif #ifdef AXIS_TL -novcs_use_fsdb -vcs_build_args=+define+FSDB_OFF -axis_run_args="-hwtype xs" -vcs_build_args="+define+AXIS_SMEM+EMUL_COSIM+AXIS_EMUL_COSIM " //-vcs_build_args="-Z $DV_ROOT/verif/env/fc/axis_hacks.v" -vcs_build_args=" $DV_ROOT/verif/env/fc/axis_modules.v" -vcs_build_args="-v $DV_ROOT/verif/env/fc/axis_siu_mon.v" -axis_run_args=-runpresim '"$DV_ROOT/verif/env/mcu/axis_convert -s "' -vcs_build_args=+define+FBDIMM_NUM_1+ -vcs_run_args=+1_FBDIMMS -vcs_run_args=+ddr2_way_err_enable=0 -vcs_run_args=+ddr2_way_warn_enable=1 -vcs_build_args=+define+X4+ -vcs_build_args=+define+AXIS_DDR2_MODEL -vcs_build_args=+define+AXIS_FBDIMM -midas_args=-DPART_0_BASE=0x0 -midas_args=-nocompress_image -vcs_build_args="+dut+tb_top" -vcs_build_args="+define+AXIS_TL +define+ALL_DUMP_OFF " -vcs_build_args="-v $DV_ROOT/verif/env/fc/axis_ccx_mon.v" #ifndef AXIS_NO_IP -vcs_build_args="-Z $DV_ROOT/verif/model/verilog/niu/niu_enet_models/n2_tcam_array.vap" #endif -vcs_build_args=" +rtlCommentPragma " -axis_build_args="-hwtype xs -model_type axis_tl -comp_64" -axis_run_args=" -model_type axis_tl" -vera_build_args=FC_NO_PEU_VERA=1 -vcs_build_args=+incdir+$DV_ROOT/design/esr/esr_l/esr/rtl/ -vcs_build_args="-v $DV_ROOT/verif/env/fc/axis_tlb_mon.v" -vcs_build_args="-v /import/datools/vendor/axis/v2004.4.3/sys/masterLib/trigProc.v" #ifndef AXIS_NO_IP -vcs_build_args=+dut+ept #endif -vcs_build_args=+define+AXIS_FBDIMM_HW -vcs_build_args=+define+USE_JTAG_DRIVER #endif #ifdef AXIS_NO_FSR -vcs_build_args=+define+AXIS_FBDIMM_NO_FSR -vcs_build_args="-Z $DV_ROOT/verif/env/mcu/axis_hack_fsr.v " #ifdef AXIS_TL -vcs_build_args=+dut+no_fsr_for_axis #endif #endif -pal_use_tgseed -config_rtl=MCU -config_rtl=RTL_SPARC0 -config_rtl=RTL_FLOP_RPTRS -config_rtl=RTL_DRAM02 -config_rtl=RTL_DRAM13 -config_rtl=NCURTL -config_rtl=FC_BENCH // Generic define for all core Benches (SPC2,CMPn,CCMn,FCn). Not set in SATs. -config_rtl=CORE_BENCH -config_rtl=ZIN_CORE_SUBSET -vera_build_args="VFLAGS=-DDRAM" -vera_build_args=PAL_OPTS="sys=DRAM" -vera_build_args=NEPTUNE_MODE=N2 -vera_build_args=VERA_SYS_DEFS="-DFC_BENCH -DNCURTL -DN2_FC" -vera_build_args=NEPTUNE_ENV=CDMSPP -vera_config_root=$DV_ROOT/verif -vera_diag_root=$DV_ROOT/verif/diag -drm_disk=[/export/home/bw=30] -drm_type=vcs -drm_freeram=2000 -drm_freeprocessor=1.0 -asm_diag_root=$DV_ROOT/verif/diag -env_base=$DV_ROOT/verif/env/fc -flist=$DV_ROOT/verif/env/common/verilog/misc/misc.flist #ifdef CONFIG_LOADNGO -flist=$DV_ROOT/verif/env/fc/loadngo/fc_loadngo.flist -vcs_build_args=-LDFLAGS -R -LDFLAGS $DV_ROOT/verif/env/fc/loadngo/pli -vcs_build_args=" -L$DV_ROOT/verif/env/fc/loadngo/pli -lloadngo" -vcs_build_args=+vc+abstract -vera_build_args="CONFIG_LOADNGO=1" #endif #ifdef AXIS_BUILD //#ifdef AXIS_TL -flist=$DV_ROOT/verif/env/common/verilog/axis_traps/axis_traps.flist //#else #endif #ifndef AXIS_TL #ifndef PLAYBACK -flist=$DV_ROOT/verif/env/common/verilog/nas_car/nas_car.flist -flist=$DV_ROOT/verif/env/common/verilog/tlb_sync/tlb_sync.flist -flist=$DV_ROOT/verif/env/common/verilog/int_sync/int_sync.flist -flist=$DV_ROOT/verif/env/common/verilog/ldst_sync/ldst_sync.flist -flist=$DV_ROOT/verif/env/common/verilog/err_sync/err_sync.flist #endif // PLAYBACK -flist=$DV_ROOT/verif/env/common/verilog/reg_slam/reg_slam.flist #ifndef GATESIM -flist=$DV_ROOT/verif/env/common/verilog/monitors/monitors_soc.flist -flist=$DV_ROOT/verif/env/common/verilog/err_random/err.flist #ifndef FC_NO_NIU_T2 #ifndef NIU_SYSTEMC_T2 -flist=$DV_ROOT/verif/env/common/verilog/soc_sync/soc_sync.flist.2 #else -flist=$DV_ROOT/verif/env/common/verilog/soc_sync/soc_sync.flist #endif #else -flist=$DV_ROOT/verif/env/common/verilog/soc_sync/soc_sync.flist #endif #endif #endif #ifndef FC_NO_NIU_T2 #ifndef IO_GATE -flist=$DV_ROOT/verif/env/niu/eser_rtl.flist #endif -flist=$DV_ROOT/verif/env/niu/eser_tb.flist -flist=$DV_ROOT/verif/env/fc/fc_niu.flist -flist=$DV_ROOT/verif/env/common/verilog/monitors/monitors.flist #endif #ifdef INPHI_AMB -flist=$DV_ROOT/verif/model/inphi/inphi_amb.flist -flist=$DV_ROOT/verif/model/sun/sun_misc.flist #elif MICRON_AMB -flist=$DV_ROOT/verif/model/micron/micron_amb.flist -flist=$DV_ROOT/verif/model/sun/sun_misc.flist #elif IDT_AMB -flist=$DV_ROOT/verif/model/idt/idt_amb.flist -flist=$DV_ROOT/verif/model/sun/sun_misc.flist // commented this out, replaced with equiv. definition // #define CRC_ERR_INJECTOR -vcs_build_args=+define+FC_CRC_INJECT -flist=$DV_ROOT/verif/env/mcu/fc_crc.flist #elif NEC_AMB -flist=$DV_ROOT/verif/model/nec/nec_amb.flist -flist=$DV_ROOT/verif/model/sun/sun_misc.flist -vcs_build_args=+define+ASSERTS_OFF -vcs_build_args=+nospecify -vcs_build_args=+access+rwc -vcs_build_args=+no_tchkmsg -vcs_build_args=+notimingcheck -vcs_build_args=+libext+.vp+ -vcs_build_args=+warn=noTMR #else -flist=$DV_ROOT/verif/model/sun/sun_amb.flist #endif //#ifdef CRC_ERR_INJECTOR //#ifndef PLAYBACK //-vcs_build_args=+define+FC_CRC_INJECT //-flist=$DV_ROOT/verif/env/mcu/fc_crc.flist //#endif // PLAYBACK //#endif #ifdef NB_BITLANE_DESKEW -vcs_build_args=+define+NB_BITLANE_DESKEW -flist=$DV_ROOT/verif/env/mcu/fc_crc.flist #endif #ifndef PLAYBACK -flist=$DV_ROOT/verif/env/fc/fc.flist #endif // PLAYBACK #ifdef PLAYBACK -flist=$DV_ROOT/verif/env/fc/fc_playback.flist -vcs_build_args=-P $DV_ROOT/verif/env/fc/vectorfile.tab -vcs_build_args=$DV_ROOT/verif/env/fc/libvectorfile.a #endif // PLAYBACK #ifdef FULL_GATE #ifndef PLAYBACK -flist=$DV_ROOT/verif/env/fc/ilu_peu_denali.flist #endif // PLAYBACK -flist=$DV_ROOT/verif/env/fc/fc_gl.flist -flist=$DV_ROOT/verif/env/fc/fc_rptr.flist #endif #ifdef PEU_DMU_GATESIM #ifndef PLAYBACK -flist=$DV_ROOT/verif/env/fc/ilu_peu_denali.flist #endif // PLAYBACK -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.peu+dmu_gate #endif #ifdef CCU_GATESIM -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.ccu_gate #endif #ifdef SUNV_EXCLUDE_CPU -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.cpu_gate -sunv_args=-excludecell=\^cpu #endif #ifdef SUNV_EXCLUDE_CLK_GL_CUST -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.clk_gl_cust_gate -sunv_args=-excludecell=\^n2_clk_gl_cust\$ -sunv_args=-excludecell=\^n2_clk_gl_cmp_tree\$ -sunv_args=-excludecell=\^n2_clk_gl_dr_tree\$ -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_top\$ -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_ccu_m0 -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_rst_m0 -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_tcu_m0 -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_17s1 -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_8s2 -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_4s4 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2b_s1_1 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1t_s1_0 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1t_s4_0 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1t_s4_1 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1t_s4_2 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1t_s1_1 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1b_s4_0 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1b_s4_1 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1b_s4_2 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1b_s4_3 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2b_s1_0 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2b_s2_0 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2b_s2_1 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2t_s1_0 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2t_s2_0 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2t_s2_1 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3t_s1_0 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3t_s1_1 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3t_s1_3 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3t_s1_2 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3b_s1_0 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3b_s1_1 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3b_s1_3 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3b_s1_2 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1b_s1_0 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1b_s1_1 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2t_s1_1 -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_align -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_mcu_dr #endif #ifdef SUNV_EXCLUDE_IO -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.io_gate -sunv_args=-excludecell=\^fsr -sunv_args=-excludecell=\^esr -sunv_args=-excludecell=\^psr -sunv_args=-excludecell=\^mio -sunv_args=-excludecell=\^mio -sunv_args=-excludecell=\^n2_pcm_main_blk #endif #ifdef SUNV_EXCLUDE_MCU -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.mcu_gate -sunv_args=-excludecell=\^mcu #endif #ifdef SUNV_EXCLUDE_NIU -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.niu_gate -sunv_args=-excludecell=\^niu -sunv_args=-excludecell=\^mac -sunv_args=-excludecell=\^rtx -sunv_args=-excludecell=\^rdp -sunv_args=-excludecell=\^tds #endif #ifdef SUNV_EXCLUDE_TCU -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.tcu_gate -sunv_args=-excludecell=\^tcu #endif #ifdef SUNV_EXCLUDE_RST -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.rst_gate -sunv_args=-excludecell=\^rst #endif #ifdef SUNV_EXCLUDE_EFU -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.efu_gate -sunv_args=-excludecell=\^efu #endif #ifdef SUNV_EXCLUDE_SII_SIO -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.sii+sio_gate -sunv_args=-excludecell=\^sii\$ -sunv_args=-excludecell=\^sii_ilc_ctl\$ -sunv_args=-excludecell=\^sii_ild_dp\$ -sunv_args=-excludecell=\^sii_inc_ctl\$ -sunv_args=-excludecell=\^sii_ipcc_ctl\$ -sunv_args=-excludecell=\^sii_ipcc_dp\$ -sunv_args=-excludecell=\^sii_ipcs_ctl\$ -sunv_args=-excludecell=\^sii_mb0_ctl\$ -sunv_args=-excludecell=\^sii_mb1_ctl\$ -sunv_args=-excludecell=\^sii_stgsio_dp\$ -sunv_args=-excludecell=\^sio\$ -sunv_args=-excludecell=\^sio_mb0_ctl\$ -sunv_args=-excludecell=\^sio_mb1_ctl\$ -sunv_args=-excludecell=\^sio_mbist_ctl\$ -sunv_args=-excludecell=\^sio_olc_ctl\$ -sunv_args=-excludecell=\^sio_old_dp\$ -sunv_args=-excludecell=\^sio_old_rf_cust\$ -sunv_args=-excludecell=\^sio_opcc_ctl\$ -sunv_args=-excludecell=\^sio_opcs_ctl\$ -sunv_args=-excludecell=\^sio_opd_data_rf_cust\$ -sunv_args=-excludecell=\^sio_opd_hdr_rf_cust\$ -sunv_args=-excludecell=\^sio_opdc_dp\$ -sunv_args=-excludecell=\^sio_opds_dp\$ -sunv_args=-excludecell=\^sio_stg1_dp\$ -sunv_args=-excludecell=\^sio_stg2_dp\$ #endif #ifdef SUNV_EXCLUDE_SPC -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.spc_gate // exclude spc -sunv_args=-excludecell=\^spc\$ -sunv_args=-excludecell=\^spc_msf0_dp\$ -sunv_args=-excludecell=\^spc_msf1_dp\$ -sunv_args=-excludecell=\^spc_lb_ctl\$ -sunv_args=-excludecell=\^clkgen_spc_cmp\$ -sunv_args=-excludecell=\^dmo_dp\$ -sunv_args=-excludecell=\^gkt\$ -sunv_args=-excludecell=\^fgu\$ -sunv_args=-excludecell=\^ifu_ibu\$ -sunv_args=-excludecell=\^ifu_ftu\$ -sunv_args=-excludecell=\^ifu_cmu\$ -sunv_args=-excludecell=\^dec\$ -sunv_args=-excludecell=\^pku\$ -sunv_args=-excludecell=\^exu\$ -sunv_args=-excludecell=\^tlu\$ -sunv_args=-excludecell=\^lsu\$ -sunv_args=-excludecell=\^spu\$ -sunv_args=-excludecell=\^mmu\$ -sunv_args=-excludecell=\^pmu\$ -sunv_args=-excludecell=\^spc_mb0_ctl\$ -sunv_args=-excludecell=\^spc_mb1_ctl\$ -sunv_args=-excludecell=\^spc_mb2_ctl\$ #endif #ifdef SUNV_EXCLUDE_CCX -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.ccx_gate // exclude ccx -sunv_args=-excludecell=\^ccx\$ -sunv_args=-excludecell=\^cpx\$ -sunv_args=-excludecell=\^pcx\$ #endif #ifdef SUNV_EXCLUDE_L2 -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.l2_gate // exclude l2t -sunv_args=-excludecell=\^l2t\$ -sunv_args=-excludecell=\^l2t_arb_ctl\$ -sunv_args=-excludecell=\^l2t_arbadr_dp\$ -sunv_args=-excludecell=\^l2t_arbdat_dp\$ -sunv_args=-excludecell=\^l2t_arbdec_dp\$ -sunv_args=-excludecell=\^l2t_csr_ctl\$ -sunv_args=-excludecell=\^l2t_csreg_ctl\$ -sunv_args=-excludecell=\^l2t_decc_dp\$ -sunv_args=-excludecell=\^l2t_deccck_ctl\$ -sunv_args=-excludecell=\^l2t_dir_ctl\$ -sunv_args=-excludecell=\^l2t_dirbuf_ctl\$ -sunv_args=-excludecell=\^l2t_dirin_dp\$ -sunv_args=-excludecell=\^l2t_dirlbf_dp\$ -sunv_args=-excludecell=\^l2t_dirout_dp\$ -sunv_args=-excludecell=\^l2t_dirrep_ctl\$ -sunv_args=-excludecell=\^l2t_dirtop_ctl\$ -sunv_args=-excludecell=\^l2t_dirvec_ctl\$ -sunv_args=-excludecell=\^l2t_dirvec_dp\$ -sunv_args=-excludecell=\^l2t_dmo_dp\$ -sunv_args=-excludecell=\^l2t_dmorpt_dp\$ -sunv_args=-excludecell=\^l2t_ecc24b_dp\$ -sunv_args=-excludecell=\^l2t_ecc30b_dp\$ -sunv_args=-excludecell=\^l2t_ecc39_dp\$ -sunv_args=-excludecell=\^l2t_ecc39a_dp\$ -sunv_args=-excludecell=\^l2t_evctag_dp\$ -sunv_args=-excludecell=\^l2t_ffrpt_dp\$ -sunv_args=-excludecell=\^l2t_filbuf_ctl\$ -sunv_args=-excludecell=\^l2t_iqu_ctl\$ -sunv_args=-excludecell=\^l2t_ique_dp\$ -sunv_args=-excludecell=\^l2t_l2brep_dp\$ -sunv_args=-excludecell=\^l2t_l2drpt_dp\$ -sunv_args=-excludecell=\^l2t_mb0_ctl\$ -sunv_args=-excludecell=\^l2t_mb2_ctl\$ -sunv_args=-excludecell=\^l2t_mbist_ctl\$ -sunv_args=-excludecell=\^l2t_misbuf_ctl\$ -sunv_args=-excludecell=\^l2t_mrep16x8_dp\$ -sunv_args=-excludecell=\^l2t_mrep2x64_dp\$ -sunv_args=-excludecell=\^l2t_mrep32x3_dp\$ -sunv_args=-excludecell=\^l2t_mrep4x6_dp\$ -sunv_args=-excludecell=\^l2t_mrep8x16_dp\$ -sunv_args=-excludecell=\^l2t_oqu_ctl\$ -sunv_args=-excludecell=\^l2t_oque_dp\$ -sunv_args=-excludecell=\^l2t_pgen32b_dp\$ -sunv_args=-excludecell=\^l2t_rdmarpt_dp\$ -sunv_args=-excludecell=\^l2t_rdmat_ctl\$ -sunv_args=-excludecell=\^l2t_rep_dp\$ -sunv_args=-excludecell=\^l2t_ret_dp\$ -sunv_args=-excludecell=\^l2t_shdwscn_dp\$ -sunv_args=-excludecell=\^l2t_snp_ctl\$ -sunv_args=-excludecell=\^l2t_snpd_dp\$ -sunv_args=-excludecell=\^l2t_tag_ctl\$ -sunv_args=-excludecell=\^l2t_tagd_dp\$ -sunv_args=-excludecell=\^l2t_tagdp_ctl\$ -sunv_args=-excludecell=\^l2t_taghdr_ctl\$ -sunv_args=-excludecell=\^l2t_tagl_dp\$ -sunv_args=-excludecell=\^l2t_usaloc_dp\$ -sunv_args=-excludecell=\^l2t_vlddir_dp\$ -sunv_args=-excludecell=\^l2t_vuad_ctl\$ -sunv_args=-excludecell=\^l2t_vuad_dp\$ -sunv_args=-excludecell=\^l2t_vuadcl_dp\$ -sunv_args=-excludecell=\^l2t_vuaddp_ctl\$ -sunv_args=-excludecell=\^l2t_vuadio_dp\$ -sunv_args=-excludecell=\^l2t_vuadpm_dp\$ -sunv_args=-excludecell=\^l2t_wbuf_ctl\$ -sunv_args=-excludecell=\^l2t_wbufrpt_dp\$ // exclude l2b -sunv_args=-excludecell=\^l2b #endif #ifdef SUNV_EXCLUDE_DB -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.db_gate // exclude db0 -sunv_args=-excludecell=\^db0\$ -sunv_args=-excludecell=\^db0_red_dp\$ -sunv_args=-excludecell=\^db0_reduct_ctl\$ -sunv_args=-excludecell=\^db0_rtc_dp\$ // exclude db1 -sunv_args=-excludecell=\^db1\$ -sunv_args=-excludecell=\^db1_csr_ctl\$ -sunv_args=-excludecell=\^db1_dbgprt_dp\$ -sunv_args=-excludecell=\^db1_ucbbusin4_ctl\$ -sunv_args=-excludecell=\^db1_ucbbusout4_ctl\$ -sunv_args=-excludecell=\^db1_ucbflow_ctl\$ #endif #ifdef SUNV_EXCLUDE_NCU -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.ncu_gate -sunv_args=-excludecell=\^ncu\$ -sunv_args=-excludecell=\^ncu_c2ibuf32_ctl\$ -sunv_args=-excludecell=\^ncu_c2ibuf4_ctl\$ -sunv_args=-excludecell=\^ncu_c2ibufpio_ctl\$ -sunv_args=-excludecell=\^ncu_c2ifc_ctl\$ -sunv_args=-excludecell=\^ncu_c2ifcd_ctl\$ -sunv_args=-excludecell=\^ncu_c2ifd_ctl\$ -sunv_args=-excludecell=\^ncu_c2isc_ctl\$ -sunv_args=-excludecell=\^ncu_c2iscd_ctl\$ -sunv_args=-excludecell=\^ncu_c2isd_ctl\$ -sunv_args=-excludecell=\^ncu_ctrl_ctl\$ -sunv_args=-excludecell=\^ncu_eccchk11_ctl\$ -sunv_args=-excludecell=\^ncu_eccchk16_ctl\$ -sunv_args=-excludecell=\^ncu_eccchk6_ctl\$ -sunv_args=-excludecell=\^ncu_eccgen11_ctl\$ -sunv_args=-excludecell=\^ncu_eccgen6_ctl\$ -sunv_args=-excludecell=\^ncu_fcd_ctl\$ -sunv_args=-excludecell=\^ncu_i2cbuf32_ctl\$ -sunv_args=-excludecell=\^ncu_i2cbuf32_ni_ctl\$ -sunv_args=-excludecell=\^ncu_i2cbuf4_ctl\$ -sunv_args=-excludecell=\^ncu_i2cbuf4_ni_ctl\$ -sunv_args=-excludecell=\^ncu_i2cbufsii_ctl\$ -sunv_args=-excludecell=\^ncu_i2cbuftcu_ctl\$ -sunv_args=-excludecell=\^ncu_i2cfc_ctl\$ -sunv_args=-excludecell=\^ncu_i2cfcd_ctl\$ -sunv_args=-excludecell=\^ncu_i2cfd_ctl\$ -sunv_args=-excludecell=\^ncu_i2csc_ctl\$ -sunv_args=-excludecell=\^ncu_i2cscd_ctl\$ -sunv_args=-excludecell=\^ncu_i2csd_ctl\$ -sunv_args=-excludecell=\^ncu_mb0_ctl\$ -sunv_args=-excludecell=\^ncu_mb1_ctl\$ -sunv_args=-excludecell=\^ncu_scd_ctl\$ -sunv_args=-excludecell=\^ncu_ssiflow_ctl\$ -sunv_args=-excludecell=\^ncu_ssisif_ctl\$ -sunv_args=-excludecell=\^ncu_ssisrg64_ctl\$ -sunv_args=-excludecell=\^ncu_ssisrg8_ctl\$ -sunv_args=-excludecell=\^ncu_ssitop_ctl\$ -sunv_args=-excludecell=\^ncu_ssiui4_ctl\$ -sunv_args=-excludecell=\^ncu_ssiuif_ctl\$ -sunv_args=-excludecell=\^ncu_ssiuo4_ctl\$ -sunv_args=-excludecell=\^ncu_ucbbusin8_ctl\$ // #endif #ifndef CCU_GATE -flist=$DV_ROOT/verif/env/tcu/ccu_rtl.flist #endif #ifndef NIU_GATE #ifndef AXIS_NO_IP #ifndef FC_NO_NIU_T2 #ifdef NIU_SYSTEMC_T2 #include "fc_niu_systemc.config" -flist=$DV_ROOT/verif/env/niu/niu_systemc.flist #else -flist=$DV_ROOT/verif/env/niu/niu.flist #endif #endif #endif #endif #ifndef AXIS_NO_IP #ifndef DMU_GATE -flist=$DV_ROOT/verif/env/dmu/dmu.rtlflist #endif -flist=$DV_ROOT/verif/env/dmu/dmu.libsflist #endif #ifdef FC_NO_PEU_VERA #ifdef AXIS_NO_IP -flist=$DV_ROOT/verif/env/fc/axis_no_ip.flist -vcs_build_args=+define+NO_VCS_CASCADE_IP_CODE #else -config_rtl=FC_NO_PEUSAT_CODE #ifndef FC_NO_PEU_T2 -flist=$DV_ROOT/verif/model/verilog/pcie/ept/ept.flist #endif #ifdef USE_BOBO -vera_build_args=BUILD_USE_BOBO=1 -config_rtl=BUILD_USE_BOBO -midas_args=-DUSE_BOBO=1 -flist=$DV_ROOT/verif/model/verilog/pcie/ept/bobo.flist #endif // use_bobo #ifndef FC_NO_PEU_T2 -flist=$DV_ROOT/verif/env/ilu_peu/ilu_peu_rtl_encrypted.axis.flist #endif #endif //axis_no_ip #else // fc_no_peu_vera #ifndef PEU_GATE #ifndef FC_NO_PEU_T2 -flist=$DV_ROOT/verif/env/fc/ilu_peu_denali.flist #ifdef PEU_SYSTEMC_T2 #include "fc_pcie_systemc.config" -flist=$DV_ROOT/verif/env/ilu_peu/ilu_peu_systemc.flist #else -flist=$DV_ROOT/verif/env/ilu_peu/ilu_peu_rtl_encrypted.flist #endif //PEU_SYSTEMC_T2 #endif #endif #endif //fc_no_peu_vera #ifndef AXIS_NO_IP #ifndef DMU_GATE -flist=$DV_ROOT/verif/env/ilu_peu/ilu_peu_common.rtlflist #endif #endif #ifndef IO_GATE -flist=$DV_ROOT/verif/env/mcu/fbd_serdes_axis.flist #endif -flist=$DV_ROOT/verif/env/fc/fc_inc.flist -fsdbfile=fc_top.fsdb -image_diag_root=$DV_ROOT/verif -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DFC -midas_args=-tsbtagfmt=tagtarget -midas_args=-cpp_args=-traditional-cpp -sas_run_args=-DTHREAD_STATUS_ADDR=0x9a00000000 -sas_run_args=-DMEM_DISABLE -sas_run_args=-DINTR_TEST -sas_run_args=-DFORCE_PC -sas_run_args=-DTSO_CHECKER SUNVFORCEOPTS -sunv_args=-preload=SUNVLIBS_SUNV -sunv_args=-perlinclude=SUNVPERLINC -sunv_args=-define=SIM -sunv_args=-define=LIB //-sunv_args=-define=INITLATZERO -sunv_args=-define=VCS -sunv_args=-version -sunv_args=-topcell=cpu -sunv_args=-warn=2000 -sunv_args=-ignorepartial -sunv_args=-unusednet='unused$:unused\[[0-9]+\]$' -sunv_args=-excludepreload -sunv_args=-out=cpu.v -sunv_args=-path=SUNV_RTL_PATH -sunv_args=-path=SUNVMACROS -sunv_args=-showCompiledOutCode=off -sunv_use_nonprim -sunv_nonprim_list=$DV_ROOT/verif/env/fc/nonprimitive.list -sunv_args=-excludecell=\^dmu\$ -sunv_args=-excludecell=\^peu\$ -sunv_args=-excludecell=\^psr\$ -sunv_args=-excludecell=\^esr\$ -sunv_args=-excludecell=\^rdp\$ -sunv_args=-excludecell=\^rtx\$ -sunv_args=-excludecell=\^tds\$ -sunv_args=-excludecell=\^mac\$ -sunv_args=-excludecell=\^ccu\$ #ifndef ONLY_FOR_TO_1_0 -sunv_args=-excludecell=\^n2_rng_cust\$ #endif -sunv_args=-excludecell=\^fsr_left\$ -sunv_args=-excludecell=\^fsr_right\$ -sunv_args=-excludecell=\^fsr_bottom\$ #ifdef INPHI_AMB -sunv_args=-define=FBD_LAT_DELAY_2 #endif #ifdef MICRON_AMB -sunv_args=-define=FBD_LAT_DELAY_1 -vcs_run_args=+MICRON_AMB_USED #endif #ifdef IDT_AMB -sunv_args=-define=FBD_LAT_DELAY_1 -vcs_build_args=+define+IDT_FBDIMM -vcs_run_args=+BYPASS_AMB_DRAM_INIT -vcs_run_args=+IDT_AMB_USED #endif #ifdef NEC_AMB -sunv_args=-define=FBD_LAT_DELAY_1 #endif -vlint_top=tb_top -vlint_args=+define+TOP=tb_top -vlint_args=SUNVLIBS_OTHER -vlint_args=-turn_unspecified_off -vlint_args=-binary -vlint_args=-vlint -vlint_args=-depth 999 -vlint_args=-vr $DV_ROOT/verif/env/config/vlint.rc -illust_args=-b -c $DV_ROOT/verif/env/config/filter_vlint.rc -illust_run -wait_cycle_to_kill=15 -zeroIn_build_args=+define+TOP=tb_top -zeroIn_build_args=-d cpu #if defined(AXIS_BUILD) || defined(AXIS_COSIM) -zeroIn_build_args=-sim axis #else -zeroIn_build_args=-sim vcs #endif #ifdef FC_COVERAGE -vera_cov_obj=FC_COVERAGE -vcs_build_args=+define+FC_COVERAGE #define ZEROINCOV -config_rtl=SPCINF_COVERAGE #endif #ifndef ZINFASTBUILD #ifndef ZEROINCOV -zeroIn_build_args="-fastsim turbo" #endif #ifndef NOFASTMOD -zeroIn_build_args=-fastmod #endif #endif -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/common/verilog/checkers/0in_checkers.v #ifdef ZEROINCOV -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/common/coverage/0in_coverages.v #endif -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/fc/fc_zeroIn_cfg.v -zeroIn_build_args=SUNVLIBS_OTHER -zeroIn_build_args=-incr -zeroIn_build_args=+define+CPU=tb_top.cpu -zeroIn_build_args=+define+FC_NO_NIU_T2 -zeroIn_build_args=+define+FC_NO_PEU_T2 #ifndef FC_NO_NIU_T2 -zeroIn_build_args=+define+ESR=tb_top.cpu.esr -zeroIn_build_args=+define+RTX=tb_top.cpu.rtx -zeroIn_build_args=+define+TDS=tb_top.cpu.tds -zeroIn_build_args=+define+RDP=tb_top.cpu.rdp -zeroIn_build_args=+define+MAC=tb_top.cpu.mac -zeroIn_build_args=+define+NIU=tb_top.cpu.niu #endif -zeroIn_build_args=+define+ILU=tb_top.cpu.dmu.ilu -zeroIn_build_args=-exit_on_directive_errors -zeroIn_build_args=+define+FSR_NOATPG -zeroIn_build_args=+error+command-19 -zeroIn_build_args=+error+command-46 -zeroIn_build_args=+error+command-6 -zeroIn_build_args=+error+command-7 //skip processing bench modules #ifndef FC_NO_PEU_T2 -zeroIn_build_args=+skip_modules+fc_dmupeu_csr_probe #endif -zeroIn_build_args=+skip_modules+fc_l2_csr_probe -zeroIn_build_args=+skip_modules+fc_mcu_csr_probe -zeroIn_build_args=+skip_modules+fc_ncu_csr_probe #ifndef FC_NO_NIU_T2 -zeroIn_build_args=+skip_modules+fc_niu_csr_probe #endif -vcs_build_args=+define+DISABLE_TID_CHKR -vcs_build_args=+define+FSR_NOATPG //-vcs_run_args=+noldst_sync -vcs_build_args=SUNVLIBS_OTHER -vcs_build_args=+define+BWSIM_SAME_GCLK_RCLK+ -vcs_build_args=+define+MODEL_DRAM+ #ifdef DRAMX8 -vcs_build_args=+define+X8 -zeroIn_build_args=+define+X8 -vcs_run_args=+X8 #else -vcs_build_args=+define+X4 -zeroIn_build_args=+define+X4 #endif -vcs_build_args=+define+DRAM_SAT+ -vcs_build_args=+define+TOP=tb_top -vcs_build_args=+define+LIB -vcs_build_args=+define+SIM -vcs_build_args=+define+IOS -vcs_build_args=+define+N2 #ifndef FC_NO_NIU_T2 -vcs_build_args=+define+N2_NIU #endif #ifdef FC_NO_NIU_T2 -diaglist_cpp_args=-DFC_NO_NIU_T2 #endif #ifdef FC_NO_PEU_T2 -diaglist_cpp_args=-DFC_NO_PEU_T2 #endif #ifdef NIU_SYSTEMC_T2 -vcs_build_args=+define+NIU_SYSTEMC_T2 -diaglist_cpp_args=-DNIU_SYSTEMC_T2 #endif -vcs_build_args=+define+FLUSH_RESET -vcs_build_args=+define+SCAN_MODE #ifdef USE_TAP_DRIVER -vera_build_args="USE_JTAG_DRIVER=1" -vcs_build_args=+define+USE_JTAG_DRIVER #else #ifndef USE_FULL_FLOP -vcs_build_args=+define+FAST_FLUSH #endif // USE_FULL_FLOP #endif // USE_TAP_DRIVER #ifdef USE_FULL_FLOP -zeroIn_build_args=+define+MUXOHTEST //enable mux-ex check -vcs_build_args=+define+MUXOHTEST //enable mux-ex check #endif // USE_FULL_FLOP // Used for DTM Mode #ifdef TO_1_0_VECTORS -vera_build_args="TO_1_0_VECTORS=1" -config_rtl=TO_1_0_VECTORS // Axis doesn't read config.v soon enough, so we also need: -vcs_build_args=+define+TO_1_0_VECTORS #endif // Option to disable MEM initialization in array cell #ifdef NO_INIT_MEM -sunv_args=-define=NOINITMEM -config_rtl=NOINITMEM #endif -vcs_build_args=+define+DISABLE_tMRD_VIOLATION_AT_PD_ENTRY -vcs_build_args=+define+NO_Ill_cmd_during_init_MRS_with_DLL_disable_expected_CHECK #ifndef AXIS_TL // -vcs_build_args=$DV_ROOT/verif/env/common/pli/bwutility/libdummy.a -vcs_build_args="-P $DV_ROOT/verif/model/infineon/bwmem_pli.tab" #ifndef LINUX -vcs_build_args=$DV_ROOT/verif/model/infineon/libbwmem_pli.a #else -vcs_build_args=$DV_ROOT/verif/model/infineon/linux/libbwmem_pli.a #endif -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/bwutility/bwutility_pli.tab" #ifndef LINUX -vcs_build_args=$DV_ROOT/verif/env/common/pli/bwutility/libbwutility_pli.a #else -vcs_build_args=$DV_ROOT/verif/env/common/pli/bwutility/linux/libbwutility_pli.a #endif //added for l2 warm -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/cache/bwioj.tab" #ifndef LINUX -vcs_build_args=$DV_ROOT/verif/env/common/pli/cache/libiob.a #else -vcs_build_args=$DV_ROOT/verif/env/common/pli/cache/linux/libiob.a #endif -vcs_build_args=+define+NO_Ill_cmd_before_init_CHECK -vcs_build_args=+define+NO_err_cke -vcs_build_args=+define+NO_err_cke_diasserted_when_not_pwr_down_CHECK -vcs_build_args=+define+NO_err_dqs_and_dqsbar_not_in_sync_CHECK -vcs_build_args=+define+NO_err_clk_and_clkbar_not_in_sync_CHECK #endif #if defined(AXIS_TL) || defined (VCS_FAST_MCU) -flist=$DV_ROOT/verif/env/fc/axis_dimm.flist #else #ifdef DRAMX8 -flist=$DV_ROOT/verif/model/verilog/mem/dram/infineon_x8_ddr2.flist #else -flist=$DV_ROOT/verif/model/verilog/mem/dram/infineon_ddr2.flist #endif #endif -flist=$DV_ROOT/design/sys/iop/ccx/ccx_rtl.flist -flist=$DV_ROOT/design/sys/iop/db0/db0_rtl.flist -flist=$DV_ROOT/design/sys/iop/db1/db1_rtl.flist -flist=$DV_ROOT/design/sys/iop/efu/efu_rtl.flist -flist=$DV_ROOT/design/sys/iop/l2b/l2b_rtl.flist -flist=$DV_ROOT/design/sys/iop/l2t/l2t_rtl.flist -flist=$DV_ROOT/design/sys/iop/mcu/mcu_rtl.flist -flist=$DV_ROOT/design/sys/iop/ncu/ncu_rtl.flist -flist=$DV_ROOT/design/sys/iop/rst/rst_rtl.flist -flist=$DV_ROOT/design/sys/iop/sii/sii_rtl.flist -flist=$DV_ROOT/design/sys/iop/sio/sio_rtl.flist -flist=$DV_ROOT/design/sys/iop/spc/spc_rtl.flist -flist=$DV_ROOT/design/sys/iop/tcu/tcu_rtl.flist -flist=$DV_ROOT/verif/env/fc/fc.flist.des_v_rtl #if defined(AXIS_BUILD) || defined(AXIS_COSIM) #ifndef AXIS_TL -vcs_build_args=vera/mempli.a -vcs_build_args=vera/mal.o -vcs_build_args=vera/pgRandom.o -vcs_build_args=" -pl -R/import/freetools/local/gcc/3.3.2/lib " -vcs_build_args=" /import/freetools/local/gcc/3.3.2/lib/libstdc++.so" -vcs_build_args=" /import/freetools/local/gcc/3.3.2/lib/libgcc_s.so " //these four packet gen files are order sensitive!! sims reverses the order from //to what gets passed to the linker, and libnet.a must be at the end of the link -vcs_build_args=vera/libnet.a -vcs_build_args=vera/pgVera.a -vcs_build_args=vera/pgVeraWrap.o -vcs_build_args=vera/genCpacket.o -vcs_build_args=" $DV_ROOT/verif/env/common/pli/niu_pli/get_plus_args.o " #endif #else //note: the actual config cpp args e.g. FC_NO_PEU_T2, FC_NO_NIU_T2 //are declared inside fc.config, as for the non config cpp args, they are declared here #if defined(T2) -nosunv_run -nozeroIn_build -nozeroInSearch_build #endif #ifdef PEU_SYSTEMC_T2 -sysc_build -vera_build_args="PEU_SYSTEMC_T2=1" -vcs_build_args="+define+PEU_SYSTEMC_MODEL" -vcs_build_args="-sysc=220" -vcs_build_args="-cpp $CC_BIN/g++" -vcs_build_args="-ld $CC_BIN/g++" -vcs_build_args="-cc $CC_BIN/gcc" #endif //added these config cpp macros for OpenSparc T2 #ifdef FC_NO_NIU_T2 -vera_build_args="FC_NO_NIU_T2=1" -vcs_build_args=+define+FC_NO_NIU_T2 #endif #ifdef NIU_SYSTEMC_T2 -vera_build_args="NIU_SYSTEMC_T2=1" #endif #ifdef FC_NO_PEU_T2 -vera_build_args="FC_NO_PEU_T2=1" -vcs_build_args=+define+FC_NO_PEU_T2 #endif #ifdef FC_NO_PEU_VERA -vera_build_args="FC_NO_PEU_VERA=1" #endif // following added for no PEU mode (but with NIU) #ifndef FC_NO_NIU_T2 -vcs_build_args=+define+ESR=tb_top.cpu.esr -vcs_build_args=+define+RTX=tb_top.cpu.rtx -vcs_build_args=+define+TDS=tb_top.cpu.tds -vcs_build_args=+define+RDP=tb_top.cpu.rdp -vcs_build_args=+define+MAC=tb_top.cpu.mac #endif // -vcs_build_args=+applylearn+$DV_ROOT/verif/env/fc/pli_learn_all.tab -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/global_chkr/global_chkr.tab" #ifndef LINUX -vcs_build_args=$DV_ROOT/verif/env/common/pli/global_chkr/libglobal_chkr.a #else -vcs_build_args=$DV_ROOT/verif/env/common/pli/global_chkr/linux/libglobal_chkr.a #endif #ifndef GATESIM -vcs_build_args=+rad #endif -vcs_build_args="-Mupdate +warn=all +lint=none" -vcs_build_args="+notimingcheck +nospecify" VCS_BUILD_WITH_GPP -vcs_build_args="-cc gcc -cpp g++ -ld g++ -lstdc++" -vcs_build="-Xstrict=0x01 " -vcs_build_args=+v2k #ifndef FC_NO_NIU_T2 #ifndef PLAYBACK -vcs_build_args=" +vc vera/mal.o" -vcs_build_args=" +vc vera/pgVeraWrap.o" -vcs_build_args=" +vc vera/genCpacket.o" -vcs_build_args=" +vc vera/libnet.a" -vcs_build_args=" +vc vera/pgVera.a" -vcs_build_args=" +vc vera/pgRandom.o" #endif // PLAYBACK //-vcs_build_args="$DV_ROOT/verif/env/common/pli/niu_pli/get_plus_args.o" #ifndef LINUX -vcs_build_args="$DV_ROOT/verif/env/common/pli/niu_pli/libniu_pli.a" #else -vcs_build_args="$DV_ROOT/verif/env/common/pli/niu_pli/linux/libniu_pli.a" #endif -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/niu_pli/get_plus_args.tab" #endif -vcs_use_vera #endif #ifndef AXIS_TL -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/socket/socket_pli.tab" #ifndef LINUX -vcs_build_args=$DV_ROOT/verif/env/common/pli/socket/libsocket_pli.a #else -vcs_build_args=$DV_ROOT/verif/env/common/pli/socket/linux/libsocket_pli.a #endif #endif -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/monitor/monitor_pli.tab" #ifdef AXIS_64BIT -vcs_build_args=$DV_ROOT/verif/env/common/pli/monitor/libmonitor_pli_64.a #else #ifndef LINUX -vcs_build_args=$DV_ROOT/verif/env/common/pli/monitor/libmonitor_pli.a #else -vcs_build_args=$DV_ROOT/verif/env/common/pli/monitor/linux/libmonitor_pli.a #endif #endif #ifndef FC_NO_PEU_VERA #ifndef PLAYBACK -vcs_build_args=-P $DV_ROOT/verif/env/fnx/clib/report/report.tab -vcs_build_args=vera/report.a // -vcs_build_args=-P vera/denali_pcie.tab -vcs_build_args=-P $DENALI/verilog/pli.tab -vcs_build_args=$DENALI/verilog/denverlib.o #endif // PLAYBACK #endif -vcs_run_args=+SLAM_INIT_CMP -vcs_run_args=+DRAM -vcs_run_args=+no_slam_init -vcs_run_args=+slam_value=0 -vcs_run_args=+vera_exit_on_error -vcs_run_args=+mac0 -vcs_run_args=+mac1 -vcs_run_args=+mac2 -vcs_run_args=+mac3 -vcs_run_args=+rxc -vcs_run_args=+vera_disable_final_report -vcs_run_args=+vera_semaphore_size=64000 -vcs_run_args=+vera_mailbox_size=64000 -vcs_run_args=+0in_debug+no_auto_message_wrap #ifndef FC_NO_PEU_VERA -vcs_run_args=+vera_directc=$VERA_LIBDIR/denali_pcie.dl:$VERA_HOME/lib/libdenaliddv.so #endif -vcs_run_args=+0in_checker_finish_delay+3000 -vcs_run_args=+skt_timeout=50000 -pre_process_cmd="ln -s $DV_ROOT/verif/env/mcu/fbdimm_register.data ." -post_process_cmd="regreport -1 | tee status.log" -midas_args=-DL2_REG_PROG // -vera_vcon_file=cmp_top.vcon -vera_vcon_file=fc_top.vcon // Note that some test vector options are handled in fc.config #ifdef DTM15_SLAM_DP1 -vcs_run_args=+serdes_dtm1=1 -vcs_run_args=+serdes_dtm2=0 -vcs_run_args=+dbg_port_config=001 #endif //DTM15_SLAM_DP1 #ifdef DTM15_SLAM_DP2 -vcs_run_args=+serdes_dtm1=0 -vcs_run_args=+serdes_dtm2=1 -vcs_run_args=+dbg_port_config=001 #endif //DTM15_SLAM_DP2 #ifdef DTM15_SLAM -vcs_build_args=+define+SLAM_VECTORS -vcs_build_args=+define+DTM_ENABLED -vcs_build_args=+define+FBDIMM_BUG_107438 -vcs_build_args=+define+TI_wizaccel -diaglist_cpp_args=-DSLAM_VECTORS=SLAM_VECTORS -tg_seed=1 -vcs_run_args=+info -vcs_run_args=+show_delta -vcs_run_args=+show_memop -vcs_run_args=+0in_no_statistics -nofast_boot -max_cycle=9999999 -rtl_timeout=1000000 -vcs_run_args=+mcu_errmon_disable -vcs_run_args=+mcu_fmon_disable -vcs_run_args=+noDebugChecks -vcs_run_args=+CMPDR_RATIO_15 -midas_args=-DDTM_ENABLED -vcs_run_args=+DTM_ENABLED -vcs_run_args=+PCIE_REF_CLK_104 -vcs_run_args=+PEU_TEST -vcs_run_args=+PEU_DTM_PCIE_SKEW_LANE0_UI=20 // The following doesn't work because $DV_ROOT is not expanded by sims 1.270 // -use_denalirc=$DV_ROOT/verif/env/ilu_peu/.denalirc_bypass_training -vcs_run_args=+set_channel_read_latency=0x1717 -midas_args=-DSLAM_VECTORS -vcs_run_args=+SLAM_VECTORS -midas_args=-DSSI_CLK_4 -vcs_run_args=+SSI_CLK_4 -vcs_run_args=+ssi_mon -midas_args=-DSSI_STATUS -vcs_run_args=+SSI_STATUS -vcs_run_args=+TCK_PERIOD=9600 -midas_args=-DBOOTPROM_INIT -midas_args=-DSYNC_SLAM_NO_SLAM #endif // DTM15_SLAM #ifdef DTM15_SLAM_DUMP -vcs_run_args=+DUMP_LIMIT -vcs_run_args=+DUMP_PINS -vcs_run_args=+DUMP_DEBUG_PORT -debussy -fsdb2vcd #endif // DTM15_SLAM_DUMP #ifdef DTM15_NONSLAM_DP1 -midas_args=-DSERDES_DTM1=1 -midas_args=-DSERDES_DTM2=0 #endif // DTM15_NONSLAM_DP1 #ifdef DTM15_NONSLAM_DP2 -midas_args=-DSERDES_DTM1=0 -midas_args=-DSERDES_DTM2=1 #endif // DTM15_NONSLAM_DP2 #ifdef DTM15_NONSLAM -vcs_build_args=+define+NON_SLAM_VECTORS -vcs_build_args=+define+DTM_ENABLED -vcs_build_args=+define+FBDIMM_BUG_107438 -vcs_build_args=+define+TI_wizaccel -vcs_build_args=+define+FULL_RESET -vcs_build_args=+define+FAST_FLUSH -diaglist_cpp_args=-DNON_SLAM_VECTORS=NON_SLAM_VECTORS -tg_seed=1 -vcs_run_args=+info -vcs_run_args=+show_delta -vcs_run_args=+show_memop -vcs_run_args=+ssi_mon -vcs_run_args=+0in_no_statistics -nofast_boot -max_cycle=9999999 -rtl_timeout=2000000000 -vcs_run_args=+th_timeout=2000000000 -vcs_run_args=+mcu_errmon_disable -vcs_run_args=+mcu_fmon_disable -vcs_run_args=+noDebugChecks -midas_args=-DCMPDR_RATIO_15 -vcs_run_args=+DTM_ENABLED -midas_args=-DDTM_ENABLED -vcs_run_args=+PCIE_REF_CLK_104 -vcs_run_args=+PEU_TEST -vcs_run_args=+PEU_DTM_PCIE_SKEW_LANE0_UI=20 -midas_args=-DMCU_CHANNEL_DATA=0x0000000000170017 -vcs_run_args=+NON_SLAM_VECTORS -midas_args=-DNON_SLAM_VECTORS -vcs_run_args=+ssi_mon -vcs_run_args=+SSI_STATUS -midas_args=-DSSI_STATUS -vcs_run_args=+TCK_PERIOD=9600 -midas_args=-DCCU_REG_PROG -midas_args=-DL2_REG_PROG -vcs_run_args=+NO_MCU_CSR_SLAM -midas_args=-DBOOTPROM_INIT -midas_args=-DWARM_RESET_INIT -vcs_run_args=+NO_CCU_CSR_SLAM -midas_args=-DNO_SLAM_INIT_MCUCTL -vcs_run_args=+noUserEvents -vcs_run_args=+lsu_mon_off -vcs_run_args=+l2esr_mon_off -vcs_run_args=+mcuesr_mon_disable -vcs_run_args=+nb_crc_mon_disable -vcs_run_args=+mcusat_cov_mon_disable -vcs_run_args=+disable_refresh_checker -vcs_run_args=+gchkr_off #endif // DTM15_NONSLAM #ifdef DTM15_NONSLAM_DUMP -vcs_run_args=+DUMP_LIMIT -vcs_run_args=+DUMP_PINS -vcs_run_args=+DUMP_DEBUG_PORT -debussy -fsdb2vcd #endif // DTM15_NONSLAM_DUMP