// ========== Copyright Header Begin ========================================== // // OpenSPARC T2 Processor File: mcu.config // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved // 4150 Network Circle, Santa Clara, California 95054, U.S.A. // // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; version 2 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // // For the avoidance of doubt, and except that if any non-GPL license // choice is available it will apply instead, Sun elects to use only // the General Public License version 2 (GPLv2) at this time for any // software where a choice of GPL license versions is made // available with the language indicating that GPLv2 or any later version // may be used, or where a choice of which version of the GPL is applied is // otherwise unspecified. // // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, // CA 95054 USA or visit www.sun.com if you need additional information or // have any questions. // // ========== Copyright Header End ============================================ #include "defaults.config" #ifdef DRAMX8 #define DRAMX8 DRAMX8 #endif #ifdef AXIS_BUILD -config_rtl=AXIS -sunv_args=-keepSectionSym=AXIS_SMEM -sunv_args=-keepSectionSym=EMUL_COSIM -vcs_build_args=-P $VERA_HOME/lib/vera_pli.tab -vcs_build_args=$VERA_HOME/lib/libSysSciTask.a -vcs_build_args=-pl -lsocket -pl -lnsl -pl -lintl -pl -ldl -vcs_build_args=+v2000 -vcs_build_args=+define+AXIS //-axis_build_args="-scope n2_fc -check_synth " //-vcs_build_args=" +dutexcl+pll_core+cl_a1_blatch_4x+cl_sc1_blatch_4x " //-vcs_build_args=" +define+AXIS_FBDIMM_HW " //-vcs_build_args=" +dut+amb_top" -axis_build_args="-scope n2_fc " -vcs_build_args=+define+DISABLE_ERR_MON -vcs_build_args=+define+FSR_NOATPG -vcs_run_args=+NO_DUMMY_READ -vcs_run_args=+BYPASS_L0_STATE_WAIT -vcs_build_args=+define+OTHER_FBDIMM -diaglist_cpp_args=-DAXIS_BUILD #ifdef AXIS_COSIM -vcs_build_args="+define+AXIS_SMEM+EMUL_COSIM+AXIS_EMUL_COSIM aaaaa" -axis_build_args="-hwtype xs -model_type axis_cs -comp_64" -vcs_build_args=" +dut+mcu+mcusat_fbdimm" -axis_build_args=-fpga_compile #else -vcs_build_args=" +dut+cpu" #endif -vcs_build_args=+define+AXIS_FBDIMM_HW -vcs_build_args=+define+FBDIMM_NUM_1+ #else #ifdef DRAMX8 -flist=$DV_ROOT/verif/model/verilog/mem/dram/infineon_x8_ddr2.flist #else -flist=$DV_ROOT/verif/model/verilog/mem/dram/infineon_ddr2.flist #endif #endif -asm_diag_root=$DV_ROOT/verif/diag -vera_diag_root=$DV_ROOT/verif/diag -vera_config_root=$DV_ROOT/verif -image_diag_root=$DV_ROOT/verif -wait_cycle_to_kill=10 -post_process_cmd="regreport -1 > status.log" -model=mcu #ifdef INPHI_AMB -flist=$DV_ROOT/verif/model/inphi/inphi_amb.flist -flist=$DV_ROOT/verif/model/sun/sun_misc.flist #elif MICRON_AMB -flist=$DV_ROOT/verif/model/micron/micron_amb.flist -flist=$DV_ROOT/verif/model/sun/sun_misc.flist #elif IDT_AMB -flist=$DV_ROOT/verif/model/idt/idt_amb.flist -flist=$DV_ROOT/verif/model/sun/sun_misc.flist #elif NEC_AMB -flist=$DV_ROOT/verif/model/nec/nec_amb.flist -flist=$DV_ROOT/verif/model/sun/sun_misc.flist -vcs_build_args=+define+ASSERTS_OFF -vcs_build_args=+nospecify -vcs_build_args=+access+rwc -vcs_build_args=+no_tchkmsg -vcs_build_args=+notimingcheck -vcs_build_args=+libext+.vp+ -vcs_build_args=+warn=noTMR #else -flist=$DV_ROOT/verif/model/sun/sun_amb.flist #endif -flist=$DV_ROOT/verif/env/mcu/mcu.flist -flist=$DV_ROOT/verif/env/tcu/ccu_rtl.flist #ifdef AXIS_BUILD -flist=$DV_ROOT/verif/env/mcu/fbd_serdes_axis.flist -vera_build_args="VFLAGS=-DAXIS_DDR2_MODEL" -vcs_build_args=+define+AXIS_DDR2_MODEL -flist=$DV_ROOT/verif/env/fc/axis_dimm.flist -vcs_run_args=+ddr2_way_err_enable=0 -vcs_run_args=+ddr2_way_warn_enable=1 #elif FSR_RTL -flist=$DV_ROOT/verif/env/mcu/fbd_serdes.flist #else -flist=$DV_ROOT/verif/env/mcu/fbd_serdes_axis.flist #endif #ifdef AXIS_NO_FSR -vcs_build_args=+define+AXIS_FBDIMM_NO_FSR -vcs_build_args="-Z $DV_ROOT/verif/env/mcu/axis_hack_fsr.v " #ifdef AXIS_TL -vcs_build_args=+dut+no_fsr_for_axis #endif #endif -config_rtl=MCU -vera_vcon_file=mcu_top.vcon -env_base=$DV_ROOT/verif/env/mcu #ifndef AXIS_BUILD // NCR:enabled in the diags directly -vcs_run_args=+slam_init_value -vcs_build_args=-v $DV_ROOT/verif/env/common/verilog/monitors/ddr2_monitor.v -vcs_build_args=-v $DV_ROOT/verif/env/mcu/amb_dram_err_inject.v -vcs_build_args=-v $DV_ROOT/verif/env/common/verilog/monitors/mcu_errmon.v -vcs_build_args="-Xpae=0x20" -vcs_build_args="+v2k" -vcs_build_args=+rad -vcs_build_args="-notice" -vcs_build_args=-M -vcs_build_args=-Mupdate -vcs_build_args=-vera -vcs_build_args=+define+ZEROIN_DDR2_DRAM_MONITOR #endif -vera_build_args=PAL_OPTS="sys=DRAM" -vcs_build_args=+define+BWSIM_SAME_GCLK_RCLK+ -vcs_build_args=+define+DRAM_SAT+ -vcs_build_args=+define+MODEL_DRAM+ #ifdef IDT_AMB -vcs_build_args=+define+DDR2_0IN_SIM_MON+ -vcs_build_args=+define+DDR2_MONITOR_ON+ #endif #ifdef DRAMX8 -vcs_build_args=+define+X8+ -vera_build_args="VFLAGS=-DX8 -DDRAM" -zeroIn_build_args=+define+X8 -vcs_run_args=+X8 #else -vcs_build_args=+define+X4+ -vera_build_args="VFLAGS=-DDRAM" #endif -vcs_build_args=+define+MCUSAT -vcs_build_args=+define+FSR_NOATPG #ifdef AXIS_BUILD -vcs_build_args=+define+NO_Ill_cmd_before_init_CHECK -vcs_build_args=+define+NO_err_cke -vcs_build_args=+define+NO_err_cke_diasserted_when_not_pwr_down_CHECK -vcs_build_args=+define+NO_err_dqs_and_dqsbar_not_in_sync_CHECK -vcs_build_args=+define+NO_Ill_bank_state_CHECK -vcs_build_args=+define+NO_Ill_cmd_while_bank_active_CHECK -vcs_build_args=+define+NO_err_rd_dqs_not_asserted_when_rd_data_ready_CHECK -vcs_build_args=+define+NO_Ill_cmd_after_pre_CHECK -vcs_build_args=+define+NO_Ill_cmd_during_init_cke_not_low_for_200ns_CHECK -vcs_build_args=+define+NO_Ill_cmd_during_init_pre_all_issued_early_CHECK -vcs_build_args=+define+NO_Ill_cmd_during_init_MRS_with_DLL_disable_expected_CHECK -vcs_build_args=+define+NO_err_clk_and_clkbar_not_in_sync_CHECK #endif // NCR -vcs_build_args=+define+NO_err_invalid_cmd_CHECK -vcs_build_args=+define+DISABLE_tMRD_VIOLATION_AT_PD_ENTRY -vcs_build_args=+define+DISABLE_TID_CHKR // NCR -vcs_build_args="-P /import/datools/vendor/denali/3.100-0008/verilog/pli.tab" // NCR -vcs_build_args=/import/datools/vendor/denali/3.100-0008/verilog/denverlib.o -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/bwsocket/bwsocket_pli.tab" -vcs_build_args=$DV_ROOT/verif/env/common/pli/bwutility/libdummy.a -vcs_build_args=$DV_ROOT/verif/env/common/pli/bwsocket/libbwsocket_pli.a -vcs_build_args="-P $DV_ROOT/verif/model/infineon/bwmem_pli.tab" -vcs_build_args=$DV_ROOT/verif/model/infineon/libbwmem_pli.a -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/bwutility/bwutility_pli.tab" -vcs_build_args=$DV_ROOT/verif/env/common/pli/bwutility/libbwutility_pli.a -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/monitor/monitor_pli.tab" -vcs_build_args=$DV_ROOT/verif/env/common/pli/monitor/libmonitor_pli.a -vcs_build_args=$DV_ROOT/verif/model/verilog/mem/fbdimm/monitor/hasher.o #ifdef INPHI_AMB -vcs_build_args=+define+INPHI_FBDIMM -vcs_build_args=+define+VERBOSE -vcs_run_args=+nospecify -vcs_run_args=+notimingcheck #endif -drm_disk=[/export/home/bw=30] -drm_type=vcs -drm_freeprocessor=1.0 SUNVFORCEOPTS -sunv_args=-topcell=cpu -sunv_args=-define=PAD_NIAGARA -sunv_args=-define=sim -sunv_args=-flattencell='_macro$' -sunv_args=-define=SIM -sunv_args=-define=LIB //-sunv_args=-define=INITLATZERO -sunv_args=-define=SCAN_MODE -sunv_args=-showCompiledOutCode=off -sunv_use_nonprim -sunv_nonprim_list=$DV_ROOT/verif/env/mcu/mcu_nonprimitive.list -sunv_args=-excludepreload -sunv_args=-excludecell=\^fsr_left\$ -sunv_args=-excludecell=\^fsr_right\$ -sunv_args=-excludecell=\^fsr_bottom\$ -sunv_args=-excludecell=\^ccu\$ -sunv_args=-out=cpu.v -sunv_args=-path=SUNV_RTL_PATH -sunv_args=-path=SUNVMACROS -sunv_args=-preload=SUNVLIBS_SUNV -sunv_args=-perlinclude=SUNVPERLINC -sunv_args=-strict #ifdef INPHI_AMB -sunv_args=-define=FBD_LAT_DELAY_2 #endif #ifdef MICRON_AMB -sunv_args=-define=FBD_LAT_DELAY_1 #endif #ifdef IDT_AMB -sunv_args=-define=FBD_LAT_DELAY_1 #endif #ifdef NEC_AMB -sunv_args=-define=FBD_LAT_DELAY_1 #endif -vlint_top=cpu -vlint_args=+define+TOP=cpu -vlint_args=-merge_bus_report -vlint_args=-turn_unspecified_off -vlint_args=-binary -vlint_args=-vlint -vlint_args=-depth 999 -vlint_args=-vr $DV_ROOT/verif/env/config/vlint.rc -vlint_args=-turn_unspecified_off -vlint_args=SUNVLIBS_OTHER -illust_run -illust_args=-b -c $DV_ROOT/verif/env/config/filter_vlint.rc -zeroIn_build_args=+define+TOP=tb_top -zeroIn_build_args=+define+MCUSAT -zeroIn_build_args=+define+FSR_NOATPG -zeroIn_build_args=-d cpu #ifdef AXIS_BUILD -drm_freeram=1500 -zeroIn_build_args=-sim axis #else #ifdef NEC_AMB -drm_freeram=512 #else -drm_freeram=200 #endif -zeroIn_build_args=+define+ZEROIN_DDR2_DRAM_MONITOR -zeroIn_build_args=-sim vcs -zeroIn_build_args="-fastmod mcu" //-zeroIn_build_args="-fastsim turbo" -zeroIn_build_args=+error+command-19 -zeroIn_build_args=+error+command-46 -zeroIn_build_args=+error+command-6 -zeroIn_build_args=+error+command-7 #endif -zeroIn_build_args=-exit_on_directive_errors -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/mcu/mcu_zeroIn_cfg.v -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/common/verilog/checkers/mcu/mcul2_intf_chkr.v -zeroIn_build_args=-v SUNV_PATH/library/cl_rtl_ext.v -zeroIn_build_args=-v LAVA_LIB_PATH/cl_dp1/compiled/cl_dp1.v -zeroIn_build_args=-v LAVA_LIB_PATH/cl_u1/compiled/cl_u1.v -zeroIn_build_args=-v LAVA_LIB_PATH/cl_sc1/compiled/cl_sc1.v -vcs_run_args=+0in_checker_finish_delay+3000 -vcs_build_args=+define+LIB //-vcs_build_args=+define+INITLATZERO -vcs_build_args=+define+SCAN_MODE -vcs_build_args=SUNVLIBS_OTHER -sas_run_args=-DSP0 -sas_run_args=-DMEM_TEST -sas_run_args=-DINTR_TEST -sas_run_args=-DMEM_DEBUG -sas_run_args=-DNIAGARA -vcs_run_args=+vera_disable_final_report -vcs_run_args=+plusarg_save -vcs_run_args=+vera_exit_on_error -vcs_run_args=+DRAM -vcs_run_args=+vera_exit_on_error -vcs_run_args=+no_slam_init -pre_process_cmd="\rm -f *.gz" #ifdef DCH_8DIMM -pre_process_cmd="ln -s $DV_ROOT/verif/env/mcu/fbdimm_mem_data/dch_8dm*.data ." -post_process_cmd="gzip dch*.data" #endif #ifdef DCH_4DIMM -pre_process_cmd="ln -s $DV_ROOT/verif/env/mcu/fbdimm_mem_data/dch_4dm*.data ." -post_process_cmd="gzip dch*.data" #endif #ifdef DCH_2DIMM -pre_process_cmd="ln -s $DV_ROOT/verif/env/mcu/fbdimm_mem_data/dch_2dm*.data ." -post_process_cmd="gzip dch*.data" #endif #ifdef DCH_1DIMM -pre_process_cmd="ln -s $DV_ROOT/verif/env/mcu/fbdimm_mem_data/dch_1dm*.data ." -post_process_cmd="gzip dch*.data" #endif #ifdef SCH_8DIMM -pre_process_cmd="ln -s $DV_ROOT/verif/env/mcu/fbdimm_mem_data/sch_8dm*.data ." -post_process_cmd="gzip sch*.data" #endif #ifdef SCH_4DIMM -pre_process_cmd="ln -s $DV_ROOT/verif/env/mcu/fbdimm_mem_data/sch_4dm*.data ." -post_process_cmd="gzip sch*.data" #endif #ifdef SCH_2DIMM -pre_process_cmd="ln -s $DV_ROOT/verif/env/mcu/fbdimm_mem_data/sch_2dm*.data ." -post_process_cmd="gzip sch*.data" #endif #ifdef SCH_1DIMM -pre_process_cmd="ln -s $DV_ROOT/verif/env/mcu/fbdimm_mem_data/sch_1dm*.data ." -post_process_cmd="gzip sch*.data" #endif -pre_process_cmd="ln -s $DV_ROOT/verif/env/mcu/fbdimm_register.data ." -post_process_cmd="regreport -1 > status.log" -post_process_cmd="gzip vcs.log" -post_process_cmd="gzip sims.log" -asm_diag_root=$DV_ROOT/verif -tpt_diag_root=$DV_ROOT/verif -spis_diag_root=$DV_ROOT/verif -vera_diag_root=$DV_ROOT/verif -vera_config_root=$DV_ROOT/verif -vcs_cm_config=$DV_ROOT/verif/env/mcu/mcu.cm_config -image_diag_root=$DV_ROOT/verif -drm_freeswap=1000 -drm_freeram=1000 #ifdef AXIS_BUILD //AXIS model only works with one size of dram.. so assume this and call axis_conver script to buil dream data based on this size -pre_process_cmd="ln -s $DV_ROOT/verif/env/mcu/fbdimm_mem_data/dch_1dm_rk1_2Gb_mem.data mem.image" -axis_run_args=-runpresim '"$DV_ROOT/verif/env/mcu/axis_convert -s -m 0x800000000 "' #endif #ifndef ZEROINCOV -zeroIn_build_args="-fastsim turbo" #else -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/common/coverage/mcusat/mcuras_0in_cov.v // This arg creates a 0in_coverage_bitmap.txt in the 0in build dir -zeroIn_dbg_args=+0in_debug+display_stats_in_binary+coverage_bit_map #endif