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// 
// OpenSPARC T2 Processor File: denali_pcie_root_complex_monitor.v
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`timescale 10fs/10fs

module denali_pcie_root_complex_monitor (
    TX,
    TX_,
    RX,
    RX_,
    CLK_TX,
    CLK_RX,
    PERST_ 
);
  parameter linkWidth = 8;

   // the DV_ROOT gets replaced by GNUmakefile
  // parameter  interface_soma = "$DV_ROOT/verif/env/fnx/vlib/FNXPCIEXactor/sim/soma_default.spc";
  // parameter  interface_soma = "$DV_ROOT/verif/env/ilu_peu/soma_fastlink_root_monitor.spc";
  parameter interface_soma = {"$DV_ROOT/verif/env/ilu_peu/soma_root.spc"};

  parameter  init_file      = "";

     input [(linkWidth-1):0] TX;
     input [(linkWidth-1):0] TX_;
    input [(linkWidth-1):0] RX;
    input [(linkWidth-1):0] RX_;
    input PERST_;
    inout CLK_TX;
      reg den_CLK_TX;
      assign CLK_TX = den_CLK_TX;
    inout CLK_RX;
      reg den_CLK_RX;
      assign CLK_RX = den_CLK_RX;
  
  

initial begin
   $pcie_access(TX,TX_,RX,RX_,PERST_,CLK_TX,den_CLK_TX,CLK_RX,den_CLK_RX);
end
   
endmodule

`timescale 1ps/1ps