//Common files for encrypted and unencrypted
$DV_ROOT/verif/env/common/verilog/misc/defines.vh
$DV_ROOT/verif/env/common/verilog/misc/dispmonDefines.vh
ilu_peu_top.h
//+incdir++
//+incdir+.
//+incdir+../common/verilog/checkers
//+incdir+../common/verilog/misc
 
+incdir+$DV_ROOT/design/sys/iop/dmu/rtl
// commented this out
//+incdir+$DV_ROOT/design/sys/iop/peu/rtl
//+incdir+$DV_ROOT/design/sys/iop/pcie_common/rtl
//+incdir+$DV_ROOT/design/sys/iop/pcie_common/rtl

$DV_ROOT/design/sys/iop/pcie_common/rtl/pcie.h
$DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_csr_defines.h


//ILU
//DMU needed but using  -vcs_build_args=+define+NO_DMC+NO_DSN+NO_MB0+NO_CB0
// so only ILU gets instantiated
// 04/22/04 udevan
// move dmu.v to verif flist so that this files can be reused for FC
//
$DV_ROOT/design/sys/iop/dmu/rtl/dmu.h
// $DV_ROOT/design/sys/iop/dmu/rtl/dmu.v
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu.v                            
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_defines.h                
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_log_en_entry.v   
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_iil.v
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib.v                        
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_log_err.v        
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_stage_mux_only.v         
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_iil_bufmgr.v
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_addr_decode.v            
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_log_err_entry.v  
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_eil.v                        
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_iil_crdtcnt.v
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_cim.v                    
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_pec_int_en.v         
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_eil_bufmgr.v                 
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_iil_parchk.v
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_csr.v                    
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_pec_int_en_entry.v   
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_eil_datafsm.v                
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_iil_rcdbldr.v
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_int_en.v         
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_csrpipe_5.v              
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_eil_rcdbldr.v                
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_iil_xfrfsm.v
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_int_en_entry.v   
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_csrpipe_6.v              
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_eil_relgen.v                 
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_isb.v
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_log_en.v         
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_default_grp.v            
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_eil_xfrfsm.v
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_diagnos_entry.v
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_diagnos.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_dcb.v


//+incdir+$DV_ROOT/design/sys/iop/plp/rtl/
// commented this out
//$DV_ROOT/design/sys/iop/peu/rtl/peu.h
$DV_ROOT/design/sys/iop/pcie_common/rtl/pcie.h
$DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_csr_defines.h

-v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_dcm_daemon.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/csr_sw.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_dcc.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_srq.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_srq_qdp.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_srq_qcp.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_srq_qci.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_dcs.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_dcs_ism.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_dcs_osm.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_dcs_sdp.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_dcd.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_frr_arbiter.v
// AT-: $DV_ROOT/design/sys/iop/pcie_common/rtl/lbist_rst_cct.v
// $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_sync_flop.v

//Generic clock modules 
-v $DV_ROOT/libs/clk/n2_clk_clstr_hdr_cust_l/n2_clk_clstr_hdr_cust/rtl/n2_clk_clstr_hdr_cust.v
-v $DV_ROOT/libs/clk/n2_clk_clstr_hdr2_cust_l/n2_clk_clstr_hdr2_cust/rtl/n2_clk_clstr_hdr2_cust.v


//Added for the real clocks for DMU
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_dmu_io_cust/rtl/n2_clk_dmu_io_cust.v
-v $DV_ROOT/libs/clk/rtl/clkgen_dmu_io.v

// AT: PEU Clk Gen modules
//-v $DV_ROOT/libs/clk/rtl/clkgen_peu_io.v
//-v $DV_ROOT/libs/clk/rtl/clkgen_peu_pc.v
//-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_peu_io_cust/rtl/n2_clk_peu_io_cust.v
//-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_peu_pc_cust/rtl/n2_clk_peu_pc_cust.v


//End Common rtl