// ========== Copyright Header Begin ========================================== // // OpenSPARC T2 Processor File: N2fcPiuShadowRegs.vr // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved // 4150 Network Circle, Santa Clara, California 95054, U.S.A. // // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; version 2 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // // For the avoidance of doubt, and except that if any non-GPL license // choice is available it will apply instead, Sun elects to use only // the General Public License version 2 (GPLv2) at this time for any // software where a choice of GPL license versions is made // available with the language indicating that GPLv2 or any later version // may be used, or where a choice of which version of the GPL is applied is // otherwise unspecified. // // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, // CA 95054 USA or visit www.sun.com if you need additional information or // have any questions. // // ========== Copyright Header End ============================================ class N2fcPiuShadowRegs { bit [63:0] piuPcie64Offset; bit [63:0] piuMsi32Address; bit [63:0] piuMsi64Address; integer piuMaxPayloadSize; bit [63:0] ncuBaseAddr [3]; bit [15:0] piuREQ_ID; bit [63:0] EQBaseAddr; bit [6:0] EQTail [36]; bit [6:0] EQHead [36]; bit [63:0] MSIMapping [256]; bit [63:0] IoMmuControl; bit [63:0] IoMmuTsbControl; bit [63:0] IoMmuDev2Iotsb [16]; bit [63:0] IoMmuIoTsbDesc [32]; task new (); function bit MsiIsValid(integer MSInum) { bit[63:0] temp = MSIMapping[MSInum]; MsiIsValid = temp[63]; } function bit MsiIsEqWr(integer MSInum) { bit[63:0] temp = MSIMapping[MSInum]; MsiIsEqWr = temp[62]; } function bit[5:0] GetMsiEqNum(integer MSInum) { bit[63:0] temp = MSIMapping[MSInum]; GetMsiEqNum = temp[5:0]; } task SetMsiEqWr(integer MSInum) { bit[63:0] temp = MSIMapping[MSInum]; temp[62] = 1; MSIMapping[MSInum] = temp; } task ClearMsiEqWr(integer MSInum) { bit[63:0] temp = MSIMapping[MSInum]; temp[62] = 0; MSIMapping[MSInum] = temp; } } //--------------------------------------------------------------- // "new" task. //--------------------------------------------------------------- task N2fcPiuShadowRegs::new () { integer i; piuPcie64Offset = 0; piuMsi32Address = 0; piuMsi64Address = 0; piuMaxPayloadSize = 128; ncuBaseAddr[0] = 0; ncuBaseAddr[1] = 0; ncuBaseAddr[2] = 0; piuREQ_ID = 0; EQBaseAddr = 0; for(i=0; i<36; i++) { EQTail[i] = 0; EQHead[i] = 0; } for(i=0; i<256; i++) { MSIMapping[i] = 0; } }