// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lpr_b.csr_define.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
#ifndef LPR_B_CSR_DEFINE
#define LPR_B_CSR_DEFINE

`define FIRE_PLC_TLU_CTB_LPR_B_CSRBUS_EXT_ADDR_WIDTH	13
`define FIRE_PLC_TLU_CTB_LPR_B_CSRBUS_EXT_ADDR_RANGE	12:0

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_HW_ADDR	27'b000000011111100000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_ADDR	30'b000000011111100000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_NAME	"fire_plc_tlu_ctb_lpr_csr_b_ahb"
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_WIDTH	64
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_DEPTH	8192
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_SLC	63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_INT_SLC	63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_POSITION	0
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_FIELD_NAME	"fire_plc_tlu_ctb_lpr_csr_b_ahb"
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_LOW_ADDR_WIDTH	13
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_SEL_RANGE	12:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_ADDR_RANGE	26:13
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_READ_MASK	64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_READ_ONLY_MASK	64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_WRITE_MASK	64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_WRITE_ONLY_MASK	64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_SET_MASK	64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_CLEAR_MASK	64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_TOGGLE_MASK	64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_RMASK	64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_RESERVED_BIT_MASK	64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_HW_LD_MASK	64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_POR_VALUE	64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_INTERNAL_REG	0
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_EXTERNAL_DECODE_REG	0
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_ALIASED_FROM	0
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_ZERO_TIME_OMNI	0
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_HW_ACC_JTAG_RD	1
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_HW_ACC_JTAG_WR	1
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_HW_ACC_PIO_SLOW_RD	1
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_HW_ACC_PIO_SLOW_WR	1
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_HW_ACC_PIO_MED_RD	1
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_HW_ACC_PIO_MED_WR	1
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_HW_ACC_PIO_FAST_RD	1
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_HW_ACC_PIO_FAST_WR	1
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_NUM_FIELDS	1
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_DATA_FID	0
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_DATA_SLC	31:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_DATA_WIDTH	32
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_DATA_INT_SLC	31:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_DATA_POSITION	0
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_DATA_FMASK	64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_DATA_HW_LD_MASK	64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_DATA_POR_VALUE	32'b00000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_B_AHB_DATA_FIELD_NAME	"data"


#endif