// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ios_ras_ports_binds.vrhpal
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
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// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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#ifndef INC__IOS_RAS_PORTS_BINDS_VRH
#define INC__IOS_RAS_PORTS_BINDS_VRH

#include "top_defines.vrh"

port niu_sii_inj_port {
	clk;
	req_vld;
	data;
//	hdr;
	parity;
}

bind niu_sii_inj_port niu_sii_inj_bind {
	clk		niu_sii_inj.clk;
	req_vld		niu_sii_inj.req;
	data		niu_sii_inj.data;
//	hdr		niu_sii_inj.hdr;
	parity		niu_sii_inj.parity;	
}

port sio_niu_inj_port {
	clk;
	req_vld;
	data;
	parity;
}

bind sio_niu_inj_port sio_niu_inj_bind {
	clk		sio_niu_inj.clk;
	req_vld		sio_niu_inj.req;
	data		sio_niu_inj.data;
	parity		sio_niu_inj.parity;	
}

port dmu_sii_inj_port {
	clk;
	req_vld;
	data;
	parity;
	be_parity;
	wrack_vld;
	wrack_tag;
	wrack_par;
}

bind dmu_sii_inj_port dmu_sii_inj_bind {
	clk		dmu_sii_inj.clk;
	req_vld		dmu_sii_inj.req;
	data		dmu_sii_inj.data;
	parity		dmu_sii_inj.parity;	
	be_parity	dmu_sii_inj.be_parity;	
	wrack_vld	dmu_sii_inj.wrack_vld;
	wrack_tag	dmu_sii_inj.wrack_tag;
	wrack_par	dmu_sii_inj.wrack_par;
}

port sio_dmu_inj_port {
	clk;
	req_vld;
	data;
	parity;
}

bind sio_dmu_inj_port sio_dmu_inj_bind {
	clk		sio_dmu_inj.clk;
	req_vld		sio_dmu_inj.req;
	data		sio_dmu_inj.data;
	parity		sio_dmu_inj.parity;	
}

port l2_sio_inj_port {
	clk;
	ctag_vld;
	data;
	parity;
	ue_err;
}

.for($b=0; $b<8; $b++) {
bind l2_sio_inj_port  l2_${b}_sio_inj_bind {
	clk		l2_${b}_sio_inj.clk;
	ctag_vld	l2_${b}_sio_inj.ctag_vld;
	data		l2_${b}_sio_inj.data;
	parity		l2_${b}_sio_inj.parity;
	ue_err		l2_${b}_sio_inj.ue_err;
}
.}

port sii_ncu_inj_port {
	clk;
	gnt;
	req;
	data;
	parity;
}

bind sii_ncu_inj_port sii_ncu_inj_bind {
	clk		sii_ncu_inj.clk;
	gnt		sii_ncu_inj.gnt;
	req		sii_ncu_inj.req;
	data		sii_ncu_inj.data;
	parity		sii_ncu_inj.parity;
}

#endif