// ========== Copyright Header Begin ========================================== // // OpenSPARC T2 Processor File: ios_rasmon.if.vrhpal // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved // 4150 Network Circle, Santa Clara, California 95054, U.S.A. // // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; version 2 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // // For the avoidance of doubt, and except that if any non-GPL license // choice is available it will apply instead, Sun elects to use only // the General Public License version 2 (GPLv2) at this time for any // software where a choice of GPL license versions is made // available with the language indicating that GPLv2 or any later version // may be used, or where a choice of which version of the GPL is applied is // otherwise unspecified. // // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, // CA 95054 USA or visit www.sun.com if you need additional information or // have any questions. // // ========== Copyright Header End ============================================ #ifndef INC__IOS_RASMON_IF_VRH #define INC__IOS_RASMON_IF_VRH #include "top_defines.vrh" interface sio_niu_err_mon { input clk CLOCK verilog_node "`CPU.sio.iol2clk"; input req PSAMPLE #-3 verilog_node "`CPU.sio_niu_hdr_vld"; input [127:0] data PSAMPLE #-3 verilog_node "`CPU.sio_niu_data"; input [7:0] parity PSAMPLE #-3 verilog_node "`CPU.sio_niu_parity"; input ctag_ce PSAMPLE #-3 verilog_node "`CPU.niu_ncu_ctag_ce"; input ctag_ue PSAMPLE #-3 verilog_node "`CPU.niu_ncu_ctag_ue"; input d_pe PSAMPLE #-3 verilog_node "`CPU.niu_ncu_d_pe"; } interface sio_dmu_err_mon { input clk CLOCK verilog_node "`CPU.sio.iol2clk"; input req PSAMPLE #-3 verilog_node "`CPU.sio_dmu_hdr_vld"; input [127:0] data PSAMPLE #-3 verilog_node "`CPU.sio_dmu_data"; input [7:0] parity PSAMPLE #-3 verilog_node "`CPU.sio_dmu_parity"; input ctag_ce PSAMPLE #-3 verilog_node "`CPU.dmu_ncu_ctag_ce"; input ctag_ue PSAMPLE #-3 verilog_node "`CPU.dmu_ncu_ctag_ue"; input d_pe PSAMPLE #-3 verilog_node "`CPU.dmu_ncu_d_pe"; } interface ncu_cpx_err_mon { input clk CLOCK verilog_node "`NCU.l2clk"; input [7:0] req PSAMPLE #-3 verilog_node "`NCU.ncu_cpx_req_cq"; input [145:0] data PSAMPLE #-3 verilog_node "`NCU.ncu_cpx_data_ca"; } #endif