// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: mac_reset_port.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
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// ========== Copyright Header End ============================================
#define OUTPUT_EDGE PHOLD
#define INPUT_EDGE PSAMPLE
#define OUTPUT_SKEW #1


interface top_level_iface {
 input         core_clock      CLOCK verilog_node 
               MAC_DUV_PATH.ht_top.core_clk";

 output         reset_l     OUTPUT_EDGE  OUTPUT_SKEW verilog_node
                MAC_DUV_PATH.reset_l";
} 


/****

 output        reset_core       OUTPUT_EDGE OUTPUT_SKEW verilog_node  
                MAC_DUV_PATH.ht_top.reset_core";

 output        pio_rd_wr       OUTPUT_EDGE OUTPUT_SKEW verilog_node
                MAC_DUV_PATH.ht_top.pio_rd_wr";

 output [8:0]  pio_reg_offset  OUTPUT_EDGE OUTPUT_SKEW  verilog_node
                MAC_DUV_PATH.ht_top.pio_reg_offset";

 output [31:0] pio_wr_data     OUTPUT_EDGE OUTPUT_SKEW  verilog_node
                MAC_DUV_PATH.ht_top.pio_wr_data";

 output [2:0]  bif_pio_rd_mux_sel  OUTPUT_EDGE OUTPUT_SKEW verilog_node 
                MAC_DUV_PATH.ht_top.bif_pio_rd_mux_sel";


 output        bif_mac0_core_sel  OUTPUT_EDGE OUTPUT_SKEW verilog_node 
                MAC_DUV_PATH.ht_top.bif_mac0_core_sel";

 output        bif_mac1_core_sel  OUTPUT_EDGE OUTPUT_SKEW verilog_node 
                MAC_DUV_PATH.ht_top.bif_mac1_core_sel";

 output        bif_mac2_core_sel  OUTPUT_EDGE OUTPUT_SKEW verilog_node 
                MAC_DUV_PATH.ht_top.bif_mac2_core_sel";

 output        bif_mac3_core_sel  OUTPUT_EDGE OUTPUT_SKEW verilog_node 
                MAC_DUV_PATH.ht_top.bif_mac3_core_sel";

***********/