// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ncu_stub.if.vrhpal
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#define OUTPUT_EDGE PHOLD
#define INPUT_EDGE PSAMPLE #-1
#define OUTPUT_SKEW #1

#include "neptune_defines.vri"
#define NCU_PIO_PATH NIU_DUV_PATH.rdp

#ifndef INC_NCU_STUB_IF_VRH
#define INC_NCU_STUB_IF_VRH


  interface ncu_stub {

#ifdef NIU_GATE
    input  clk CLOCK verilog_node NCU_PIO_PATH.iol2clk";
#else
#ifdef NIU_SYSTEMC_T2
    input  clk CLOCK verilog_node NIU_DUV_PATH.rdp_niu_pio_ucb_niu_clk";
#else
    input  clk CLOCK verilog_node NCU_PIO_PATH.niu_pio_ucb.niu_clk";
#endif
#endif

#ifdef NEPTUNE
    output  [31:0]  ncu_niu_data OUTPUT_EDGE OUTPUT_SKEW  verilog_node TOP.ncu_niu_data";
    output  ncu_niu_vld OUTPUT_EDGE OUTPUT_SKEW verilog_node TOP.ncu_niu_vld";
    input  niu_ncu_stall INPUT_EDGE verilog_node TOP.niu_ncu_stall";


    // NIU to NCU
    output  ncu_niu_stall OUTPUT_EDGE OUTPUT_SKEW verilog_node TOP.ncu_niu_stall";
    input  [31:0]  niu_ncu_data INPUT_EDGE verilog_node TOP.niu_ncu_data";
    input  niu_ncu_vld INPUT_EDGE verilog_node TOP.niu_ncu_vld";
#else
#ifdef NIU_SYSTEMC_T2
    output  [31:0]  ncu_niu_data OUTPUT_EDGE OUTPUT_SKEW  verilog_node NIU_DUV_PATH.dummy";
    output  ncu_niu_vld OUTPUT_EDGE OUTPUT_SKEW verilog_node NIU_DUV_PATH.dummy[0]";
    input  niu_ncu_stall INPUT_EDGE verilog_node NIU_DUV_PATH.dummy[1]";
    output  ncu_niu_stall OUTPUT_EDGE OUTPUT_SKEW verilog_node NIU_DUV_PATH.dummy[2]";
    input  [31:0]  niu_ncu_data INPUT_EDGE verilog_node NIU_DUV_PATH.niu_ncu_data";
    input  niu_ncu_vld INPUT_EDGE verilog_node NIU_DUV_PATH.niu_ncu_vld";
#else
    // NCU to NIU
    output  [31:0]  ncu_niu_data OUTPUT_EDGE OUTPUT_SKEW  verilog_node NCU_PIO_PATH.ncu_niu_data";
    output  ncu_niu_vld OUTPUT_EDGE OUTPUT_SKEW verilog_node NCU_PIO_PATH.ncu_niu_vld";
    input  niu_ncu_stall INPUT_EDGE verilog_node NCU_PIO_PATH.niu_ncu_stall";


    // NIU to NCU
    output  ncu_niu_stall OUTPUT_EDGE OUTPUT_SKEW verilog_node NCU_PIO_PATH.ncu_niu_stall";
    input  [31:0]  niu_ncu_data INPUT_EDGE verilog_node NCU_PIO_PATH.niu_ncu_data";
    input  niu_ncu_vld INPUT_EDGE verilog_node NCU_PIO_PATH.niu_ncu_vld";
#endif
#endif
  }  // end of interface ncu_stub

#endif

// ports and port binds -- to move to a different file

port ncu_port {

	clk;
	ncu_niu_data;
	ncu_niu_vld;
	niu_ncu_stall;

	ncu_niu_stall;
	niu_ncu_data;
	niu_ncu_vld;

}

bind ncu_port ncu_bind {

	clk 		ncu_stub.clk;


	ncu_niu_data 	ncu_stub.ncu_niu_data;
	ncu_niu_vld 	ncu_stub.ncu_niu_vld;
	niu_ncu_stall 	ncu_stub.niu_ncu_stall;

	ncu_niu_stall 	ncu_stub.ncu_niu_stall;
	niu_ncu_data 	ncu_stub.niu_ncu_data;
	niu_ncu_vld 	ncu_stub.niu_ncu_vld;


}