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// 
// OpenSPARC T2 Processor File: dmc_util.vr
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#include <vera_defines.vrh>
#include "dmc_memory_map.vri"
#include "pio_driver.vrh"
#include "niu_mem.vrh"
extern niu_gen_pio gen_pio_drv;
extern CSparseMem SparseMem;


//inclune "dmc_shadow_class.vrh"
#include "cMesg.vrh"

extern Mesg be_msg;

class dmc_util_class {

        task new( ) ;
        task dmc_init ();

}

task dmc_util_class::new( ) { } 


task dmc_util_class::dmc_init () {
bit [63:0] read_data;
integer status;
integer i;
bit [63:0] data;
bit [ 63:0] address;






                //gen_pio_drv.pio_wr(RXDMA_CFIG1,64'h0000_0000_8000_0000); //b31 DMA-EN
                //gen_pio_drv.pio_wr(RBR_CFIG_A,64'h00FF_0000_0000_0200);  // LEN FF , START ADDR 200
                ////gen_pio_drv.pio_wr(RBR_CFIG_B,64'h0000_0000_0080_8080);  //Set all 3 sizes S,M &L 
                //gen_pio_drv.pio_wr(RBR_CFIG_B,64'h0000_0000_0000_0080);  //Set all 3 sizes S,M &L 
                //gen_pio_drv.pio_wr(RX_LOG_PAGE_VLD,64'h0000_0000_0000_0003);// Logical Page0&1 valid
                //gen_pio_drv.pio_wr(RCRCFIG_A,64'h000F_0000_0000_0040);
                //gen_pio_drv.pio_wr(TBR_CFIG_A,64'h000F_0000_0000_0080);
                //gen_pio_drv.pio_wr(RBR_KICK,64'h0000_0000_0000_0128); //KICK 8 buffers
                gen_pio_drv.pio_wr(RBR_HDH,64'h0000_0000_0000_0200);
                gen_pio_drv.pio_wr(RBR_HDL,64'h0000_0000_0000_0006);
                //gen_pio_drv.pio_wr(RCR_CFIG_A,64'h00FF_0000_0004_0000);  // LEN FF , START ADDR 200



   	be_msg.print(e_mesg_info, "dmc_init", "dmc_pio_class","DMC INIT DONE\n");


}