// ========== Copyright Header Begin ========================================== // // OpenSPARC T2 Processor File: dmc_memory_map.vri // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved // 4150 Network Circle, Santa Clara, California 95054, U.S.A. // // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; version 2 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // // For the avoidance of doubt, and except that if any non-GPL license // choice is available it will apply instead, Sun elects to use only // the General Public License version 2 (GPLv2) at this time for any // software where a choice of GPL license versions is made // available with the language indicating that GPLv2 or any later version // may be used, or where a choice of which version of the GPL is applied is // otherwise unspecified. // // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, // CA 95054 USA or visit www.sun.com if you need additional information or // have any questions. // // ========== Copyright Header End ============================================ #include "neptune_memory_map.vri" #define RX_DMA_CK_DIV FZC_DMC_ADDRESS_RANGE+20'h00000 #define RDC_DEF_PT0_RDC FZC_DMC_ADDRESS_RANGE+20'h00008 #define RDC_DEF_PT1_RDC FZC_DMC_ADDRESS_RANGE+20'h00010 #define RDC_DEF_PT2_RDC FZC_DMC_ADDRESS_RANGE+20'h00018 #define RDC_DEF_PT3_RDC FZC_DMC_ADDRESS_RANGE+20'h00020 #define RDC_TABLE_BASE FZC_DMC_ADDRESS_RANGE+20'h10000 #define RX_LOG_PAGE_VLD FZC_DMC_ADDRESS_RANGE+20'h20000 #define RX_LOG_STEP 'h40 #define RX_LOG_PAGE1 FZC_DMC_ADDRESS_RANGE+20'h20008 #define RX_LOG_PAGE2 FZC_DMC_ADDRESS_RANGE+20'h20010 #define RX_LOG_PAGE_MASK1 FZC_DMC_ADDRESS_RANGE+20'h20008 #define RX_LOG_PAGE_MASK2 FZC_DMC_ADDRESS_RANGE+20'h20010 #define RX_LOG_PAGE_VALUE1 FZC_DMC_ADDRESS_RANGE+20'h20018 #define RX_LOG_PAGE_VALUE2 FZC_DMC_ADDRESS_RANGE+20'h20020 #define RX_LOG_PAGE_RELO1 FZC_DMC_ADDRESS_RANGE+20'h20028 #define RX_LOG_PAGE_RELO2 FZC_DMC_ADDRESS_RANGE+20'h20030 #define RX_LOG_PAGE_HDL FZC_DMC_ADDRESS_RANGE+20'h20038 #define RDC_RED_PARA FZC_DMC_ADDRESS_RANGE+20'h30000 #define RDC_RED_STEP 'h10 //#define RXDMA_CFIG_BASE DMC_ADDRESS_RANGE+20'h00000 #define RXDMA_CFIG1 DMC_ADDRESS_RANGE+20'h00000 #define RXDMA_CFIG2 DMC_ADDRESS_RANGE+20'h00008 #define RBR_CFIG_A DMC_ADDRESS_RANGE+20'h00010 #define RBR_CFIG_B DMC_ADDRESS_RANGE+20'h00018 #define RBR_KICK DMC_ADDRESS_RANGE+20'h00020 #define RBR_STAT DMC_ADDRESS_RANGE+20'h00028 #define RBR_HD DMC_ADDRESS_RANGE+20'h00030 #define RCR_CFIG_A DMC_ADDRESS_RANGE+20'h00040 #define RCR_CFIG_B DMC_ADDRESS_RANGE+20'h00048 #define RCR_STAT_A DMC_ADDRESS_RANGE+20'h00050 #define RCR_STAT_C DMC_ADDRESS_RANGE+20'h00058 #define RCR_STAT_D DMC_ADDRESS_RANGE+20'h00060 #define TBR_CFIG_A DMC_ADDRESS_RANGE+20'h10000 #define RBR_HDH DMC_ADDRESS_RANGE+20'h00030 #define RBR_HDL DMC_ADDRESS_RANGE+20'h00038 /* #define TX_RING_HD DMC_ADDRESS_RANGE+20'h40008 #define TX_RING_KICK DMC_ADDRESS_RANGE+20'h40010 #define TXDMA_CFG DMC_ADDRESS_RANGE+20'h40018 */ #define TX_RNG_CFIG DMC_ADDRESS_RANGE+20'h40000 #define TX_RING_HDH DMC_ADDRESS_RANGE+20'h40008 #define TX_RING_HDL DMC_ADDRESS_RANGE+20'h40010 #define TX_RING_KICK DMC_ADDRESS_RANGE+20'h40018 #define TX_ENT_MASK DMC_ADDRESS_RANGE+20'h40020 #define TX_CS DMC_ADDRESS_RANGE+20'h40028 #define TXDMA_MBH DMC_ADDRESS_RANGE+20'h40030 #define TXDMA_MBL DMC_ADDRESS_RANGE+20'h40038 #define TX_DMA_PRE_ST DMC_ADDRESS_RANGE+20'h40040 #define TX_RNG_ERR_LOGH DMC_ADDRESS_RANGE+20'h40048 #define TX_RNG_ERR_LOGL DMC_ADDRESS_RANGE+20'h40050 #define TDMC_INTR_DBG DMC_ADDRESS_RANGE+20'h40060 #define TX_CS_DBG DMC_ADDRESS_RANGE+20'h40068 #define TX_LOG_PAGE_VLD FZC_DMC_ADDRESS_RANGE+20'h40000 #define TX_LOG_MASK1 FZC_DMC_ADDRESS_RANGE+20'h40008 #define TX_LOG_VALUE1 FZC_DMC_ADDRESS_RANGE+20'h40010 #define TX_LOG_MASK2 FZC_DMC_ADDRESS_RANGE+20'h40018 #define TX_LOG_VALUE2 FZC_DMC_ADDRESS_RANGE+20'h40020 #define TX_LOG_PAGE_RELO1 FZC_DMC_ADDRESS_RANGE+20'h40028 #define TX_LOG_PAGE_RELO2 FZC_DMC_ADDRESS_RANGE+20'h40030 #define TX_LOG_PAGE_HDL FZC_DMC_ADDRESS_RANGE+20'h40038 #define TDMC_INJ_PAR_ERR FZC_DMC_ADDRESS_RANGE+20'h45040 #define TDMC_DBG_SEL FZC_DMC_ADDRESS_RANGE+20'h45080 #define TDMC_TRAIN_VEC FZC_DMC_ADDRESS_RANGE+20'h45088 #define TX_DMA_MAP0 FZC_DMC_ADDRESS_RANGE+20'h50000 #define TX_DMA_MAP1 FZC_DMC_ADDRESS_RANGE+20'h50008 #define TX_DMA_MAP2 FZC_DMC_ADDRESS_RANGE+20'h50010 #define TX_DMA_MAP3 FZC_DMC_ADDRESS_RANGE+20'h50018 #define TXDMA_DUMMY DMC_ADDRESS_RANGE+20'h40040 // ################################################################################ // ALL RDMC Registers #defined. Not using hard numbers anywhere in the tests/env. // ################################################################################ #define DEF_PTO_RDC FZC_DMC_ADDRESS_RANGE+20'h00008 #define DEF_PT1_RDC FZC_DMC_ADDRESS_RANGE+20'h00010 #define DEF_PT2_RDC FZC_DMC_ADDRESS_RANGE+20'h00018 #define DEF_PT3_RDC FZC_DMC_ADDRESS_RANGE+20'h00020 #define RDC_TBL_START FZC_DMC_ADDRESS_RANGE+20'h10000 #define RDC_TBL_END FZC_DMC_ADDRESS_RANGE+20'h107f8 #define RDC_TBL_STEP 8 #define RX_ADDR_MD FZC_DMC_ADDRESS_RANGE+20'h00070 #define PT_DRR_WT0 FZC_DMC_ADDRESS_RANGE+20'h00028 #define PT_DRR_WT1 FZC_DMC_ADDRESS_RANGE+20'h00030 #define PT_DRR_WT2 FZC_DMC_ADDRESS_RANGE+20'h00038 #define PT_DRR_WT3 FZC_DMC_ADDRESS_RANGE+20'h00040 #define PT_USE0 FZC_DMC_ADDRESS_RANGE+20'h00048 #define PT_USE1 FZC_DMC_ADDRESS_RANGE+20'h00050 #define PT_USE2 FZC_DMC_ADDRESS_RANGE+20'h00058 #define PT_USE3 FZC_DMC_ADDRESS_RANGE+20'h00060 #define RX_LOG_PAGE_VLD_START FZC_DMC_ADDRESS_RANGE+20'h20000 #define RX_LOG_PAGE_VLD_END FZC_DMC_ADDRESS_RANGE+20'h203c0 #define RX_LOG_PAGE_VLD_STEP 8'h40 #define RX_LOG_MASK1_START FZC_DMC_ADDRESS_RANGE+20'h20008 #define RX_LOG_MASK1_END FZC_DMC_ADDRESS_RANGE+20'h203c8 #define RX_LOG_MASK1_STEP 8'h40 #define RX_LOG_VAL1_START FZC_DMC_ADDRESS_RANGE+20'h20010 #define RX_LOG_VAL1_END FZC_DMC_ADDRESS_RANGE+20'h203d0 #define RX_LOG_VAL1_STEP 8'h40 #define RX_LOG_MASK2_START FZC_DMC_ADDRESS_RANGE+20'h20018 #define RX_LOG_MASK2_END FZC_DMC_ADDRESS_RANGE+20'h203d8 #define RX_LOG_MASK2_STEP 8'h40 #define RX_LOG_VAL2_START FZC_DMC_ADDRESS_RANGE+20'h20020 #define RX_LOG_VAL2_END FZC_DMC_ADDRESS_RANGE+20'h203e0 #define RX_LOG_VAL2_STEP 8'h40 #define RX_LOG_RELO1_START FZC_DMC_ADDRESS_RANGE+20'h20028 #define RX_LOG_RELO1_END FZC_DMC_ADDRESS_RANGE+20'h203e8 #define RX_LOG_RELO1_STEP 8'h40 #define RX_LOG_RELO2_START FZC_DMC_ADDRESS_RANGE+20'h20030 #define RX_LOG_RELO2_END FZC_DMC_ADDRESS_RANGE+20'h203f0 #define RX_LOG_RELO2_STEP 8'h40 #define RX_LOG_PAGE_HDL_START FZC_DMC_ADDRESS_RANGE+20'h20038 #define RX_LOG_PAGE_HDL_END FZC_DMC_ADDRESS_RANGE+20'h203f8 #define RX_LOG_PAGE_HDL_STEP 8'h40 #define RED_RAN_INIT FZC_DMC_ADDRESS_RANGE+20'h00068 #define RDC_RED_PARA_START FZC_DMC_ADDRESS_RANGE+20'h30000 #define RDC_RED_PARA_END FZC_DMC_ADDRESS_RANGE+20'h303c0 #define RDC_RED_PARA_STEP 8'h40 #define RED_DIS_CNT_START FZC_DMC_ADDRESS_RANGE+20'h30008 #define RED_DIS_CNT_END FZC_DMC_ADDRESS_RANGE+20'h303c8 #define RED_DIS_CNT_STEP 8'h40 #define RXDMA_CFIG1_START DMC_ADDRESS_RANGE+20'h00000 #define RXDMA_CFIG1_END DMC_ADDRESS_RANGE+20'h01e00 #define RXDMA_CFIG2_START DMC_ADDRESS_RANGE+20'h00008 #define RXDMA_CFIG2_END DMC_ADDRESS_RANGE+20'h01e08 #define RBR_CFIG_A_START DMC_ADDRESS_RANGE+20'h00010 #define RBR_CFIG_A_END DMC_ADDRESS_RANGE+20'h01e10 #define RBR_CFIG_B_START DMC_ADDRESS_RANGE+20'h00018 #define RBR_CFIG_B_END DMC_ADDRESS_RANGE+20'h01e18 #define RBR_KICK_START DMC_ADDRESS_RANGE+20'h00020 #define RBR_KICK_END DMC_ADDRESS_RANGE+20'h01e20 #define RBR_STAT_START DMC_ADDRESS_RANGE+20'h00028 #define RBR_STAT_END DMC_ADDRESS_RANGE+20'h01e28 #define RBR_HDH_START DMC_ADDRESS_RANGE+20'h00030 #define RBR_HDH_END DMC_ADDRESS_RANGE+20'h01e30 #define RBR_HDL_START DMC_ADDRESS_RANGE+20'h00038 #define RBR_HDL_END DMC_ADDRESS_RANGE+20'h01e38 #define RCR_CFIG_A_START DMC_ADDRESS_RANGE+20'h00040 #define RCR_CFIG_A_END DMC_ADDRESS_RANGE+20'h01e40 #define RCR_CFIG_B_START DMC_ADDRESS_RANGE+20'h00048 #define RCR_CFIG_B_END DMC_ADDRESS_RANGE+20'h01e48 #define RCR_STAT_A_START DMC_ADDRESS_RANGE+20'h00050 #define RCR_STAT_A_END DMC_ADDRESS_RANGE+20'h01e50 #define RCR_STAT_B_START DMC_ADDRESS_RANGE+20'h00058 #define RCR_STAT_B_END DMC_ADDRESS_RANGE+20'h01e58 #define RCR_STAT_C_START DMC_ADDRESS_RANGE+20'h00060 #define RCR_STAT_C_END DMC_ADDRESS_RANGE+20'h01e60 #define RX_DMA_ENT_MSK_START DMC_ADDRESS_RANGE+20'h00068 #define RX_DMA_ENT_MSK_END DMC_ADDRESS_RANGE+20'h01e68 #define RX_DMA_CTL_STAT_START DMC_ADDRESS_RANGE+20'h00070 #define RX_DMA_CTL_STAT_END DMC_ADDRESS_RANGE+20'h01e70 #define RCR_FLUSH_START DMC_ADDRESS_RANGE+20'h00078 #define RCR_FLUSH_END DMC_ADDRESS_RANGE+20'h01e78 #define RX_DMA_LOGA_START DMC_ADDRESS_RANGE+20'h00080 #define RX_DMA_LOGA_END DMC_ADDRESS_RANGE+20'h01e80 #define RX_DMA_LOGB_START DMC_ADDRESS_RANGE+20'h00088 #define RX_DMA_LOGB_END DMC_ADDRESS_RANGE+20'h01e88 #define RX_MISC_START DMC_ADDRESS_RANGE+20'h00090 #define RX_MISC_END DMC_ADDRESS_RANGE+20'h01e90 #define RDC_PRE_EMPTY_START DMC_ADDRESS_RANGE+20'h000b0 #define RDC_PRE_EMPTY_END DMC_ADDRESS_RANGE+20'h01eb0 #define RX_DMA_INTR_DEBUG_START DMC_ADDRESS_RANGE+20'h00098 #define RX_DMA_INTR_DEBUG_END DMC_ADDRESS_RANGE+20'h01e98 #define RXDMA_STEP 12'h200 #define RDMC_PRE_PAR_ERR FZC_DMC_ADDRESS_RANGE+20'h00078 #define RDMC_SHA_PAR_ERR FZC_DMC_ADDRESS_RANGE+20'h00080 #define RDMC_MEM_ADDR FZC_DMC_ADDRESS_RANGE+20'h00088 #define RDMC_MEM_DAT0 FZC_DMC_ADDRESS_RANGE+20'h00090 #define RDMC_MEM_DAT1 FZC_DMC_ADDRESS_RANGE+20'h00098 #define RDMC_MEM_DAT2 FZC_DMC_ADDRESS_RANGE+20'h000a0 #define RDMC_MEM_DAT3 FZC_DMC_ADDRESS_RANGE+20'h000a8 #define RDMC_MEM_DAT4 FZC_DMC_ADDRESS_RANGE+20'h000b0 #define RX_CTL_DAT_FIFO_MASK FZC_DMC_ADDRESS_RANGE+20'h000c0 #define RX_CTL_DAT_FIFO_STAT FZC_DMC_ADDRESS_RANGE+20'h000b8 #define RX_CTL_DAT_FIFO_STAT_DBG FZC_DMC_ADDRESS_RANGE+20'h000d0 #define RDMC_TRAINING_VECTOR FZC_DMC_ADDRESS_RANGE+20'h000c8 // RDMC Register Bit definitions // RX_DMA_ENT_MSK Register #define RX_DMA_ENT_MSK_RBR_TMOUT 21 #define RX_DMA_ENT_MSK_RSP_CNT_ERR 20 #define RX_DMA_ENT_MSK_BYTE_EN_BUS 19 #define RX_DMA_ENT_MSK_RSP_DAT_ERR 18 #define RX_DMA_ENT_MSK_RCR_ACK_ERR 17 #define RX_DMA_ENT_MSK_DC_FIFO_ERR 16 #define RX_DMA_ENT_MSK_RCRTHRES 14 #define RX_DMA_ENT_MSK_RCRTO 13 #define RX_DMA_ENT_MSK_RCR_SHA_PAR 12 #define RX_DMA_ENT_MSK_RBR_PRE_PAR 11 #define RX_DMA_ENT_MSK_PORT_DROP_PKT 10 #define RX_DMA_ENT_MSK_WRED_DROP 9 #define RX_DMA_ENT_MSK_RBR_PRE_EMTY 8 #define RX_DMA_ENT_MSK_RCR_SHADOW_FULL 7 #define RX_DMA_ENT_MSK_CONFIG_ERR 6 #define RX_DMA_ENT_MSK_RCRINCON 5 #define RX_DMA_ENT_MSK_RCRFULL 4 #define RX_DMA_ENT_MSK_RBR_EMPTY 3 #define RX_DMA_ENT_MSK_RBRFULL 2 #define RX_DMA_ENT_MSK_RBRLOGPAGE 1 #define RX_DMA_ENT_MSK_CFIGLOGPAGE 0 // RX_DMA_CTL_STAT Register #define RX_DMA_CTL_STAT_RBR_TMOUT 53 #define RX_DMA_CTL_STAT_RSP_CNT_ERR 52 #define RX_DMA_CTL_STAT_BYTE_EN_BUS 51 #define RX_DMA_CTL_STAT_RSP_DAT_ERR 50 #define RX_DMA_CTL_STAT_RCR_ACK_ERR 49 #define RX_DMA_CTL_STAT_DC_FIFO_ERR 48 #define RX_DMA_CTL_STAT_MEX 47 #define RX_DMA_CTL_STAT_RCRTHRES 46 #define RX_DMA_CTL_STAT_RCRTO 45 #define RX_DMA_CTL_STAT_RCR_SHA_PAR 44 #define RX_DMA_CTL_STAT_RBR_PRE_PAR 43 #define RX_DMA_CTL_STAT_PORT_DROP_PKT 42 #define RX_DMA_CTL_STAT_WRED_DROP 41 #define RX_DMA_CTL_STAT_RBR_PRE_EMTY 40 #define RX_DMA_CTL_STAT_RCR_SHADOW_FULL 39 #define RX_DMA_CTL_STAT_CONFIG_ERR 38 #define RX_DMA_CTL_STAT_RCRINCON 37 #define RX_DMA_CTL_STAT_RCRFULL 36 #define RX_DMA_CTL_STAT_RBR_EMPTY 35 #define RX_DMA_CTL_STAT_RBRFULL 34 #define RX_DMA_CTL_STAT_RBRLOGPAGE 33 #define RX_DMA_CTL_STAT_CFIGLOGPAGE 32 #define RX_DMA_CTL_STAT_PTRREAD 31:16 #define RX_DMA_CTL_STAT_PKTREAD 15:0 // RX_DMA_INTR_DEBUG Register #define RX_DMA_INTR_DEBUG_RBR_TMOUT 53 #define RX_DMA_INTR_DEBUG_RSP_CNT_ERR 52 #define RX_DMA_INTR_DEBUG_BYTE_EN_BUS 51 #define RX_DMA_INTR_DEBUG_RSP_DAT_ERR 50 #define RX_DMA_INTR_DEBUG_RCR_ACK_ERR 49 #define RX_DMA_INTR_DEBUG_DC_FIFO_ERR 48 #define RX_DMA_INTR_DEBUG_MEX 47 #define RX_DMA_INTR_DEBUG_RCRTHRES 46 #define RX_DMA_INTR_DEBUG_RCRTO 45 #define RX_DMA_INTR_DEBUG_RCR_SHA_PAR 44 #define RX_DMA_INTR_DEBUG_RBR_PRE_PAR 43 #define RX_DMA_INTR_DEBUG_PORT_DROP_PKT 42 #define RX_DMA_INTR_DEBUG_WRED_DROP 41 #define RX_DMA_INTR_DEBUG_RBR_PRE_EMTY 40 #define RX_DMA_INTR_DEBUG_RCR_SHADOW_FULL 39 #define RX_DMA_INTR_DEBUG_CONFIG_ERR 38 #define RX_DMA_INTR_DEBUG_RCRINCON 37 #define RX_DMA_INTR_DEBUG_RCRFULL 36 #define RX_DMA_INTR_DEBUG_RBR_EMPTY 35 #define RX_DMA_INTR_DEBUG_RBRFULL 34 #define RX_DMA_INTR_DEBUG_RBRLOGPAGE 33 #define RX_DMA_INTR_DEBUG_CFIGLOGPAGE 32 #define RX_DMA_INTR_DEBUG_PTRREAD 31:16 #define RX_DMA_INTR_DEBUG_PKTREAD 15:0 #define RX_ADDR_MD_RAM_ACC 1 #define RDMC_MEM_ADDR_PRE_SHAD 8 #define RDMC_MEM_ADDR_PRE_ADDR 7:0