// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ipp_memory_map.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
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// ========== Copyright Header End ============================================
#include "neptune_memory_map.vri"

#define IPP_PORT_STEP                   16'h8000


#define IPP_CONFIG                      20'h0_0000
#define IPP_DISCARD_PKT_COUNTER         20'h0_0020
#define IPP_TCP_CHKSUM_ERR_COUNTER      20'h0_0028
#define IPP_ECC_ERR_COUNTER             20'h0_0030

// ox24 to ox34 are reserved for any new counters

#define IPP_INT_STATUS                  20'h0_0040
#define IPP_INT_MASK                    20'h0_0048

// 0x40 to 0x44 are reserved for future use

#define IPP_FIFO_RD_DATA_31_0           20'h0_0060
#define IPP_FIFO_RD_DATA_63_32          20'h0_0068
#define IPP_FIFO_RD_DATA_95_64          20'h0_0070
#define IPP_FIFO_RD_DATA_127_96         20'h0_0078
#define IPP_FIFO_RD_DATA_129_128        20'h0_0080

#define IPP_FIFO_WR_DATA_31_0           20'h0_0088
#define IPP_FIFO_WR_DATA_63_32          20'h0_0090
#define IPP_FIFO_WR_DATA_95_64          20'h0_0098
#define IPP_FIFO_WR_DATA_127_96         20'h0_00a0
#define IPP_FIFO_WR_DATA_129_128        20'h0_00a8

#define IPP_FIFO_READ_POINTER           20'h0_00b0
#define IPP_FIFO_WRITE_POINTER          20'h0_00b8

//#define IPP_POINTER_QUEUE0              20'h0_00c0
//#define IPP_POINTER_QUEUE1              20'h0_00c8
//#define IPP_POINTER_QUEUE2              20'h0_00d0
//#define IPP_POINTER_QUEUE3              20'h0_00d8
//#define IPP_POINTER_QUEUE4              20'h0_00e0
//#define IPP_POINTER_QUEUE5              20'h0_00e8
//#define IPP_POINTER_QUEUE6              20'h0_00f0
//#define IPP_POINTER_QUEUE7              20'h0_00f8

#define IPP_STATE_MACHINE0              20'h0_0080
#define IPP_STATE_MACHINE1              20'h0_0084


// 0x88 to 0x90 are added for fflp decision bypass
#define IPP_DECISION_REG1               20'h0_0110
#define IPP_DECISION_REG2               20'h0_0118
#define IPP_DECISION_REG3               20'h0_0120
#define IPP_DEBUG_REG                   20'h0_0128


// more defines for IPP
#define IPP_DFIFO_RD_PTR		20'h0_0110
#define IPP_DFIFO_WR_PTR		20'h0_0118

// BASE ADDRESS FOR EACH IPP BLOCK

#define IPP0_BASE       (IPP_ADDRESS_RANGE + IPP_0_RANGE)
#define IPP1_BASE       (IPP_ADDRESS_RANGE + IPP_1_RANGE)
#define IPP2_BASE       (IPP_ADDRESS_RANGE + IPP_2_RANGE)
#define IPP3_BASE       (IPP_ADDRESS_RANGE + IPP_3_RANGE)

// BIT DEFINES FOR IPP_INT_STAT AND IPP_INT_MSK REGISTERS

#define IPP_MASK_ECC_ERR_MX 	7
#define IPP_MASK_DFIFO_EOP_SOP 	6
#define IPP_MASK_DFIFO_UC 	5
#define IPP_MASK_PFIFO_PAR 	4
#define IPP_MASK_PFIFO_OVER 	3
#define IPP_MASK_PFIFO_UND 	2
#define IPP_MASK_BAD_CS 	1
#define IPP_MASK_PKT_DIS_CNT 	0

#define IPP_STAT_SOP_MISS 	31	// corresponds to MASK 6
#define IPP_STAT_EOP_MISS 	30	// corresponds to MASK 6
#define IPP_STAT_DFIFO_UE 	29:28	// corresponds to MASK 5
#define IPP_STAT_DFIFO_CE 	27:26
#define IPP_STAT_DFIFO_ECC 	25:24
#define IPP_STAT_DFIFO_ECC_ID 	22:12
#define IPP_STAT_PFIFO_PERR 	11	// corresponds to MASK 4
#define IPP_STAT_ECC_ERR_MA 	10	// corresponds to MASK 7
#define IPP_STAT_PFIFO_ERR_ID 	9:4
#define IPP_STAT_PFIFO_OVER 	3	// corresponds to MASK 3
#define IPP_STAT_PFIFO_UND 	2	// corresponds to MASK 2
#define IPP_STAT_BAD_CS_MX 	1	// corresponds to MASK 1
#define IPP_STAT_PKT_DIS_MX 	0	// corresponds to MASK 0