// ========== Copyright Header Begin ========================================== // // OpenSPARC T2 Processor File: mbox_defines.vri // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved // 4150 Network Circle, Santa Clara, California 95054, U.S.A. // // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; version 2 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // // For the avoidance of doubt, and except that if any non-GPL license // choice is available it will apply instead, Sun elects to use only // the General Public License version 2 (GPLv2) at this time for any // software where a choice of GPL license versions is made // available with the language indicating that GPLv2 or any later version // may be used, or where a choice of which version of the GPL is applied is // otherwise unspecified. // // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, // CA 95054 USA or visit www.sun.com if you need additional information or // have any questions. // // ========== Copyright Header End ============================================ #define IAM_MAC_IPP_CHKR 8'h00 #define IAM_IPP_DMC_CHKR 8'h01 #define IAM_NTX_MAC_CHKR 8'h02 #define IAM_RDMC_WR_CHKR 8'h03 // FFLP #define IAM_FFLP_CAM_MBOX 8'h10 #define IAM_CAM_RAM_MBOX 8'h11 #define IAM_RAM_IPP_MBOX 8'h12 #define IAM_RAM_BMC_MBOX 8'h13 #define IAM_BMC_CAM_RAM_MBOX 8'h14 #define IAM_FFLP_IPP_MBOX 8'h15 #define IAM_RAM_CAM_MBOX 8'h16 #define IAM_FFLP_CAM_V4_MBOX 8'h17 #define IAM_FFLP_CAM_V6_MBOX 8'h18 // IPP #define IAM_PG_IPP_MBOX 8'h20 #define IAM_IPP_FFL_MBOX 8'h21 //IPP #define IAM_NRX_FFL_CHK_MBOX 8'h80 //TX DMA #define IAM_TXC_DMA0_MBOX 8'h90 #define IAM_TXC_DMA1_MBOX 8'h91 #define IAM_TXC_DMA2_MBOX 8'h92 #define IAM_TXC_DMA3_MBOX 8'h93 #define IAM_TXC_DMA4_MBOX 8'h94 #define IAM_TXC_DMA5_MBOX 8'h95 #define IAM_TXC_DMA6_MBOX 8'h96 #define IAM_TXC_DMA7_MBOX 8'h97 #define IAM_TXC_DMA8_MBOX 8'h98 #define IAM_TXC_DMA9_MBOX 8'h99 #define IAM_TXC_DMA10_MBOX 8'h9a #define IAM_TXC_DMA11_MBOX 8'h9b #define IAM_TXC_DMA12_MBOX 8'h9c #define IAM_TXC_DMA13_MBOX 8'h9d #define IAM_TXC_DMA14_MBOX 8'h9e #define IAM_TXC_DMA15_MBOX 8'h9f #define IAM_TXC_DMA16_MBOX 8'ha0 #define IAM_TXC_DMA17_MBOX 8'ha1 #define IAM_TXC_DMA18_MBOX 8'ha2 #define IAM_TXC_DMA19_MBOX 8'ha3 #define IAM_TXC_DMA20_MBOX 8'ha4 #define IAM_TXC_DMA21_MBOX 8'ha5 #define IAM_TXC_DMA22_MBOX 8'ha6 #define IAM_TXC_DMA23_MBOX 8'ha7 #define IAM_TXC_DMA24_MBOX 8'ha8 #define IAM_TXC_DMA25_MBOX 8'ha9 #define IAM_TXC_DMA26_MBOX 8'haa #define IAM_TXC_DMA27_MBOX 8'hab #define IAM_TXC_DMA28_MBOX 8'hac #define IAM_TXC_DMA29_MBOX 8'had #define IAM_TXC_DMA30_MBOX 8'hae #define IAM_TXC_DMA31_MBOX 8'haf