// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: niu_rxc_mon.if.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
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// ========== Copyright Header End ============================================
#ifdef NIU_GATE
  //   Do nothing
#else

#ifndef NIU_RXC_IF
#define NIU_RXC_IF

#define OUTPUT_EDGE     PHOLD
#define INPUT_EDGE      PSAMPLE #-1
#define OUTPUT_SKEW     #1

#define NIU_RXC_PATH      NIU_DUV_PATH.rtx.rxc

interface mac_ipp_ports_if
{
  input         clk                         CLOCK      verilog_node NIU_RXC_PATH.niu_clk";

  input         rxc_mac_req0                INPUT_EDGE verilog_node NIU_RXC_PATH.rxc_mac_req0";
  input         mac_rxc_tag0                INPUT_EDGE verilog_node NIU_RXC_PATH.mac_rxc_tag0";
  input         mac_rxc_ack0                INPUT_EDGE verilog_node NIU_RXC_PATH.mac_rxc_ack0";
  input [63:0]  mac_rxc_data0               INPUT_EDGE verilog_node NIU_RXC_PATH.mac_rxc_data0";
  input         mac_rxc_ctrl0               INPUT_EDGE verilog_node NIU_RXC_PATH.mac_rxc_ctrl0";
  input [22:0]  mac_rxc_stat0               INPUT_EDGE verilog_node NIU_RXC_PATH.mac_rxc_stat0";

  input         rxc_mac_req1                INPUT_EDGE verilog_node NIU_RXC_PATH.rxc_mac_req1";
  input         mac_rxc_tag1                INPUT_EDGE verilog_node NIU_RXC_PATH.mac_rxc_tag1";
  input         mac_rxc_ack1                INPUT_EDGE verilog_node NIU_RXC_PATH.mac_rxc_ack1";
  input [63:0]  mac_rxc_data1               INPUT_EDGE verilog_node NIU_RXC_PATH.mac_rxc_data1";
  input         mac_rxc_ctrl1               INPUT_EDGE verilog_node NIU_RXC_PATH.mac_rxc_ctrl1";
  input [22:0]  mac_rxc_stat1               INPUT_EDGE verilog_node NIU_RXC_PATH.mac_rxc_stat1";

}

port mac_ipp_port
{
  clk;
  req;
  tag;
  ack;
  data;
  ctrl;
  stat;
}

bind mac_ipp_port mac_ipp_port0_bind
{
  clk          mac_ipp_ports_if.clk;
  req          mac_ipp_ports_if.rxc_mac_req0;
  tag          mac_ipp_ports_if.mac_rxc_tag0;
  ack          mac_ipp_ports_if.mac_rxc_ack0;
  data         mac_ipp_ports_if.mac_rxc_data0;
  ctrl         mac_ipp_ports_if.mac_rxc_ctrl0;
  stat         mac_ipp_ports_if.mac_rxc_stat0;
}

bind mac_ipp_port mac_ipp_port1_bind
{
  clk          mac_ipp_ports_if.clk;
  req          mac_ipp_ports_if.rxc_mac_req1;
  tag          mac_ipp_ports_if.mac_rxc_tag1;
  ack          mac_ipp_ports_if.mac_rxc_ack1;
  data         mac_ipp_ports_if.mac_rxc_data1;
  ctrl         mac_ipp_ports_if.mac_rxc_ctrl1;
  stat         mac_ipp_ports_if.mac_rxc_stat1;
}


#endif  // NIU_RXC_IF
#endif	// if NIU_GATE... else...endif

// End