// ========== Copyright Header Begin ========================================== // // OpenSPARC T2 Processor File: siu_chk_ports.vri // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved // 4150 Network Circle, Santa Clara, California 95054, U.S.A. // // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; version 2 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // // For the avoidance of doubt, and except that if any non-GPL license // choice is available it will apply instead, Sun elects to use only // the General Public License version 2 (GPLv2) at this time for any // software where a choice of GPL license versions is made // available with the language indicating that GPLv2 or any later version // may be used, or where a choice of which version of the GPL is applied is // otherwise unspecified. // // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, // CA 95054 USA or visit www.sun.com if you need additional information or // have any questions. // // ========== Copyright Header End ============================================ #include "neptune_defines.vri" /* Port defines for SIU Stub interface to NIU for checkers */ #define OUTPUT_EDGE PHOLD #define INPUT_EDGE PSAMPLE #-1 #define OUTPUT_SKEW #1 #ifdef NIU_GATE interface niu_siu_chk { input clk CLOCK verilog_node TDS_DUV_PATH.iol2clk"; input niu_sii_hdr_vld INPUT_EDGE verilog_node TDS_DUV_PATH.niu_sii_hdr_vld"; // Ethernet requesting to send packet to SIU input niu_sii_reqbypass INPUT_EDGE verilog_node TDS_DUV_PATH.niu_sii_reqbypass"; // Ethernet requesting to send packet to bypass queue of SIU input niu_sii_datareq INPUT_EDGE verilog_node TDS_DUV_PATH.niu_sii_datareq"; // Ethernet requesting to send packet w/data to SIU input [127:0] niu_sii_data INPUT_EDGE verilog_node TDS_DUV_PATH.niu_sii_data"; // Packet from Ethernet to SIU input [7:0] niu_sii_parity INPUT_EDGE verilog_node TDS_DUV_PATH.niu_sii_parity"; // Packet parity from Ethernet to SIU input niu_reset_l INPUT_EDGE verilog_node TDS_DUV_PATH.rst_por_" ; // Asserted when SIU dqs an NIU entry from Ordered Queue VJH input sii_niu_oqdq INPUT_EDGE verilog_node TDS_DUV_PATH.sii_niu_oqdq" ; // Asserted when SIU dqs an NIU entry from Ordered Queue input sii_niu_bqdq INPUT_EDGE verilog_node TDS_DUV_PATH.sii_niu_bqdq" ; // Asserted when SIU dqs an NIU entry from Bypass Queue input sio_niu_hdr_vld INPUT_EDGE verilog_node TDS_DUV_PATH.sio_niu_hdr_vld" ; // SIO requesting to send packet to Ethernet input sio_niu_datareq INPUT_EDGE verilog_node TDS_DUV_PATH.sio_niu_datareq" ; // Valid during header phase only - 1=current request is a read data return input [127:0] sio_niu_data INPUT_EDGE verilog_node TDS_DUV_PATH.sio_niu_data" ; // Packet from SIO to Ethernet input [7:0] sio_niu_parity INPUT_EDGE verilog_node TDS_DUV_PATH.sio_niu_parity" ; // Packet parity from SIO to Ethernet } #else interface niu_siu_chk { input clk CLOCK verilog_node TDS_DUV_PATH.niu_smx.niu_clk"; input niu_sii_hdr_vld INPUT_EDGE verilog_node TDS_DUV_PATH.niu_sii_hdr_vld"; // Ethernet requesting to send packet to SIU input niu_sii_reqbypass INPUT_EDGE verilog_node TDS_DUV_PATH.niu_sii_reqbypass"; // Ethernet requesting to send packet to bypass queue of SIU input niu_sii_datareq INPUT_EDGE verilog_node TDS_DUV_PATH.niu_sii_datareq"; // Ethernet requesting to send packet w/data to SIU input [127:0] niu_sii_data INPUT_EDGE verilog_node TDS_DUV_PATH.niu_sii_data"; // Packet from Ethernet to SIU input [7:0] niu_sii_parity INPUT_EDGE verilog_node TDS_DUV_PATH.niu_sii_parity"; // Packet parity from Ethernet to SIU input niu_reset_l INPUT_EDGE verilog_node TDS_DUV_PATH.niu_smx.niu_reset_l" ; // Asserted when SIU dqs an NIU entry from Ordered Queue input sii_niu_oqdq INPUT_EDGE verilog_node TDS_DUV_PATH.sii_niu_oqdq" ; // Asserted when SIU dqs an NIU entry from Ordered Queue input sii_niu_bqdq INPUT_EDGE verilog_node TDS_DUV_PATH.sii_niu_bqdq" ; // Asserted when SIU dqs an NIU entry from Bypass Queue input sio_niu_hdr_vld INPUT_EDGE verilog_node TDS_DUV_PATH.sio_niu_hdr_vld" ; // SIO requesting to send packet to Ethernet input sio_niu_datareq INPUT_EDGE verilog_node TDS_DUV_PATH.sio_niu_datareq" ; // Valid during header phase only - 1=current request is a read data return input [127:0] sio_niu_data INPUT_EDGE verilog_node TDS_DUV_PATH.sio_niu_data" ; // Packet from SIO to Ethernet input [7:0] sio_niu_parity INPUT_EDGE verilog_node TDS_DUV_PATH.sio_niu_parity" ; // Packet parity from SIO to Ethernet } #endif // RAS Interface from NCU- #ifdef NIU_GATE interface ncu_smx_chk { input clk CLOCK verilog_node TDS_DUV_PATH.iol2clk"; input ncu_niu_ctag_uei INPUT_EDGE verilog_node TDS_DUV_PATH.ncu_niu_ctag_uei"; input ncu_niu_ctag_cei INPUT_EDGE verilog_node TDS_DUV_PATH.ncu_niu_ctag_cei"; input ncu_niu_d_pei INPUT_EDGE verilog_node TDS_DUV_PATH.ncu_niu_d_pei "; input niu_ncu_ctag_ue INPUT_EDGE verilog_node TDS_DUV_PATH.niu_ncu_ctag_ue"; input niu_ncu_ctag_ce INPUT_EDGE verilog_node TDS_DUV_PATH.niu_ncu_ctag_ce"; input niu_ncu_d_pe INPUT_EDGE verilog_node TDS_DUV_PATH.niu_ncu_d_pe "; } #else interface ncu_smx_chk { input clk CLOCK verilog_node TDS_DUV_PATH.niu_smx.niu_clk"; input ncu_niu_ctag_uei INPUT_EDGE verilog_node TDS_DUV_PATH.ncu_niu_ctag_uei"; input ncu_niu_ctag_cei INPUT_EDGE verilog_node TDS_DUV_PATH.ncu_niu_ctag_cei"; input ncu_niu_d_pei INPUT_EDGE verilog_node TDS_DUV_PATH.ncu_niu_d_pei "; input niu_ncu_ctag_ue INPUT_EDGE verilog_node TDS_DUV_PATH.niu_ncu_ctag_ue"; input niu_ncu_ctag_ce INPUT_EDGE verilog_node TDS_DUV_PATH.niu_ncu_ctag_ce"; input niu_ncu_d_pe INPUT_EDGE verilog_node TDS_DUV_PATH.niu_ncu_d_pe "; } #endif port niu_siu_chk_iface { clk; niu_reset_l; niu_sii_hdr_vld; niu_sii_reqbypass; niu_sii_datareq; niu_sii_data; niu_sii_parity; sii_niu_oqdq; sii_niu_bqdq; sio_niu_hdr_vld; sio_niu_datareq; sio_niu_data; sio_niu_parity; } bind niu_siu_chk_iface niu_siu_chk_pbind { clk niu_siu_chk.clk; niu_reset_l niu_siu_chk.niu_reset_l; niu_sii_hdr_vld niu_siu_chk.niu_sii_hdr_vld; niu_sii_reqbypass niu_siu_chk.niu_sii_reqbypass; niu_sii_datareq niu_siu_chk.niu_sii_datareq; niu_sii_data niu_siu_chk.niu_sii_data; niu_sii_parity niu_siu_chk.niu_sii_parity; sii_niu_oqdq niu_siu_chk.sii_niu_oqdq; sii_niu_bqdq niu_siu_chk.sii_niu_bqdq; sio_niu_hdr_vld niu_siu_chk.sio_niu_hdr_vld; sio_niu_datareq niu_siu_chk.sio_niu_datareq; sio_niu_data niu_siu_chk.sio_niu_data; sio_niu_parity niu_siu_chk.sio_niu_parity; } port ncu_smx_chk_iface { clk; ncu_niu_ctag_uei; ncu_niu_ctag_cei; ncu_niu_d_pei; niu_ncu_ctag_ue; niu_ncu_ctag_ce; niu_ncu_d_pe; } bind ncu_smx_chk_iface ncu_smx_chk_ras_pbind { clk ncu_smx_chk.clk ; ncu_niu_ctag_uei ncu_smx_chk.ncu_niu_ctag_uei; ncu_niu_ctag_cei ncu_smx_chk.ncu_niu_ctag_cei; ncu_niu_d_pei ncu_smx_chk.ncu_niu_d_pei ; niu_ncu_ctag_ue ncu_smx_chk.niu_ncu_ctag_ue ; niu_ncu_ctag_ce ncu_smx_chk.niu_ncu_ctag_ce ; niu_ncu_d_pe ncu_smx_chk.niu_ncu_d_pe ; }